Moving fp arithmetic insns to decodetree.

[PATCH v2 0/2] Moving fp arithmetic insns to decodetree.

Chinmay Rath posted 2 patches 1 month, 2 weeks ago

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git fetch https://github.com/patchew-project/qemu tags/patchew/20240315064422.737812-1-rathc@linux.ibm.com

Maintainers: Nicholas Piggin <npiggin@gmail.com>, Daniel Henrique Barboza <danielhb413@gmail.com>

target/ppc/helper.h                |  44 ++---
target/ppc/insn32.decode           |  42 +++++
target/ppc/fpu_helper.c            | 235 +++++++-----------------
target/ppc/translate/fp-impl.c.inc | 285 +++++++++++------------------
target/ppc/translate/fp-ops.c.inc  |  31 ----
5 files changed, 242 insertions(+), 395 deletions(-)

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[PATCH v2 0/2] Moving fp arithmetic insns to decodetree.

Posted by Chinmay Rath 1 month, 2 weeks ago

This patch series moves floating-point arithmetic instructions from
legacy to decodetree format. The first patch consolidates the common
behaviour of floating-point helper functions using macros, reducing
code duplication. The second patch moves all the floating arithmetic
instructions to decodetree.

Change log :
v2 : Addressed review comments on v1
v1 : https://lore.kernel.org/qemu-devel/20240307110318.170319-1-rathc@linux.ibm.com/

Chinmay Rath (2):
  target/ppc: Merge various fpu helpers
  target/ppc: Move floating-point arithmetic instructions to decodetree.

 target/ppc/helper.h                |  44 ++---
 target/ppc/insn32.decode           |  42 +++++
 target/ppc/fpu_helper.c            | 235 +++++++-----------------
 target/ppc/translate/fp-impl.c.inc | 285 +++++++++++------------------
 target/ppc/translate/fp-ops.c.inc  |  31 ----
 5 files changed, 242 insertions(+), 395 deletions(-)

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2.39.3