The following changes since commit 8f6330a807f2642dc2a3cdf33347aa28a4c00a87:

Merge tag 'pull-maintainer-updates-060324-1' of https://gitlab.com/stsquad/qemu into staging (2024-03-06 16:56:20 +0000)

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20240308

for you to fetch changes up to bbf6c6dbead82292a20951eb1204442a6b838de9:

target/arm: Move v7m-related code from cpu32.c into a separate file (2024-03-08 14:45:03 +0000)

* Implement FEAT_ECV

* STM32L4x5: Implement GPIO device

* Fix 32-bit SMOPA

* Refactor v7m related code from cpu32.c into its own file

* hw/rtc/sun4v-rtc: Relicense to GPLv2-or-later

Inès Varhol (3):

hw/gpio: Implement STM32L4x5 GPIO

hw/arm: Connect STM32L4x5 GPIO to STM32L4x5 SoC

tests/qtest: Add STM32L4x5 GPIO QTest testcase

Peter Maydell (9):

target/arm: Move some register related defines to internals.h

target/arm: Timer _EL02 registers UNDEF for E2H == 0

target/arm: use FIELD macro for CNTHCTL bit definitions

target/arm: Don't allow RES0 CNTHCTL_EL2 bits to be written

target/arm: Implement new FEAT_ECV trap bits

target/arm: Define CNTPCTSS_EL0 and CNTVCTSS_EL0

target/arm: Implement FEAT_ECV CNTPOFF_EL2 handling

target/arm: Enable FEAT_ECV for 'max' CPU

hw/rtc/sun4v-rtc: Relicense to GPLv2-or-later

Richard Henderson (1):

target/arm: Fix 32-bit SMOPA

target/arm: Move v7m-related code from cpu32.c into a separate file

MAINTAINERS | 1 +

docs/system/arm/b-l475e-iot01a.rst | 2 +-

docs/system/arm/emulation.rst | 1 +

include/hw/arm/stm32l4x5_soc.h | 2 +

include/hw/gpio/stm32l4x5_gpio.h | 71 +++++

include/hw/misc/stm32l4x5_syscfg.h | 3 +-

include/hw/rtc/sun4v-rtc.h | 2 +-

target/arm/cpu-features.h | 10 +

target/arm/cpu.h | 129 +--------

target/arm/internals.h | 151 ++++++++++

hw/arm/stm32l4x5_soc.c | 71 ++++-

hw/gpio/stm32l4x5_gpio.c | 477 ++++++++++++++++++++++++++++++++

hw/misc/stm32l4x5_syscfg.c | 1 +

hw/rtc/sun4v-rtc.c | 2 +-

target/arm/helper.c | 189 ++++++++++++-

target/arm/tcg/cpu-v7m.c | 290 +++++++++++++++++++

target/arm/tcg/cpu32.c | 261 ------------------

target/arm/tcg/cpu64.c | 1 +

target/arm/tcg/sme_helper.c | 77 +++---

tests/qtest/stm32l4x5_gpio-test.c | 551 +++++++++++++++++++++++++++++++++++++

tests/tcg/aarch64/sme-smopa-1.c | 47 ++++

tests/tcg/aarch64/sme-smopa-2.c | 54 ++++

hw/arm/Kconfig | 3 +-

hw/gpio/Kconfig | 3 +

hw/gpio/meson.build | 1 +

hw/gpio/trace-events | 6 +

target/arm/meson.build | 3 +

target/arm/tcg/meson.build | 3 +

target/arm/trace-events | 1 +

tests/qtest/meson.build | 3 +-

tests/tcg/aarch64/Makefile.target | 2 +-

31 files changed, 1962 insertions(+), 456 deletions(-)

create mode 100644 include/hw/gpio/stm32l4x5_gpio.h

create mode 100644 hw/gpio/stm32l4x5_gpio.c

create mode 100644 target/arm/tcg/cpu-v7m.c

create mode 100644 tests/qtest/stm32l4x5_gpio-test.c

create mode 100644 tests/tcg/aarch64/sme-smopa-1.c

create mode 100644 tests/tcg/aarch64/sme-smopa-2.c

From: Inès Varhol <ines.varhol@telecom-paris.fr>

Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>

Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>

Acked-by: Alistair Francis <alistair.francis@wdc.com>

Message-id: 20240305210444.310665-3-ines.varhol@telecom-paris.fr

include/hw/arm/stm32l4x5_soc.h | 2 +

include/hw/gpio/stm32l4x5_gpio.h | 1 +

include/hw/misc/stm32l4x5_syscfg.h | 3 +-

hw/arm/stm32l4x5_soc.c | 71 +++++++++++++++++++++++-------

hw/misc/stm32l4x5_syscfg.c | 1 +

hw/arm/Kconfig | 3 +-

6 files changed, 63 insertions(+), 18 deletions(-)

diff --git a/include/hw/arm/stm32l4x5_soc.h b/include/hw/arm/stm32l4x5_soc.h

--- a/include/hw/arm/stm32l4x5_soc.h

+++ b/include/hw/arm/stm32l4x5_soc.h

@@ -XXX,XX +XXX,XX @@

#include "hw/misc/stm32l4x5_syscfg.h"

#include "hw/misc/stm32l4x5_exti.h"

#include "hw/misc/stm32l4x5_rcc.h"

+#include "hw/gpio/stm32l4x5_gpio.h"

#include "qom/object.h"

#define TYPE_STM32L4X5_SOC "stm32l4x5-soc"

@@ -XXX,XX +XXX,XX @@ struct Stm32l4x5SocState {

OrIRQState exti_or_gates[NUM_EXTI_OR_GATES];

Stm32l4x5SyscfgState syscfg;

Stm32l4x5RccState rcc;

+ Stm32l4x5GpioState gpio[NUM_GPIOS];

MemoryRegion sram1;

MemoryRegion sram2;

diff --git a/include/hw/gpio/stm32l4x5_gpio.h b/include/hw/gpio/stm32l4x5_gpio.h

index XXXXXXX..XXXXXXX 100644

--- a/include/hw/gpio/stm32l4x5_gpio.h

+++ b/include/hw/gpio/stm32l4x5_gpio.h

@@ -XXX,XX +XXX,XX @@

#define TYPE_STM32L4X5_GPIO "stm32l4x5-gpio"

OBJECT_DECLARE_SIMPLE_TYPE(Stm32l4x5GpioState, STM32L4X5_GPIO)

+#define NUM_GPIOS 8

#define GPIO_NUM_PINS 16

struct Stm32l4x5GpioState {

diff --git a/include/hw/misc/stm32l4x5_syscfg.h b/include/hw/misc/stm32l4x5_syscfg.h

index XXXXXXX..XXXXXXX 100644

--- a/include/hw/misc/stm32l4x5_syscfg.h

+++ b/include/hw/misc/stm32l4x5_syscfg.h

@@ -XXX,XX +XXX,XX @@

#include "hw/sysbus.h"

#include "qom/object.h"

+#include "hw/gpio/stm32l4x5_gpio.h"

#define TYPE_STM32L4X5_SYSCFG "stm32l4x5-syscfg"

OBJECT_DECLARE_SIMPLE_TYPE(Stm32l4x5SyscfgState, STM32L4X5_SYSCFG)

-#define NUM_GPIOS 8

-#define GPIO_NUM_PINS 16

#define SYSCFG_NUM_EXTICR 4

struct Stm32l4x5SyscfgState {

diff --git a/hw/arm/stm32l4x5_soc.c b/hw/arm/stm32l4x5_soc.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/stm32l4x5_soc.c

+++ b/hw/arm/stm32l4x5_soc.c

@@ -XXX,XX +XXX,XX @@

#include "sysemu/sysemu.h"

#include "hw/or-irq.h"

#include "hw/arm/stm32l4x5_soc.h"

+#include "hw/gpio/stm32l4x5_gpio.h"

#include "hw/qdev-clock.h"

#include "hw/misc/unimp.h"

@@ -XXX,XX +XXX,XX @@ static const int exti_or_gate1_lines_in[EXTI_OR_GATE1_NUM_LINES_IN] = {

16, 35, 36, 37, 38,

};

+static const struct {

+ uint32_t addr;

+ uint32_t moder_reset;

+ uint32_t ospeedr_reset;

+ uint32_t pupdr_reset;

+} stm32l4x5_gpio_cfg[NUM_GPIOS] = {

+ { 0x48000000, 0xABFFFFFF, 0x0C000000, 0x64000000 },

+ { 0x48000400, 0xFFFFFEBF, 0x00000000, 0x00000100 },

+ { 0x48000800, 0xFFFFFFFF, 0x00000000, 0x00000000 },

+ { 0x48000C00, 0xFFFFFFFF, 0x00000000, 0x00000000 },

+ { 0x48001000, 0xFFFFFFFF, 0x00000000, 0x00000000 },

+ { 0x48001400, 0xFFFFFFFF, 0x00000000, 0x00000000 },

+ { 0x48001800, 0xFFFFFFFF, 0x00000000, 0x00000000 },

+ { 0x48001C00, 0x0000000F, 0x00000000, 0x00000000 },

+};

+

static void stm32l4x5_soc_initfn(Object *obj)

{

Stm32l4x5SocState *s = STM32L4X5_SOC(obj);

@@ -XXX,XX +XXX,XX @@ static void stm32l4x5_soc_initfn(Object *obj)

}

object_initialize_child(obj, "syscfg", &s->syscfg, TYPE_STM32L4X5_SYSCFG);

object_initialize_child(obj, "rcc", &s->rcc, TYPE_STM32L4X5_RCC);

+

+ for (unsigned i = 0; i < NUM_GPIOS; i++) {

+ g_autofree char *name = g_strdup_printf("gpio%c", 'a' + i);

+ object_initialize_child(obj, name, &s->gpio[i], TYPE_STM32L4X5_GPIO);

+ }

}

static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)

@@ -XXX,XX +XXX,XX @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)

Stm32l4x5SocState *s = STM32L4X5_SOC(dev_soc);

const Stm32l4x5SocClass *sc = STM32L4X5_SOC_GET_CLASS(dev_soc);

MemoryRegion *system_memory = get_system_memory();

- DeviceState *armv7m;

+ DeviceState *armv7m, *dev;

SysBusDevice *busdev;

+ uint32_t pin_index;

if (!memory_region_init_rom(&s->flash, OBJECT(dev_soc), "flash",

sc->flash_size, errp)) {

@@ -XXX,XX +XXX,XX @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)

+ /* GPIOs */

+ for (unsigned i = 0; i < NUM_GPIOS; i++) {

+ g_autofree char *name = g_strdup_printf("%c", 'A' + i);

+ dev = DEVICE(&s->gpio[i]);

+ qdev_prop_set_string(dev, "name", name);

+ qdev_prop_set_uint32(dev, "mode-reset",

+ stm32l4x5_gpio_cfg[i].moder_reset);

+ qdev_prop_set_uint32(dev, "ospeed-reset",

+ stm32l4x5_gpio_cfg[i].ospeedr_reset);

+ qdev_prop_set_uint32(dev, "pupd-reset",

+ stm32l4x5_gpio_cfg[i].pupdr_reset);

+ busdev = SYS_BUS_DEVICE(&s->gpio[i]);

+ g_free(name);

+ name = g_strdup_printf("gpio%c-out", 'a' + i);

+ qdev_connect_clock_in(DEVICE(&s->gpio[i]), "clk",

+ qdev_get_clock_out(DEVICE(&(s->rcc)), name));

+ if (!sysbus_realize(busdev, errp)) {

+ return;

+ }

+ sysbus_mmio_map(busdev, 0, stm32l4x5_gpio_cfg[i].addr);

+ }

+

/* System configuration controller */

busdev = SYS_BUS_DEVICE(&s->syscfg);

if (!sysbus_realize(busdev, errp)) {

return;

}

sysbus_mmio_map(busdev, 0, SYSCFG_ADDR);

- /*

- * TODO: when the GPIO device is implemented, connect it

- * to SYCFG using `qdev_connect_gpio_out`, NUM_GPIOS and

- * GPIO_NUM_PINS.

- */

+

+ for (unsigned i = 0; i < NUM_GPIOS; i++) {

+ for (unsigned j = 0; j < GPIO_NUM_PINS; j++) {

+ pin_index = GPIO_NUM_PINS * i + j;

+ qdev_connect_gpio_out(DEVICE(&s->gpio[i]), j,

+ qdev_get_gpio_in(DEVICE(&s->syscfg),

+ pin_index));

+ }

+ }

/* EXTI device */

busdev = SYS_BUS_DEVICE(&s->exti);

@@ -XXX,XX +XXX,XX @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)

}

}

- for (unsigned i = 0; i < 16; i++) {

+ for (unsigned i = 0; i < GPIO_NUM_PINS; i++) {

qdev_connect_gpio_out(DEVICE(&s->syscfg), i,

qdev_get_gpio_in(DEVICE(&s->exti), i));

}

@@ -XXX,XX +XXX,XX @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)

/* RESERVED: 0x40024400, 0x7FDBC00 */

/* AHB2 BUS */

- create_unimplemented_device("GPIOA", 0x48000000, 0x400);

- create_unimplemented_device("GPIOB", 0x48000400, 0x400);

- create_unimplemented_device("GPIOC", 0x48000800, 0x400);

- create_unimplemented_device("GPIOD", 0x48000C00, 0x400);

- create_unimplemented_device("GPIOE", 0x48001000, 0x400);

- create_unimplemented_device("GPIOF", 0x48001400, 0x400);

- create_unimplemented_device("GPIOG", 0x48001800, 0x400);

- create_unimplemented_device("GPIOH", 0x48001C00, 0x400);

/* RESERVED: 0x48002000, 0x7FDBC00 */

create_unimplemented_device("OTG_FS", 0x50000000, 0x40000);

create_unimplemented_device("ADC", 0x50040000, 0x400);

diff --git a/hw/misc/stm32l4x5_syscfg.c b/hw/misc/stm32l4x5_syscfg.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/misc/stm32l4x5_syscfg.c

+++ b/hw/misc/stm32l4x5_syscfg.c

@@ -XXX,XX +XXX,XX @@

#include "hw/irq.h"

#include "migration/vmstate.h"

#include "hw/misc/stm32l4x5_syscfg.h"

+#include "hw/gpio/stm32l4x5_gpio.h"

#define SYSCFG_MEMRMP 0x00

#define SYSCFG_CFGR1 0x04

diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/Kconfig

+++ b/hw/arm/Kconfig

@@ -XXX,XX +XXX,XX @@ config STM32L4X5_SOC

bool

select ARM_V7M

select OR_IRQ

- select STM32L4X5_SYSCFG

select STM32L4X5_EXTI

+ select STM32L4X5_SYSCFG

select STM32L4X5_RCC

+ select STM32L4X5_GPIO

config XLNX_ZYNQMP_ARM

bool

2.34.1

From: Inès Varhol <ines.varhol@telecom-paris.fr>

Features supported :

- the 8 STM32L4x5 GPIOs are initialized with their reset values

(except IDR, see below)

- input mode : setting a pin in input mode "externally" (using input

irqs) results in an out irq (transmitted to SYSCFG)

- output mode : setting a bit in ODR sets the corresponding out irq

(if this line is configured in output mode)

- pull-up, pull-down

- push-pull, open-drain

Difference with the real GPIOs :

- Alternate Function and Analog mode aren't implemented :

pins in AF/Analog behave like pins in input mode

- floating pins stay at their last value

- register IDR reset values differ from the real one :

values are coherent with the other registers reset values

and the fact that AF/Analog modes aren't implemented

- setting I/O output speed isn't supported

- locking port bits isn't supported

- ADC function isn't supported

- GPIOH has 16 pins instead of 2 pins

- writing to registers LCKR, AFRL, AFRH and ASCR is ineffective

Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>

Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>

Acked-by: Alistair Francis <alistair.francis@wdc.com>

Message-id: 20240305210444.310665-2-ines.varhol@telecom-paris.fr

MAINTAINERS | 1 +

docs/system/arm/b-l475e-iot01a.rst | 2 +-

include/hw/gpio/stm32l4x5_gpio.h | 70 +++++

hw/gpio/stm32l4x5_gpio.c | 477 +++++++++++++++++++++++++++++

hw/gpio/Kconfig | 3 +

hw/gpio/meson.build | 1 +

hw/gpio/trace-events | 6 +

7 files changed, 559 insertions(+), 1 deletion(-)

create mode 100644 include/hw/gpio/stm32l4x5_gpio.h

create mode 100644 hw/gpio/stm32l4x5_gpio.c

@@ -XXX,XX +XXX,XX @@ F: hw/arm/stm32l4x5_soc.c

F: hw/misc/stm32l4x5_exti.c

F: hw/misc/stm32l4x5_syscfg.c

F: hw/misc/stm32l4x5_rcc.c

+F: hw/gpio/stm32l4x5_gpio.c

F: include/hw/*/stm32l4x5_*.h

B-L475E-IOT01A IoT Node

diff --git a/docs/system/arm/b-l475e-iot01a.rst b/docs/system/arm/b-l475e-iot01a.rst

index XXXXXXX..XXXXXXX 100644

--- a/docs/system/arm/b-l475e-iot01a.rst

+++ b/docs/system/arm/b-l475e-iot01a.rst

@@ -XXX,XX +XXX,XX @@ Currently B-L475E-IOT01A machine's only supports the following devices:

- STM32L4x5 EXTI (Extended interrupts and events controller)

- STM32L4x5 SYSCFG (System configuration controller)

- STM32L4x5 RCC (Reset and clock control)

+- STM32L4x5 GPIOs (General-purpose I/Os)

Missing devices

"""""""""""""""

@@ -XXX,XX +XXX,XX @@ Missing devices

The B-L475E-IOT01A does *not* support the following devices:

- Serial ports (UART)

-- General-purpose I/Os (GPIO)

- Analog to Digital Converter (ADC)

- SPI controller

- Timer controller (TIMER)

diff --git a/include/hw/gpio/stm32l4x5_gpio.h b/include/hw/gpio/stm32l4x5_gpio.h

new file mode 100644

index XXXXXXX..XXXXXXX

--- /dev/null

+++ b/include/hw/gpio/stm32l4x5_gpio.h

@@ -XXX,XX +XXX,XX @@

+/*

+ * STM32L4x5 GPIO (General Purpose Input/Ouput)

+ *

+ * Copyright (c) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>

+ * Copyright (c) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>

+ *

+ * SPDX-License-Identifier: GPL-2.0-or-later

+ *

+ * This work is licensed under the terms of the GNU GPL, version 2 or later.

+ * See the COPYING file in the top-level directory.

+ */

+

+/*

+ * The reference used is the STMicroElectronics RM0351 Reference manual

+ * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.

+ * https://www.st.com/en/microcontrollers-microprocessors/stm32l4x5/documentation.html

+ */

+

+#ifndef HW_STM32L4X5_GPIO_H

+#define HW_STM32L4X5_GPIO_H

+

+#include "hw/sysbus.h"

+#include "qom/object.h"

+

+#define TYPE_STM32L4X5_GPIO "stm32l4x5-gpio"

+OBJECT_DECLARE_SIMPLE_TYPE(Stm32l4x5GpioState, STM32L4X5_GPIO)

+

+#define GPIO_NUM_PINS 16

+

+struct Stm32l4x5GpioState {

+ SysBusDevice parent_obj;

+

+ MemoryRegion mmio;

+

+ /* GPIO registers */

+ uint32_t moder;

+ uint32_t otyper;

+ uint32_t ospeedr;

+ uint32_t pupdr;

+ uint32_t idr;

+ uint32_t odr;

+ uint32_t lckr;

+ uint32_t afrl;

+ uint32_t afrh;

+ uint32_t ascr;

+

+ /* GPIO registers reset values */

+ uint32_t moder_reset;

+ uint32_t ospeedr_reset;

+ uint32_t pupdr_reset;

+

+ /*

+ * External driving of pins.

+ * The pins can be set externally through the device

+ * anonymous input GPIOs lines under certain conditions.

+ * The pin must not be in push-pull output mode,

+ * and can't be set high in open-drain mode.

+ * Pins driven externally and configured to

+ * output mode will in general be "disconnected"

+ * (see `get_gpio_pinmask_to_disconnect()`)

+ */

+ uint16_t disconnected_pins;

+ uint16_t pins_connected_high;

+

+ char *name;

+ Clock *clk;

+ qemu_irq pin[GPIO_NUM_PINS];

+};

+

+#endif

diff --git a/hw/gpio/stm32l4x5_gpio.c b/hw/gpio/stm32l4x5_gpio.c

new file mode 100644

index XXXXXXX..XXXXXXX

--- /dev/null

+++ b/hw/gpio/stm32l4x5_gpio.c

@@ -XXX,XX +XXX,XX @@

+/*

+ * STM32L4x5 GPIO (General Purpose Input/Ouput)

+ *

+ * Copyright (c) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>

+ * Copyright (c) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>

+ *

+ * SPDX-License-Identifier: GPL-2.0-or-later

+ *

+ * This work is licensed under the terms of the GNU GPL, version 2 or later.

+ * See the COPYING file in the top-level directory.

+ */

+

+/*

+ * The reference used is the STMicroElectronics RM0351 Reference manual

+ * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.

+ * https://www.st.com/en/microcontrollers-microprocessors/stm32l4x5/documentation.html

+ */

+

+#include "qemu/osdep.h"

+#include "qemu/log.h"

+#include "hw/gpio/stm32l4x5_gpio.h"

+#include "hw/irq.h"

+#include "hw/qdev-clock.h"

+#include "hw/qdev-properties.h"

+#include "qapi/visitor.h"

+#include "qapi/error.h"

+#include "migration/vmstate.h"

+#include "trace.h"

+

+#define GPIO_MODER 0x00

+#define GPIO_OTYPER 0x04

+#define GPIO_OSPEEDR 0x08

+#define GPIO_PUPDR 0x0C

+#define GPIO_IDR 0x10

+#define GPIO_ODR 0x14

+#define GPIO_BSRR 0x18

+#define GPIO_LCKR 0x1C

+#define GPIO_AFRL 0x20

+#define GPIO_AFRH 0x24

+#define GPIO_BRR 0x28

+#define GPIO_ASCR 0x2C

+

+/* 0b11111111_11111111_00000000_00000000 */

+#define RESERVED_BITS_MASK 0xFFFF0000

+

+static void update_gpio_idr(Stm32l4x5GpioState *s);

+

+static bool is_pull_up(Stm32l4x5GpioState *s, unsigned pin)

+{

+ return extract32(s->pupdr, 2 * pin, 2) == 1;

+}

+

+static bool is_pull_down(Stm32l4x5GpioState *s, unsigned pin)

+{

+ return extract32(s->pupdr, 2 * pin, 2) == 2;

+}

+

+static bool is_output(Stm32l4x5GpioState *s, unsigned pin)

+{

+ return extract32(s->moder, 2 * pin, 2) == 1;

+}

+

+static bool is_open_drain(Stm32l4x5GpioState *s, unsigned pin)

+{

+ return extract32(s->otyper, pin, 1) == 1;

+}

+

+static bool is_push_pull(Stm32l4x5GpioState *s, unsigned pin)

+{

+ return extract32(s->otyper, pin, 1) == 0;

+}

+

+static void stm32l4x5_gpio_reset_hold(Object *obj)

+{

+ Stm32l4x5GpioState *s = STM32L4X5_GPIO(obj);

+

+ s->moder = s->moder_reset;

+ s->otyper = 0x00000000;

+ s->ospeedr = s->ospeedr_reset;

+ s->pupdr = s->pupdr_reset;

+ s->idr = 0x00000000;

+ s->odr = 0x00000000;

+ s->lckr = 0x00000000;

+ s->afrl = 0x00000000;

+ s->afrh = 0x00000000;

+ s->ascr = 0x00000000;

+

+ s->disconnected_pins = 0xFFFF;

+ s->pins_connected_high = 0x0000;

+ update_gpio_idr(s);

+}

+

+static void stm32l4x5_gpio_set(void *opaque, int line, int level)

+{

+ Stm32l4x5GpioState *s = opaque;

+ /*

+ * The pin isn't set if line is configured in output mode

+ * except if level is 0 and the output is open-drain.

+ * This way there will be no short-circuit prone situations.

+ */

+ if (is_output(s, line) && !(is_open_drain(s, line) && (level == 0))) {

+ qemu_log_mask(LOG_GUEST_ERROR, "Line %d can't be driven externally\n",

+ line);

+ return;

+ }

+

+ s->disconnected_pins &= ~(1 << line);

+ if (level) {

+ s->pins_connected_high |= (1 << line);

+ } else {

+ s->pins_connected_high &= ~(1 << line);

+ }

+ trace_stm32l4x5_gpio_pins(s->name, s->disconnected_pins,

+ s->pins_connected_high);

+ update_gpio_idr(s);

+}

+

+

+static void update_gpio_idr(Stm32l4x5GpioState *s)

+{

+ uint32_t new_idr_mask = 0;

+ uint32_t new_idr = s->odr;

+ uint32_t old_idr = s->idr;

+ int new_pin_state, old_pin_state;

+

+ for (int i = 0; i < GPIO_NUM_PINS; i++) {

+ if (is_output(s, i)) {

+ if (is_push_pull(s, i)) {

+ new_idr_mask |= (1 << i);

+ } else if (!(s->odr & (1 << i))) {

+ /* open-drain ODR 0 */

+ new_idr_mask |= (1 << i);

+ /* open-drain ODR 1 */

+ } else if (!(s->disconnected_pins & (1 << i)) &&

+ !(s->pins_connected_high & (1 << i))) {

+ /* open-drain ODR 1 with pin connected low */

+ new_idr_mask |= (1 << i);

+ new_idr &= ~(1 << i);

+ /* open-drain ODR 1 with unactive pin */

+ } else if (is_pull_up(s, i)) {

+ new_idr_mask |= (1 << i);

+ } else if (is_pull_down(s, i)) {

+ new_idr_mask |= (1 << i);

+ new_idr &= ~(1 << i);

+ }

+ /*

+ * The only case left is for open-drain ODR 1

+ * with unactive pin without pull-up or pull-down :

+ * the value is floating.

+ */

+ /* input or analog mode with connected pin */

+ } else if (!(s->disconnected_pins & (1 << i))) {

+ if (s->pins_connected_high & (1 << i)) {

+ /* pin high */

+ new_idr_mask |= (1 << i);

+ new_idr |= (1 << i);

+ } else {

+ /* pin low */

+ new_idr_mask |= (1 << i);

+ new_idr &= ~(1 << i);

+ }

+ /* input or analog mode with disconnected pin */

+ } else {

+ if (is_pull_up(s, i)) {

+ /* pull-up */

+ new_idr_mask |= (1 << i);

+ new_idr |= (1 << i);

+ } else if (is_pull_down(s, i)) {

+ /* pull-down */

+ new_idr_mask |= (1 << i);

+ new_idr &= ~(1 << i);

+ }

+ /*

+ * The only case left is for a disconnected pin

+ * without pull-up or pull-down :

+ * the value is floating.

+ */

+ }

+ }

+

+ s->idr = (old_idr & ~new_idr_mask) | (new_idr & new_idr_mask);

+ trace_stm32l4x5_gpio_update_idr(s->name, old_idr, s->idr);

+

+ for (int i = 0; i < GPIO_NUM_PINS; i++) {

+ if (new_idr_mask & (1 << i)) {

+ new_pin_state = (new_idr & (1 << i)) > 0;

+ old_pin_state = (old_idr & (1 << i)) > 0;

+ if (new_pin_state > old_pin_state) {

+ qemu_irq_raise(s->pin[i]);

+ } else if (new_pin_state < old_pin_state) {

+ qemu_irq_lower(s->pin[i]);

+ }

+ }

+ }

+}

+

+/*

+ * Return mask of pins that are both configured in output

+ * mode and externally driven (except pins in open-drain

+ * mode externally set to 0).

+ */

+static uint32_t get_gpio_pinmask_to_disconnect(Stm32l4x5GpioState *s)

+{

+ uint32_t pins_to_disconnect = 0;

+ for (int i = 0; i < GPIO_NUM_PINS; i++) {

+ /* for each connected pin in output mode */

+ if (!(s->disconnected_pins & (1 << i)) && is_output(s, i)) {

+ /* if either push-pull or high level */

+ if (is_push_pull(s, i) || s->pins_connected_high & (1 << i)) {

+ pins_to_disconnect |= (1 << i);

+ qemu_log_mask(LOG_GUEST_ERROR,

+ "Line %d can't be driven externally\n",

+ i);

+ }

+ }

+ }

+ return pins_to_disconnect;

+}

+

+/*

+ * Set field `disconnected_pins` and call `update_gpio_idr()`

+ */

+static void disconnect_gpio_pins(Stm32l4x5GpioState *s, uint16_t lines)

+{

+ s->disconnected_pins |= lines;

+ trace_stm32l4x5_gpio_pins(s->name, s->disconnected_pins,

+ s->pins_connected_high);

+ update_gpio_idr(s);

+}

+

+static void disconnected_pins_set(Object *obj, Visitor *v,

+ const char *name, void *opaque, Error **errp)

+{

+ Stm32l4x5GpioState *s = STM32L4X5_GPIO(obj);

+ uint16_t value;

+ if (!visit_type_uint16(v, name, &value, errp)) {

+ return;

+ }

+ disconnect_gpio_pins(s, value);

+}

+

+static void disconnected_pins_get(Object *obj, Visitor *v,

+ const char *name, void *opaque, Error **errp)

+{

+ visit_type_uint16(v, name, (uint16_t *)opaque, errp);

+}

+

+static void clock_freq_get(Object *obj, Visitor *v,

+ const char *name, void *opaque, Error **errp)

+{

+ Stm32l4x5GpioState *s = STM32L4X5_GPIO(obj);

+ uint32_t clock_freq_hz = clock_get_hz(s->clk);

+ visit_type_uint32(v, name, &clock_freq_hz, errp);

+}

+

+static void stm32l4x5_gpio_write(void *opaque, hwaddr addr,

+ uint64_t val64, unsigned int size)

+{

+ Stm32l4x5GpioState *s = opaque;

+

+ uint32_t value = val64;

+ trace_stm32l4x5_gpio_write(s->name, addr, val64);

+

+ switch (addr) {

+ case GPIO_MODER:

+ s->moder = value;

+ disconnect_gpio_pins(s, get_gpio_pinmask_to_disconnect(s));

+ qemu_log_mask(LOG_UNIMP,

+ "%s: Analog and AF modes aren't supported\n\

+ Analog and AF mode behave like input mode\n",

+ __func__);

+ return;

+ case GPIO_OTYPER:

+ s->otyper = value & ~RESERVED_BITS_MASK;

+ disconnect_gpio_pins(s, get_gpio_pinmask_to_disconnect(s));

+ return;

+ case GPIO_OSPEEDR:

+ qemu_log_mask(LOG_UNIMP,

+ "%s: Changing I/O output speed isn't supported\n\

+ I/O speed is already maximal\n",

+ __func__);

+ s->ospeedr = value;

+ return;

+ case GPIO_PUPDR:

+ s->pupdr = value;

+ update_gpio_idr(s);

+ return;

+ case GPIO_IDR:

+ qemu_log_mask(LOG_UNIMP,

+ "%s: GPIO->IDR is read-only\n",

+ __func__);

+ return;

+ case GPIO_ODR:

+ s->odr = value & ~RESERVED_BITS_MASK;

+ update_gpio_idr(s);

+ return;

+ case GPIO_BSRR: {

+ uint32_t bits_to_reset = (value & RESERVED_BITS_MASK) >> GPIO_NUM_PINS;

+ uint32_t bits_to_set = value & ~RESERVED_BITS_MASK;

+ /* If both BSx and BRx are set, BSx has priority.*/

+ s->odr &= ~bits_to_reset;

+ s->odr |= bits_to_set;

+ update_gpio_idr(s);

+ return;

+ }

+ case GPIO_LCKR:

+ qemu_log_mask(LOG_UNIMP,

+ "%s: Locking port bits configuration isn't supported\n",

+ __func__);

+ s->lckr = value & ~RESERVED_BITS_MASK;

+ return;

+ case GPIO_AFRL:

+ qemu_log_mask(LOG_UNIMP,

+ "%s: Alternate functions aren't supported\n",

+ __func__);

+ s->afrl = value;

+ return;

+ case GPIO_AFRH:

+ qemu_log_mask(LOG_UNIMP,

+ "%s: Alternate functions aren't supported\n",

+ __func__);

+ s->afrh = value;

+ return;

+ case GPIO_BRR: {

+ uint32_t bits_to_reset = value & ~RESERVED_BITS_MASK;

+ s->odr &= ~bits_to_reset;

+ update_gpio_idr(s);

+ return;

+ }

+ case GPIO_ASCR:

+ qemu_log_mask(LOG_UNIMP,

+ "%s: ADC function isn't supported\n",

+ __func__);

+ s->ascr = value & ~RESERVED_BITS_MASK;

+ return;

+ default:

+ qemu_log_mask(LOG_GUEST_ERROR,

+ "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, addr);

+ }

+}

+

+static uint64_t stm32l4x5_gpio_read(void *opaque, hwaddr addr,

+ unsigned int size)

+{

+ Stm32l4x5GpioState *s = opaque;

+

+ trace_stm32l4x5_gpio_read(s->name, addr);

+

+ switch (addr) {

+ case GPIO_MODER:

+ return s->moder;

+ case GPIO_OTYPER:

+ return s->otyper;

+ case GPIO_OSPEEDR:

+ return s->ospeedr;

+ case GPIO_PUPDR:

+ return s->pupdr;

+ case GPIO_IDR:

+ return s->idr;

+ case GPIO_ODR:

+ return s->odr;

+ case GPIO_BSRR:

+ return 0;

+ case GPIO_LCKR:

+ return s->lckr;

+ case GPIO_AFRL:

+ return s->afrl;

+ case GPIO_AFRH:

+ return s->afrh;

+ case GPIO_BRR:

+ return 0;

+ case GPIO_ASCR:

+ return s->ascr;

+ default:

+ qemu_log_mask(LOG_GUEST_ERROR,

+ "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, addr);

+ return 0;

+ }

+}

+

+static const MemoryRegionOps stm32l4x5_gpio_ops = {

+ .read = stm32l4x5_gpio_read,

+ .write = stm32l4x5_gpio_write,

+ .endianness = DEVICE_NATIVE_ENDIAN,

+ .impl = {

+ .min_access_size = 4,

+ .max_access_size = 4,

+ .unaligned = false,

+ },

+ .valid = {

+ .min_access_size = 4,

+ .max_access_size = 4,

+ .unaligned = false,

+ },

+};

+

+static void stm32l4x5_gpio_init(Object *obj)

+{

+ Stm32l4x5GpioState *s = STM32L4X5_GPIO(obj);

+

+ memory_region_init_io(&s->mmio, obj, &stm32l4x5_gpio_ops, s,

+ TYPE_STM32L4X5_GPIO, 0x400);

+

+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);

+

+ qdev_init_gpio_out(DEVICE(obj), s->pin, GPIO_NUM_PINS);

+ qdev_init_gpio_in(DEVICE(obj), stm32l4x5_gpio_set, GPIO_NUM_PINS);

+

+ s->clk = qdev_init_clock_in(DEVICE(s), "clk", NULL, s, 0);

+

+ object_property_add(obj, "disconnected-pins", "uint16",

+ disconnected_pins_get, disconnected_pins_set,

+ NULL, &s->disconnected_pins);

+ object_property_add(obj, "clock-freq-hz", "uint32",

+ clock_freq_get, NULL, NULL, NULL);

+}

+

+static void stm32l4x5_gpio_realize(DeviceState *dev, Error **errp)

+{

+ Stm32l4x5GpioState *s = STM32L4X5_GPIO(dev);

+ if (!clock_has_source(s->clk)) {

+ error_setg(errp, "GPIO: clk input must be connected");

+ return;

+ }

+}

+

+static const VMStateDescription vmstate_stm32l4x5_gpio = {

+ .name = TYPE_STM32L4X5_GPIO,

+ .version_id = 1,

+ .minimum_version_id = 1,

+ .fields = (VMStateField[]){

+ VMSTATE_UINT32(moder, Stm32l4x5GpioState),

+ VMSTATE_UINT32(otyper, Stm32l4x5GpioState),

+ VMSTATE_UINT32(ospeedr, Stm32l4x5GpioState),

+ VMSTATE_UINT32(pupdr, Stm32l4x5GpioState),

+ VMSTATE_UINT32(idr, Stm32l4x5GpioState),

+ VMSTATE_UINT32(odr, Stm32l4x5GpioState),

+ VMSTATE_UINT32(lckr, Stm32l4x5GpioState),

+ VMSTATE_UINT32(afrl, Stm32l4x5GpioState),

+ VMSTATE_UINT32(afrh, Stm32l4x5GpioState),

+ VMSTATE_UINT32(ascr, Stm32l4x5GpioState),

+ VMSTATE_UINT16(disconnected_pins, Stm32l4x5GpioState),

+ VMSTATE_UINT16(pins_connected_high, Stm32l4x5GpioState),

+ VMSTATE_END_OF_LIST()

+ }

+};

+

+static Property stm32l4x5_gpio_properties[] = {

+ DEFINE_PROP_STRING("name", Stm32l4x5GpioState, name),

+ DEFINE_PROP_UINT32("mode-reset", Stm32l4x5GpioState, moder_reset, 0),

+ DEFINE_PROP_UINT32("ospeed-reset", Stm32l4x5GpioState, ospeedr_reset, 0),

+ DEFINE_PROP_UINT32("pupd-reset", Stm32l4x5GpioState, pupdr_reset, 0),

+ DEFINE_PROP_END_OF_LIST(),

+};

+

+static void stm32l4x5_gpio_class_init(ObjectClass *klass, void *data)

+{

+ DeviceClass *dc = DEVICE_CLASS(klass);

+ ResettableClass *rc = RESETTABLE_CLASS(klass);

+

+ device_class_set_props(dc, stm32l4x5_gpio_properties);

+ dc->vmsd = &vmstate_stm32l4x5_gpio;

+ dc->realize = stm32l4x5_gpio_realize;

+ rc->phases.hold = stm32l4x5_gpio_reset_hold;

+}

+

+static const TypeInfo stm32l4x5_gpio_types[] = {

+ {

+ .name = TYPE_STM32L4X5_GPIO,

+ .parent = TYPE_SYS_BUS_DEVICE,

+ .instance_size = sizeof(Stm32l4x5GpioState),

+ .instance_init = stm32l4x5_gpio_init,

+ .class_init = stm32l4x5_gpio_class_init,

+ },

+};

+

+DEFINE_TYPES(stm32l4x5_gpio_types)

diff --git a/hw/gpio/Kconfig b/hw/gpio/Kconfig

index XXXXXXX..XXXXXXX 100644

--- a/hw/gpio/Kconfig

+++ b/hw/gpio/Kconfig

@@ -XXX,XX +XXX,XX @@ config GPIO_PWR

config SIFIVE_GPIO

bool

+

+config STM32L4X5_GPIO

+ bool

diff --git a/hw/gpio/meson.build b/hw/gpio/meson.build

index XXXXXXX..XXXXXXX 100644

--- a/hw/gpio/meson.build

+++ b/hw/gpio/meson.build

@@ -XXX,XX +XXX,XX @@ system_ss.add(when: 'CONFIG_RASPI', if_true: files(

'bcm2835_gpio.c',

'bcm2838_gpio.c'

))

+system_ss.add(when: 'CONFIG_STM32L4X5_SOC', if_true: files('stm32l4x5_gpio.c'))

system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_gpio.c'))

system_ss.add(when: 'CONFIG_SIFIVE_GPIO', if_true: files('sifive_gpio.c'))

diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events

index XXXXXXX..XXXXXXX 100644

--- a/hw/gpio/trace-events

+++ b/hw/gpio/trace-events

@@ -XXX,XX +XXX,XX @@ sifive_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " val

# aspeed_gpio.c

aspeed_gpio_read(uint64_t offset, uint64_t value) "offset: 0x%" PRIx64 " value 0x%" PRIx64

aspeed_gpio_write(uint64_t offset, uint64_t value) "offset: 0x%" PRIx64 " value 0x%" PRIx64

+

+# stm32l4x5_gpio.c

+stm32l4x5_gpio_read(char *gpio, uint64_t addr) "GPIO%s addr: 0x%" PRIx64 " "

+stm32l4x5_gpio_write(char *gpio, uint64_t addr, uint64_t data) "GPIO%s addr: 0x%" PRIx64 " val: 0x%" PRIx64 ""

+stm32l4x5_gpio_update_idr(char *gpio, uint32_t old_idr, uint32_t new_idr) "GPIO%s from: 0x%x to: 0x%x"

+stm32l4x5_gpio_pins(char *gpio, uint16_t disconnected, uint16_t high) "GPIO%s disconnected pins: 0x%x levels: 0x%x"

2.34.1

When ID_AA64MMFR0_EL1.ECV is 0b0010, a new register CNTPOFF_EL2 is

implemented. This is similar to the existing CNTVOFF_EL2, except

that it controls a hypervisor-adjustable offset made to the physical

counter and timer.

Implement the handling for this register, which includes control/trap

bits in SCR_EL3 and CNTHCTL_EL2.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20240301183219.2424889-8-peter.maydell@linaro.org

target/arm/cpu-features.h | 5 +++

target/arm/cpu.h | 1 +

target/arm/helper.c | 68 +++++++++++++++++++++++++++++++++++++--

target/arm/trace-events | 1 +

4 files changed, 73 insertions(+), 2 deletions(-)

@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)

if (cpu_isar_feature(aa64_rme, cpu)) {

valid_mask |= SCR_NSE | SCR_GPF;

}

+ if (cpu_isar_feature(aa64_ecv, cpu)) {

+ valid_mask |= SCR_ECVEN;

+ }

} else {

valid_mask &= ~(SCR_RW | SCR_ST);

if (cpu_isar_feature(aa32_ras, cpu)) {

@@ -XXX,XX +XXX,XX @@ void gt_rme_post_el_change(ARMCPU *cpu, void *ignored)

gt_update_irq(cpu, GTIMER_PHYS);

+static uint64_t gt_phys_raw_cnt_offset(CPUARMState *env)

+ if ((env->cp15.scr_el3 & SCR_ECVEN) &&

+ FIELD_EX64(env->cp15.cnthctl_el2, CNTHCTL, ECV) &&

+ arm_is_el2_enabled(env) &&

+ (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {

+ return env->cp15.cntpoff_el2;

uint64_t offset = timeridx == GTIMER_VIRT ?

- cpu->env.cp15.cntvoff_el2 : 0;

+ cpu->env.cp15.cntvoff_el2 : gt_phys_raw_cnt_offset(&cpu->env);

2.34.1

For FEAT_ECV, new registers CNTPCTSS_EL0 and CNTVCTSS_EL0 are

defined, which are "self-synchronized" views of the physical and

virtual counts as seen in the CNTPCT_EL0 and CNTVCT_EL0 registers

(meaning that no barriers are needed around accesses to them to

ensure that reads of them do not occur speculatively and out-of-order

with other instructions).