[PULL 00/34] riscv-to-apply queue
[PULL 00/28] riscv-to-apply queue
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The following changes since commit 8f6330a807f2642dc2a3cdf33347aa28a4c00a87:
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The following changes since commit ad10b4badc1dd5b28305f9b9f1168cf0aa3ae946:
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Merge tag 'pull-maintainer-updates-060324-1' of https://gitlab.com/stsquad/qemu into staging (2024-03-06 16:56:20 +0000)
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Merge tag 'pull-error-2024-05-27' of https://repo.or.cz/qemu/armbru into staging (2024-05-27 06:40:42 -0700)
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are available in the Git repository at:
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are available in the Git repository at:
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https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20240308-1
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https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20240528
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for you to fetch changes up to 301876597112218c1e465ecc2b2fef6b27d5c27b:
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for you to fetch changes up to 1806da76cb81088ea026ca3441551782b850e393:
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target/riscv: fix ACPI MCFG table (2024-03-08 21:00:37 +1000)
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target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR (2024-05-28 12:20:27 +1000)
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----------------------------------------------------------------
13
----------------------------------------------------------------
14
RISC-V PR for 9.0
14
RISC-V PR for 9.1
15
15
16
* Update $ra with current $pc in trans_cm_jalt
16
* APLICs add child earlier than realize
17
* Enable SPCR for SCPI virt machine
17
* Fix exposure of Zkr
18
* Allow large kernels to boot by moving the initrd further away in RAM
18
* Raise exceptions on wrs.nto
19
* Sync hwprobe keys with kernel
19
* Implement SBI debug console (DBCN) calls for KVM
20
* Named features riscv,isa, 'svade' rework
20
* Support 64-bit addresses for initrd
21
* FIX xATP_MODE validation
21
* Change RISCV_EXCP_SEMIHOST exception number to 63
22
* Add missing include guard in pmu.h
22
* Tolerate KVM disable ext errors
23
* Add SRAT and SLIT ACPI tables
23
* Set tval in breakpoints
24
* libqos fixes and add a riscv machine
24
* Add support for Zve32x extension
25
* Add Ztso extension
25
* Add support for Zve64x extension
26
* Use 'zfa' instead of 'Zfa'
26
* Relax vector register check in RISCV gdbstub
27
* Update KVM exts to Linux 6.8
27
* Fix the element agnostic Vector function problem
28
* move ratified/frozen exts to non-experimental
28
* Fix Zvkb extension config
29
* Ensure mcountinhibit, mcounteren, scounteren, hcounteren are 32-bit
29
* Implement dynamic establishment of custom decoder
30
* mark_vs_dirty() before loads and stores
30
* Add th.sxstatus CSR emulation
31
* Remove 'is_store' bool from load/store fns
31
* Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
32
* Fix shift count overflow
32
* Check single width operator for vector fp widen instructions
33
* Fix setipnum_le write emulation for APLIC MSI-mode
33
* Check single width operator for vfncvt.rod.f.f.w
34
* Fix in_clrip[x] read emulation
34
* Remove redudant SEW checking for vector fp narrow/widen instructions
35
* Fix privilege mode of G-stage translation for debugging
35
* Prioritize pmp errors in raise_mmu_exception()
36
* Fix ACPI MCFG table for virt machine
36
* Do not set mtval2 for non guest-page faults
37
* Remove experimental prefix from "B" extension
38
* Fixup CBO extension register calculation
39
* Fix the hart bit setting of AIA
40
* Fix reg_width in ricsv_gen_dynamic_vector_feature()
41
* Decode all of the pmpcfg and pmpaddr CSRs
42
* Raise an exception when CSRRS/CSRRC writes a read-only CSR
37
43
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----------------------------------------------------------------
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----------------------------------------------------------------
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Alexandre Ghiti (1):
45
Alexei Filippov (1):
40
hw: riscv: Allow large kernels to boot by moving the initrd further away in RAM
46
target/riscv: do not set mtval2 for non guest-page faults
41
47
42
Andrew Jones (3):
48
Alistair Francis (2):
43
target/riscv: Reset henvcfg to zero
49
target/riscv: rvzicbo: Fixup CBO extension register calculation
44
target/riscv: Gate hardware A/D PTE bit updating
50
disas/riscv: Decode all of the pmpcfg and pmpaddr CSRs
45
target/riscv: Promote svade to a normal extension
46
51
47
Anup Patel (2):
52
Andrew Jones (2):
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hw/intc/riscv_aplic: Fix setipnum_le write emulation for APLIC MSI-mode
53
target/riscv/kvm: Fix exposure of Zkr
49
hw/intc/riscv_aplic: Fix in_clrip[x] read emulation
54
target/riscv: Raise exceptions on wrs.nto
50
55
51
Christoph Müllner (4):
56
Cheng Yang (1):
52
linux-user/riscv: Add Zicboz extensions to hwprobe
57
hw/riscv/boot.c: Support 64-bit address for initrd
53
linux-user/riscv: Sync hwprobe keys with Linux
54
linux-user/riscv: Add Ztso extension to hwprobe
55
tests: riscv64: Use 'zfa' instead of 'Zfa'
56
58
57
Daniel Henrique Barboza (12):
59
Christoph Müllner (1):
58
target/riscv/tcg: set 'mmu' with 'satp' in cpu_set_profile()
60
riscv: thead: Add th.sxstatus CSR emulation
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target/riscv: add riscv,isa to named features
60
target/riscv: add remaining named features
61
hw/riscv/virt.c: create '/soc/pci@...' fdt node earlier
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hw/riscv/virt.c: add virtio-iommu-pci hotplug support
63
hw/riscv/virt.c: make aclint compatible with 'qtest' accel
64
tests/libqos: add riscv/virt machine nodes
65
linux-headers: Update to Linux v6.8-rc6
66
target/riscv/kvm: update KVM exts to Linux 6.8
67
target/riscv: move ratified/frozen exts to non-experimental
68
trans_rvv.c.inc: mark_vs_dirty() before loads and stores
69
trans_rvv.c.inc: remove 'is_store' bool from load/store fns
70
61
71
Frank Chang (1):
62
Clément Léger (1):
72
target/riscv: Add missing include guard in pmu.h
63
target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63
73
64
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Haibo Xu (1):
65
Daniel Henrique Barboza (6):
75
hw/riscv/virt-acpi-build.c: Add SRAT and SLIT ACPI tables
66
target/riscv/kvm: implement SBI debug console (DBCN) calls
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target/riscv/kvm: tolerate KVM disable ext errors
68
target/riscv/debug: set tval=pc in breakpoint exceptions
69
trans_privileged.c.inc: set (m|s)tval on ebreak breakpoint
70
target/riscv: prioritize pmp errors in raise_mmu_exception()
71
riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature()
76
72
77
Hiroaki Yamamoto (1):
73
Huang Tao (2):
78
target/riscv: Fix privilege mode of G-stage translation for debugging
74
target/riscv: Fix the element agnostic function problem
75
target/riscv: Implement dynamic establishment of custom decoder
79
76
80
Ilya Chugin (1):
77
Jason Chien (3):
81
target/riscv: fix ACPI MCFG table
78
target/riscv: Add support for Zve32x extension
79
target/riscv: Add support for Zve64x extension
80
target/riscv: Relax vector register check in RISCV gdbstub
82
81
83
Irina Ryapolova (2):
82
Max Chou (4):
84
target/riscv: FIX xATP_MODE validation
83
target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
85
target/riscv: UPDATE xATP write CSR
84
target/riscv: rvv: Check single width operator for vector fp widen instructions
85
target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w
86
target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions
86
87
87
Jason Chien (1):
88
Rob Bradford (1):
88
target/riscv: Update $ra with current $pc in trans_cm_jalt()
89
target/riscv: Remove experimental prefix from "B" extension
89
90
90
Palmer Dabbelt (1):
91
Yangyu Chen (1):
91
RISC-V: Add support for Ztso
92
target/riscv/cpu.c: fix Zvkb extension config
92
93
93
Sia Jee Heng (2):
94
Yong-Xuan Wang (1):
94
hw/arm/virt-acpi-build.c: Migrate SPCR creation to common location
95
target/riscv/kvm.c: Fix the hart bit setting of AIA
95
hw/riscv/virt-acpi-build.c: Generate SPCR table
96
96
97
Vadim Shakirov (1):
97
Yu-Ming Chang (1):
98
target/riscv: mcountinhibit, mcounteren, scounteren, hcounteren is 32-bit
98
target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR
99
99
100
demin.han (1):
100
yang.zhang (1):
101
target/riscv: Fix shift count overflow
101
hw/intc/riscv_aplic: APLICs should add child earlier than realize
102
102
103
include/hw/acpi/acpi-defs.h | 33 ++++++
103
MAINTAINERS | 1 +
104
include/hw/acpi/aml-build.h | 4 +
104
target/riscv/cpu.h | 11 ++
105
include/standard-headers/drm/drm_fourcc.h | 10 +-
105
target/riscv/cpu_bits.h | 2 +-
106
include/standard-headers/linux/ethtool.h | 41 +++++---
106
target/riscv/cpu_cfg.h | 2 +
107
include/standard-headers/linux/virtio_config.h | 8 +-
107
target/riscv/helper.h | 1 +
108
include/standard-headers/linux/virtio_pci.h | 68 ++++++++++++
108
target/riscv/sbi_ecall_interface.h | 17 +++
109
include/standard-headers/linux/virtio_pmem.h | 7 ++
109
target/riscv/tcg/tcg-cpu.h | 15 +++
110
linux-headers/asm-generic/unistd.h | 15 ++-
110
disas/riscv.c | 65 +++++++++-
111
linux-headers/asm-mips/mman.h | 2 +-
111
hw/intc/riscv_aplic.c | 8 +-
112
linux-headers/asm-mips/unistd_n32.h | 5 +
112
hw/riscv/boot.c | 4 +-
113
linux-headers/asm-mips/unistd_n64.h | 5 +
113
target/riscv/cpu.c | 10 +-
114
linux-headers/asm-mips/unistd_o32.h | 5 +
114
target/riscv/cpu_helper.c | 37 +++---
115
linux-headers/asm-powerpc/unistd_32.h | 5 +
115
target/riscv/csr.c | 71 +++++++++--
116
linux-headers/asm-powerpc/unistd_64.h | 5 +
116
target/riscv/debug.c | 3 +
117
linux-headers/asm-riscv/kvm.h | 40 +++++++
117
target/riscv/gdbstub.c | 8 +-
118
linux-headers/asm-s390/unistd_32.h | 5 +
118
target/riscv/kvm/kvm-cpu.c | 157 ++++++++++++++++++++++++-
119
linux-headers/asm-s390/unistd_64.h | 5 +
119
target/riscv/op_helper.c | 17 ++-
120
linux-headers/asm-x86/kvm.h | 3 +
120
target/riscv/tcg/tcg-cpu.c | 50 +++++---
121
linux-headers/asm-x86/unistd_32.h | 5 +
121
target/riscv/th_csr.c | 79 +++++++++++++
122
linux-headers/asm-x86/unistd_64.h | 5 +
122
target/riscv/translate.c | 31 +++--
123
linux-headers/asm-x86/unistd_x32.h | 5 +
123
target/riscv/vector_internals.c | 22 ++++
124
linux-headers/linux/iommufd.h | 79 ++++++++++++++
124
target/riscv/insn_trans/trans_privileged.c.inc | 2 +
125
linux-headers/linux/kvm.h | 140 +++++++++----------------
125
target/riscv/insn_trans/trans_rvv.c.inc | 46 +++++---
126
linux-headers/linux/userfaultfd.h | 29 ++++-
126
target/riscv/insn_trans/trans_rvzawrs.c.inc | 29 +++--
127
linux-headers/linux/vfio.h | 1 +
127
target/riscv/insn_trans/trans_rvzicbo.c.inc | 16 ++-
128
target/riscv/cpu.h | 8 +-
128
target/riscv/meson.build | 1 +
129
target/riscv/cpu_cfg.h | 13 ++-
129
26 files changed, 596 insertions(+), 109 deletions(-)
130
target/riscv/pmu.h | 5 +
130
create mode 100644 target/riscv/th_csr.c
131
hw/acpi/aml-build.c | 53 ++++++++++
132
hw/arm/virt-acpi-build.c | 68 +++++-------
133
hw/intc/riscv_aplic.c | 37 +++++--
134
hw/riscv/boot.c | 12 +--
135
hw/riscv/virt-acpi-build.c | 103 +++++++++++++++++-
136
hw/riscv/virt.c | 97 ++++++++++++-----
137
linux-user/syscall.c | 104 ++++++++++++++++--
138
target/riscv/cpu.c | 94 +++++++++++------
139
target/riscv/cpu_helper.c | 21 +++-
140
target/riscv/csr.c | 58 +++++-----
141
target/riscv/kvm/kvm-cpu.c | 29 +++++
142
target/riscv/machine.c | 16 +--
143
target/riscv/tcg/tcg-cpu.c | 34 +++---
144
target/riscv/translate.c | 3 +
145
target/riscv/vector_helper.c | 5 +-
146
tests/qtest/libqos/riscv-virt-machine.c | 137 ++++++++++++++++++++++++
147
target/riscv/insn_trans/trans_rva.c.inc | 11 +-
148
target/riscv/insn_trans/trans_rvi.c.inc | 16 ++-
149
target/riscv/insn_trans/trans_rvv.c.inc | 97 +++++++++--------
150
target/riscv/insn_trans/trans_rvzce.c.inc | 6 +-
151
tests/qtest/libqos/meson.build | 1 +
152
tests/tcg/riscv64/Makefile.target | 2 +-
153
50 files changed, 1213 insertions(+), 347 deletions(-)
154
create mode 100644 tests/qtest/libqos/riscv-virt-machine.c
155
131
diff view generated by jsdifflib
[PULL 32/34] hw/intc/riscv_aplic: Fix in_clrip[x] read emulation
[PULL 01/28] hw/intc/riscv_aplic: APLICs should add child earlier than realize
1
From: Anup Patel <apatel@ventanamicro.com>
1
From: "yang.zhang" <yang.zhang@hexintek.com>
2
2
3
The reads to in_clrip[x] registers return rectified input values of the
3
Since only root APLICs can have hw IRQ lines, aplic->parent should
4
interrupt sources.
4
be initialized first.
5
5
6
A rectified input value of an interrupt source is defined by the section
6
Fixes: e8f79343cf ("hw/intc: Add RISC-V AIA APLIC device emulation")
7
"4.5.2 Source configurations (sourcecfg[1]–sourcecfg[1023])" of the RISC-V
8
AIA specification as:
9
"rectified input value = (incoming wire value) XOR (source is inverted)"
10
11
Update the riscv_aplic_read_input_word() implementation to match the above.
12
13
Fixes: e8f79343cfc8 ("hw/intc: Add RISC-V AIA APLIC device emulation")
14
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
15
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
7
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
16
Message-ID: <20240306095722.463296-3-apatel@ventanamicro.com>
8
Signed-off-by: yang.zhang <yang.zhang@hexintek.com>
9
Cc: qemu-stable <qemu-stable@nongnu.org>
10
Message-ID: <20240409014445.278-1-gaoshanliukou@163.com>
17
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
18
---
12
---
19
hw/intc/riscv_aplic.c | 17 +++++++++++++++--
13
hw/intc/riscv_aplic.c | 8 ++++----
20
1 file changed, 15 insertions(+), 2 deletions(-)
14
1 file changed, 4 insertions(+), 4 deletions(-)
21
15
22
diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
16
diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
23
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
24
--- a/hw/intc/riscv_aplic.c
18
--- a/hw/intc/riscv_aplic.c
25
+++ b/hw/intc/riscv_aplic.c
19
+++ b/hw/intc/riscv_aplic.c
26
@@ -XXX,XX +XXX,XX @@ static bool is_kvm_aia(bool msimode)
20
@@ -XXX,XX +XXX,XX @@ DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size,
27
static uint32_t riscv_aplic_read_input_word(RISCVAPLICState *aplic,
21
qdev_prop_set_bit(dev, "msimode", msimode);
28
uint32_t word)
22
qdev_prop_set_bit(dev, "mmode", mmode);
29
{
23
30
- uint32_t i, irq, ret = 0;
24
+ if (parent) {
31
+ uint32_t i, irq, sourcecfg, sm, raw_input, irq_inverted, ret = 0;
25
+ riscv_aplic_add_child(parent, dev);
32
26
+ }
33
for (i = 0; i < 32; i++) {
34
irq = word * 32 + i;
35
@@ -XXX,XX +XXX,XX @@ static uint32_t riscv_aplic_read_input_word(RISCVAPLICState *aplic,
36
continue;
37
}
38
39
- ret |= ((aplic->state[irq] & APLIC_ISTATE_INPUT) ? 1 : 0) << i;
40
+ sourcecfg = aplic->sourcecfg[irq];
41
+ if (sourcecfg & APLIC_SOURCECFG_D) {
42
+ continue;
43
+ }
44
+
27
+
45
+ sm = sourcecfg & APLIC_SOURCECFG_SM_MASK;
28
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
46
+ if (sm == APLIC_SOURCECFG_SM_INACTIVE) {
29
47
+ continue;
30
if (!is_kvm_aia(msimode)) {
48
+ }
31
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
49
+
50
+ raw_input = (aplic->state[irq] & APLIC_ISTATE_INPUT) ? 1 : 0;
51
+ irq_inverted = (sm == APLIC_SOURCECFG_SM_LEVEL_LOW ||
52
+ sm == APLIC_SOURCECFG_SM_EDGE_FALL) ? 1 : 0;
53
+ ret |= (raw_input ^ irq_inverted) << i;
54
}
32
}
55
33
56
return ret;
34
- if (parent) {
35
- riscv_aplic_add_child(parent, dev);
36
- }
37
-
38
if (!msimode) {
39
for (i = 0; i < num_harts; i++) {
40
CPUState *cpu = cpu_by_arch_id(hartid_base + i);
57
--
41
--
58
2.44.0
42
2.45.1
59
60
diff view generated by jsdifflib
[PULL 10/34] target/riscv: Reset henvcfg to zero
[PULL 02/28] target/riscv/kvm: Fix exposure of Zkr
1
From: Andrew Jones <ajones@ventanamicro.com>
1
From: Andrew Jones <ajones@ventanamicro.com>
2
2
3
The hypervisor should decide what it wants to enable. Zero all
3
The Zkr extension may only be exposed to KVM guests if the VMM
4
configuration enable bits on reset.
4
implements the SEED CSR. Use the same implementation as TCG.
5
5
6
Also, commit ed67d63798f2 ("target/riscv: Update CSR bits name for
6
Without this patch, running with a KVM which does not forward the
7
svadu extension") missed one reference to 'hade'. Change it now.
7
SEED CSR access to QEMU will result in an ILL exception being
8
injected into the guest (this results in Linux guests crashing on
9
boot). And, when running with a KVM which does forward the access,
10
QEMU will crash, since QEMU doesn't know what to do with the exit.
8
11
9
Fixes: 0af3f115e68e ("target/riscv: Add *envcfg.HADE related check in address translation")
12
Fixes: 3108e2f1c69d ("target/riscv/kvm: update KVM exts to Linux 6.8")
10
Fixes: ed67d63798f2 ("target/riscv: Update CSR bits name for svadu extension")
13
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
11
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
14
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
12
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
15
Cc: qemu-stable <qemu-stable@nongnu.org>
13
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
16
Message-ID: <20240422134605.534207-2-ajones@ventanamicro.com>
14
Message-ID: <20240215223955.969568-5-dbarboza@ventanamicro.com>
15
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
17
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
16
---
18
---
17
target/riscv/cpu.c | 3 +--
19
target/riscv/cpu.h | 3 +++
18
target/riscv/csr.c | 2 +-
20
target/riscv/csr.c | 18 ++++++++++++++----
19
2 files changed, 2 insertions(+), 3 deletions(-)
21
target/riscv/kvm/kvm-cpu.c | 25 +++++++++++++++++++++++++
22
3 files changed, 42 insertions(+), 4 deletions(-)
20
23
21
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
24
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
22
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
23
--- a/target/riscv/cpu.c
26
--- a/target/riscv/cpu.h
24
+++ b/target/riscv/cpu.c
27
+++ b/target/riscv/cpu.h
25
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset_hold(Object *obj)
28
@@ -XXX,XX +XXX,XX @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
26
29
27
env->menvcfg = (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0) |
30
void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
28
(cpu->cfg.ext_svadu ? MENVCFG_ADUE : 0);
31
29
- env->henvcfg = (cpu->cfg.ext_svpbmt ? HENVCFG_PBMTE : 0) |
32
+target_ulong riscv_new_csr_seed(target_ulong new_value,
30
- (cpu->cfg.ext_svadu ? HENVCFG_ADUE : 0);
33
+ target_ulong write_mask);
31
+ env->henvcfg = 0;
34
+
32
35
uint8_t satp_mode_max_from_map(uint32_t map);
33
/* Initialized default priorities of local interrupts. */
36
const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
34
for (i = 0; i < ARRAY_SIZE(env->miprio); i++) {
37
35
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
38
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
36
index XXXXXXX..XXXXXXX 100644
39
index XXXXXXX..XXXXXXX 100644
37
--- a/target/riscv/csr.c
40
--- a/target/riscv/csr.c
38
+++ b/target/riscv/csr.c
41
+++ b/target/riscv/csr.c
39
@@ -XXX,XX +XXX,XX @@ static RISCVException read_henvcfg(CPURISCVState *env, int csrno,
42
@@ -XXX,XX +XXX,XX @@ static RISCVException write_upmbase(CPURISCVState *env, int csrno,
40
/*
43
#endif
41
* henvcfg.pbmte is read_only 0 when menvcfg.pbmte = 0
44
42
* henvcfg.stce is read_only 0 when menvcfg.stce = 0
45
/* Crypto Extension */
43
- * henvcfg.hade is read_only 0 when menvcfg.hade = 0
46
-static RISCVException rmw_seed(CPURISCVState *env, int csrno,
44
+ * henvcfg.adue is read_only 0 when menvcfg.adue = 0
47
- target_ulong *ret_value,
45
*/
48
- target_ulong new_value,
46
*val = env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE) |
49
- target_ulong write_mask)
47
env->menvcfg);
50
+target_ulong riscv_new_csr_seed(target_ulong new_value,
51
+ target_ulong write_mask)
52
{
53
uint16_t random_v;
54
Error *random_e = NULL;
55
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_seed(CPURISCVState *env, int csrno,
56
rval = random_v | SEED_OPST_ES16;
57
}
58
59
+ return rval;
60
+}
61
+
62
+static RISCVException rmw_seed(CPURISCVState *env, int csrno,
63
+ target_ulong *ret_value,
64
+ target_ulong new_value,
65
+ target_ulong write_mask)
66
+{
67
+ target_ulong rval;
68
+
69
+ rval = riscv_new_csr_seed(new_value, write_mask);
70
+
71
if (ret_value) {
72
*ret_value = rval;
73
}
74
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
75
index XXXXXXX..XXXXXXX 100644
76
--- a/target/riscv/kvm/kvm-cpu.c
77
+++ b/target/riscv/kvm/kvm-cpu.c
78
@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
79
return ret;
80
}
81
82
+static int kvm_riscv_handle_csr(CPUState *cs, struct kvm_run *run)
83
+{
84
+ target_ulong csr_num = run->riscv_csr.csr_num;
85
+ target_ulong new_value = run->riscv_csr.new_value;
86
+ target_ulong write_mask = run->riscv_csr.write_mask;
87
+ int ret = 0;
88
+
89
+ switch (csr_num) {
90
+ case CSR_SEED:
91
+ run->riscv_csr.ret_value = riscv_new_csr_seed(new_value, write_mask);
92
+ break;
93
+ default:
94
+ qemu_log_mask(LOG_UNIMP,
95
+ "%s: un-handled CSR EXIT for CSR %lx\n",
96
+ __func__, csr_num);
97
+ ret = -1;
98
+ break;
99
+ }
100
+
101
+ return ret;
102
+}
103
+
104
int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
105
{
106
int ret = 0;
107
@@ -XXX,XX +XXX,XX @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
108
case KVM_EXIT_RISCV_SBI:
109
ret = kvm_riscv_handle_sbi(cs, run);
110
break;
111
+ case KVM_EXIT_RISCV_CSR:
112
+ ret = kvm_riscv_handle_csr(cs, run);
113
+ break;
114
default:
115
qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n",
116
__func__, run->exit_reason);
48
--
117
--
49
2.44.0
118
2.45.1
diff view generated by jsdifflib
[PULL 15/34] target/riscv: Add missing include guard in pmu.h
[PULL 03/28] target/riscv: Raise exceptions on wrs.nto
1
From: Frank Chang <frank.chang@sifive.com>
1
From: Andrew Jones <ajones@ventanamicro.com>
2
2
3
Add missing include guard in pmu.h to avoid the problem of double
3
Implementing wrs.nto to always just return is consistent with the
4
inclusion.
4
specification, as the instruction is permitted to terminate the
5
stall for any reason, but it's not useful for virtualization, where
6
we'd like the guest to trap to the hypervisor in order to allow
7
scheduling of the lock holding VCPU. Change to always immediately
8
raise exceptions when the appropriate conditions are present,
9
otherwise continue to just return. Note, immediately raising
10
exceptions is also consistent with the specification since the
11
time limit that should expire prior to the exception is
12
implementation-specific.
5
13
6
Signed-off-by: Frank Chang <frank.chang@sifive.com>
14
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
7
Reviewed-by: Atish Patra <atishp@rivosinc.com>
15
Reviewed-by: Christoph Müllner <christoph.muellner@vrull.eu>
8
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
16
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
17
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
11
Message-ID: <20240220110907.10479-1-frank.chang@sifive.com>
18
Message-ID: <20240424142808.62936-2-ajones@ventanamicro.com>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
19
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
---
20
---
14
target/riscv/pmu.h | 5 +++++
21
target/riscv/helper.h | 1 +
15
1 file changed, 5 insertions(+)
22
target/riscv/op_helper.c | 11 ++++++++
23
target/riscv/insn_trans/trans_rvzawrs.c.inc | 29 ++++++++++++++-------
24
3 files changed, 32 insertions(+), 9 deletions(-)
16
25
17
diff --git a/target/riscv/pmu.h b/target/riscv/pmu.h
26
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
18
index XXXXXXX..XXXXXXX 100644
27
index XXXXXXX..XXXXXXX 100644
19
--- a/target/riscv/pmu.h
28
--- a/target/riscv/helper.h
20
+++ b/target/riscv/pmu.h
29
+++ b/target/riscv/helper.h
30
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_6(csrrw_i128, tl, env, int, tl, tl, tl, tl)
31
DEF_HELPER_1(sret, tl, env)
32
DEF_HELPER_1(mret, tl, env)
33
DEF_HELPER_1(wfi, void, env)
34
+DEF_HELPER_1(wrs_nto, void, env)
35
DEF_HELPER_1(tlb_flush, void, env)
36
DEF_HELPER_1(tlb_flush_all, void, env)
37
/* Native Debug */
38
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
39
index XXXXXXX..XXXXXXX 100644
40
--- a/target/riscv/op_helper.c
41
+++ b/target/riscv/op_helper.c
42
@@ -XXX,XX +XXX,XX @@ void helper_wfi(CPURISCVState *env)
43
}
44
}
45
46
+void helper_wrs_nto(CPURISCVState *env)
47
+{
48
+ if (env->virt_enabled && (env->priv == PRV_S || env->priv == PRV_U) &&
49
+ get_field(env->hstatus, HSTATUS_VTW) &&
50
+ !get_field(env->mstatus, MSTATUS_TW)) {
51
+ riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
52
+ } else if (env->priv != PRV_M && get_field(env->mstatus, MSTATUS_TW)) {
53
+ riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
54
+ }
55
+}
56
+
57
void helper_tlb_flush(CPURISCVState *env)
58
{
59
CPUState *cs = env_cpu(env);
60
diff --git a/target/riscv/insn_trans/trans_rvzawrs.c.inc b/target/riscv/insn_trans/trans_rvzawrs.c.inc
61
index XXXXXXX..XXXXXXX 100644
62
--- a/target/riscv/insn_trans/trans_rvzawrs.c.inc
63
+++ b/target/riscv/insn_trans/trans_rvzawrs.c.inc
21
@@ -XXX,XX +XXX,XX @@
64
@@ -XXX,XX +XXX,XX @@
22
* this program. If not, see <http://www.gnu.org/licenses/>.
65
* this program. If not, see <http://www.gnu.org/licenses/>.
23
*/
66
*/
24
67
25
+#ifndef RISCV_PMU_H
68
-static bool trans_wrs(DisasContext *ctx)
26
+#define RISCV_PMU_H
69
+static bool trans_wrs_sto(DisasContext *ctx, arg_wrs_sto *a)
70
{
71
if (!ctx->cfg_ptr->ext_zawrs) {
72
return false;
73
@@ -XXX,XX +XXX,XX @@ static bool trans_wrs(DisasContext *ctx)
74
return true;
75
}
76
77
-#define GEN_TRANS_WRS(insn) \
78
-static bool trans_ ## insn(DisasContext *ctx, arg_ ## insn *a) \
79
-{ \
80
- (void)a; \
81
- return trans_wrs(ctx); \
82
-}
83
+static bool trans_wrs_nto(DisasContext *ctx, arg_wrs_nto *a)
84
+{
85
+ if (!ctx->cfg_ptr->ext_zawrs) {
86
+ return false;
87
+ }
88
89
-GEN_TRANS_WRS(wrs_nto)
90
-GEN_TRANS_WRS(wrs_sto)
91
+ /*
92
+ * Depending on the mode of execution, mstatus.TW and hstatus.VTW, wrs.nto
93
+ * should raise an exception when the implementation-specific bounded time
94
+ * limit has expired. Our time limit is zero, so we either return
95
+ * immediately, as does our implementation of wrs.sto, or raise an
96
+ * exception, as handled by the wrs.nto helper.
97
+ */
98
+#ifndef CONFIG_USER_ONLY
99
+ gen_helper_wrs_nto(tcg_env);
100
+#endif
27
+
101
+
28
#include "cpu.h"
102
+ /* We only get here when helper_wrs_nto() doesn't raise an exception. */
29
#include "qapi/error.h"
103
+ return trans_wrs_sto(ctx, NULL);
30
104
+}
31
@@ -XXX,XX +XXX,XX @@ int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_event_idx event_idx);
32
void riscv_pmu_generate_fdt_node(void *fdt, uint32_t cmask, char *pmu_name);
33
int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value,
34
uint32_t ctr_idx);
35
+
36
+#endif /* RISCV_PMU_H */
37
--
105
--
38
2.44.0
106
2.45.1
39
107
40
108
diff view generated by jsdifflib
[PULL 20/34] tests/libqos: add riscv/virt machine nodes
[PULL 04/28] target/riscv/kvm: implement SBI debug console (DBCN) calls
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
2
2
3
Add a RISC-V 'virt' machine to the graph. This implementation is a
3
SBI defines a Debug Console extension "DBCN" that will, in time, replace
4
modified copy of the existing arm machine in arm-virt-machine.c
4
the legacy console putchar and getchar SBI extensions.
5
5
6
It contains a virtio-mmio and a generic-pcihost controller. The
6
The appeal of the DBCN extension is that it allows multiple bytes to be
7
generic-pcihost controller hardcodes assumptions from the ARM 'virt'
7
read/written in the SBI console in a single SBI call.
8
machine, like ecam and pio_base addresses, so we'll add an extra step to
8
9
set its parameters after creating it.
9
As far as KVM goes, the DBCN calls are forwarded by an in-kernel KVM
10
10
module to userspace. But this will only happens if the KVM module
11
Our command line is incremented with 'aclint' parameters to allow the
11
actually supports this SBI extension and we activate it.
12
machine to run MSI tests.
12
13
We'll check for DBCN support during init time, checking if get-reg-list
14
is advertising KVM_RISCV_SBI_EXT_DBCN. In that case, we'll enable it via
15
kvm_set_one_reg() during kvm_arch_init_vcpu().
16
17
Finally, change kvm_riscv_handle_sbi() to handle the incoming calls for
18
SBI_EXT_DBCN, reading and writing as required.
19
20
A simple KVM guest with 'earlycon=sbi', running in an emulated RISC-V
21
host, takes around 20 seconds to boot without using DBCN. With this
22
patch we're taking around 14 seconds to boot due to the speed-up in the
23
terminal output. There's no change in boot time if the guest isn't
24
using earlycon.
13
25
14
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
26
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
15
Acked-by: Alistair Francis <alistair.francis@wdc.com>
27
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
16
Acked-by: Thomas Huth <thuth@redhat.com>
28
Message-ID: <20240425155012.581366-1-dbarboza@ventanamicro.com>
17
Message-ID: <20240217192607.32565-7-dbarboza@ventanamicro.com>
18
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
29
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
19
---
30
---
20
tests/qtest/libqos/riscv-virt-machine.c | 137 ++++++++++++++++++++++++
31
target/riscv/sbi_ecall_interface.h | 17 +++++
21
tests/qtest/libqos/meson.build | 1 +
32
target/riscv/kvm/kvm-cpu.c | 111 +++++++++++++++++++++++++++++
22
2 files changed, 138 insertions(+)
33
2 files changed, 128 insertions(+)
23
create mode 100644 tests/qtest/libqos/riscv-virt-machine.c
34
24
35
diff --git a/target/riscv/sbi_ecall_interface.h b/target/riscv/sbi_ecall_interface.h
25
diff --git a/tests/qtest/libqos/riscv-virt-machine.c b/tests/qtest/libqos/riscv-virt-machine.c
36
index XXXXXXX..XXXXXXX 100644
26
new file mode 100644
37
--- a/target/riscv/sbi_ecall_interface.h
27
index XXXXXXX..XXXXXXX
38
+++ b/target/riscv/sbi_ecall_interface.h
28
--- /dev/null
29
+++ b/tests/qtest/libqos/riscv-virt-machine.c
30
@@ -XXX,XX +XXX,XX @@
39
@@ -XXX,XX +XXX,XX @@
31
+/*
40
32
+ * libqos driver framework for risc-v
41
/* clang-format off */
33
+ *
42
34
+ * Initial version based on arm-virt-machine.c
43
+#define SBI_SUCCESS 0
35
+ *
44
+#define SBI_ERR_FAILED -1
36
+ * Copyright (c) 2024 Ventana Micro
45
+#define SBI_ERR_NOT_SUPPORTED -2
37
+ *
46
+#define SBI_ERR_INVALID_PARAM -3
38
+ * This library is free software; you can redistribute it and/or
47
+#define SBI_ERR_DENIED -4
39
+ * modify it under the terms of the GNU Lesser General Public
48
+#define SBI_ERR_INVALID_ADDRESS -5
40
+ * License version 2.1 as published by the Free Software Foundation.
49
+#define SBI_ERR_ALREADY_AVAILABLE -6
41
+ *
50
+#define SBI_ERR_ALREADY_STARTED -7
42
+ * This library is distributed in the hope that it will be useful,
51
+#define SBI_ERR_ALREADY_STOPPED -8
43
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
52
+#define SBI_ERR_NO_SHMEM -9
44
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
53
+
45
+ * Lesser General Public License for more details.
54
/* SBI Extension IDs */
46
+ *
55
#define SBI_EXT_0_1_SET_TIMER 0x0
47
+ * You should have received a copy of the GNU Lesser General Public
56
#define SBI_EXT_0_1_CONSOLE_PUTCHAR 0x1
48
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>
57
@@ -XXX,XX +XXX,XX @@
49
+ */
58
#define SBI_EXT_IPI 0x735049
50
+
59
#define SBI_EXT_RFENCE 0x52464E43
51
+#include "qemu/osdep.h"
60
#define SBI_EXT_HSM 0x48534D
52
+#include "../libqtest.h"
61
+#define SBI_EXT_DBCN 0x4442434E
53
+#include "qemu/module.h"
62
54
+#include "libqos-malloc.h"
63
/* SBI function IDs for BASE extension */
55
+#include "qgraph.h"
64
#define SBI_EXT_BASE_GET_SPEC_VERSION 0x0
56
+#include "virtio-mmio.h"
65
@@ -XXX,XX +XXX,XX @@
57
+#include "generic-pcihost.h"
66
#define SBI_EXT_HSM_HART_STOP 0x1
58
+#include "hw/pci/pci_regs.h"
67
#define SBI_EXT_HSM_HART_GET_STATUS 0x2
59
+
68
60
+#define RISCV_PAGE_SIZE 4096
69
+/* SBI function IDs for DBCN extension */
61
+
70
+#define SBI_EXT_DBCN_CONSOLE_WRITE 0x0
62
+/* VIRT_DRAM */
71
+#define SBI_EXT_DBCN_CONSOLE_READ 0x1
63
+#define RISCV_VIRT_RAM_ADDR 0x80000000
72
+#define SBI_EXT_DBCN_CONSOLE_WRITE_BYTE 0x2
64
+#define RISCV_VIRT_RAM_SIZE 0x20000000
73
+
65
+
74
#define SBI_HSM_HART_STATUS_STARTED 0x0
66
+/*
75
#define SBI_HSM_HART_STATUS_STOPPED 0x1
67
+ * VIRT_VIRTIO. BASE_ADDR points to the last
76
#define SBI_HSM_HART_STATUS_START_PENDING 0x2
68
+ * virtio_mmio device.
77
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
69
+ */
78
index XXXXXXX..XXXXXXX 100644
70
+#define VIRTIO_MMIO_BASE_ADDR 0x10008000
79
--- a/target/riscv/kvm/kvm-cpu.c
71
+#define VIRTIO_MMIO_SIZE 0x00001000
80
+++ b/target/riscv/kvm/kvm-cpu.c
72
+
81
@@ -XXX,XX +XXX,XX @@ static KVMCPUConfig kvm_v_vlenb = {
73
+/* VIRT_PCIE_PIO */
82
KVM_REG_RISCV_VECTOR_CSR_REG(vlenb)
74
+#define RISCV_GPEX_PIO_BASE 0x3000000
83
};
75
+#define RISCV_BUS_PIO_LIMIT 0x10000
84
76
+
85
+static KVMCPUConfig kvm_sbi_dbcn = {
77
+/* VIRT_PCIE_MMIO */
86
+ .name = "sbi_dbcn",
78
+#define RISCV_BUS_MMIO_ALLOC_PTR 0x40000000
87
+ .kvm_reg_id = KVM_REG_RISCV | KVM_REG_SIZE_U64 |
79
+#define RISCV_BUS_MMIO_LIMIT 0x80000000
88
+ KVM_REG_RISCV_SBI_EXT | KVM_RISCV_SBI_EXT_DBCN
80
+
81
+/* VIRT_PCIE_ECAM */
82
+#define RISCV_ECAM_ALLOC_PTR 0x30000000
83
+
84
+typedef struct QVirtMachine QVirtMachine;
85
+
86
+struct QVirtMachine {
87
+ QOSGraphObject obj;
88
+ QGuestAllocator alloc;
89
+ QVirtioMMIODevice virtio_mmio;
90
+ QGenericPCIHost bridge;
91
+};
89
+};
92
+
90
+
93
+static void virt_destructor(QOSGraphObject *obj)
91
static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs)
92
{
93
CPURISCVState *env = &cpu->env;
94
@@ -XXX,XX +XXX,XX @@ static int uint64_cmp(const void *a, const void *b)
95
return 0;
96
}
97
98
+static void kvm_riscv_check_sbi_dbcn_support(RISCVCPU *cpu,
99
+ KVMScratchCPU *kvmcpu,
100
+ struct kvm_reg_list *reglist)
94
+{
101
+{
95
+ QVirtMachine *machine = (QVirtMachine *) obj;
102
+ struct kvm_reg_list *reg_search;
96
+ alloc_destroy(&machine->alloc);
103
+
104
+ reg_search = bsearch(&kvm_sbi_dbcn.kvm_reg_id, reglist->reg, reglist->n,
105
+ sizeof(uint64_t), uint64_cmp);
106
+
107
+ if (reg_search) {
108
+ kvm_sbi_dbcn.supported = true;
109
+ }
97
+}
110
+}
98
+
111
+
99
+static void *virt_get_driver(void *object, const char *interface)
112
static void kvm_riscv_read_vlenb(RISCVCPU *cpu, KVMScratchCPU *kvmcpu,
113
struct kvm_reg_list *reglist)
114
{
115
@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu)
116
if (riscv_has_ext(&cpu->env, RVV)) {
117
kvm_riscv_read_vlenb(cpu, kvmcpu, reglist);
118
}
119
+
120
+ kvm_riscv_check_sbi_dbcn_support(cpu, kvmcpu, reglist);
121
}
122
123
static void riscv_init_kvm_registers(Object *cpu_obj)
124
@@ -XXX,XX +XXX,XX @@ static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, CPUState *cs)
125
return ret;
126
}
127
128
+static int kvm_vcpu_enable_sbi_dbcn(RISCVCPU *cpu, CPUState *cs)
100
+{
129
+{
101
+ QVirtMachine *machine = object;
130
+ target_ulong reg = 1;
102
+ if (!g_strcmp0(interface, "memory")) {
131
+
103
+ return &machine->alloc;
132
+ if (!kvm_sbi_dbcn.supported) {
133
+ return 0;
104
+ }
134
+ }
105
+
135
+
106
+ fprintf(stderr, "%s not present in riscv/virtio\n", interface);
136
+ return kvm_set_one_reg(cs, kvm_sbi_dbcn.kvm_reg_id, &reg);
107
+ g_assert_not_reached();
108
+}
137
+}
109
+
138
+
110
+static QOSGraphObject *virt_get_device(void *obj, const char *device)
139
int kvm_arch_init_vcpu(CPUState *cs)
140
{
141
int ret = 0;
142
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
143
kvm_riscv_update_cpu_misa_ext(cpu, cs);
144
kvm_riscv_update_cpu_cfg_isa_ext(cpu, cs);
145
146
+ ret = kvm_vcpu_enable_sbi_dbcn(cpu, cs);
147
+
148
return ret;
149
}
150
151
@@ -XXX,XX +XXX,XX @@ bool kvm_arch_stop_on_emulation_error(CPUState *cs)
152
return true;
153
}
154
155
+static void kvm_riscv_handle_sbi_dbcn(CPUState *cs, struct kvm_run *run)
111
+{
156
+{
112
+ QVirtMachine *machine = obj;
157
+ g_autofree uint8_t *buf = NULL;
113
+ if (!g_strcmp0(device, "generic-pcihost")) {
158
+ RISCVCPU *cpu = RISCV_CPU(cs);
114
+ return &machine->bridge.obj;
159
+ target_ulong num_bytes;
115
+ } else if (!g_strcmp0(device, "virtio-mmio")) {
160
+ uint64_t addr;
116
+ return &machine->virtio_mmio.obj;
161
+ unsigned char ch;
162
+ int ret;
163
+
164
+ switch (run->riscv_sbi.function_id) {
165
+ case SBI_EXT_DBCN_CONSOLE_READ:
166
+ case SBI_EXT_DBCN_CONSOLE_WRITE:
167
+ num_bytes = run->riscv_sbi.args[0];
168
+
169
+ if (num_bytes == 0) {
170
+ run->riscv_sbi.ret[0] = SBI_SUCCESS;
171
+ run->riscv_sbi.ret[1] = 0;
172
+ break;
173
+ }
174
+
175
+ addr = run->riscv_sbi.args[1];
176
+
177
+ /*
178
+ * Handle the case where a 32 bit CPU is running in a
179
+ * 64 bit addressing env.
180
+ */
181
+ if (riscv_cpu_mxl(&cpu->env) == MXL_RV32) {
182
+ addr |= (uint64_t)run->riscv_sbi.args[2] << 32;
183
+ }
184
+
185
+ buf = g_malloc0(num_bytes);
186
+
187
+ if (run->riscv_sbi.function_id == SBI_EXT_DBCN_CONSOLE_READ) {
188
+ ret = qemu_chr_fe_read_all(serial_hd(0)->be, buf, num_bytes);
189
+ if (ret < 0) {
190
+ error_report("SBI_EXT_DBCN_CONSOLE_READ: error when "
191
+ "reading chardev");
192
+ exit(1);
193
+ }
194
+
195
+ cpu_physical_memory_write(addr, buf, ret);
196
+ } else {
197
+ cpu_physical_memory_read(addr, buf, num_bytes);
198
+
199
+ ret = qemu_chr_fe_write_all(serial_hd(0)->be, buf, num_bytes);
200
+ if (ret < 0) {
201
+ error_report("SBI_EXT_DBCN_CONSOLE_WRITE: error when "
202
+ "writing chardev");
203
+ exit(1);
204
+ }
205
+ }
206
+
207
+ run->riscv_sbi.ret[0] = SBI_SUCCESS;
208
+ run->riscv_sbi.ret[1] = ret;
209
+ break;
210
+ case SBI_EXT_DBCN_CONSOLE_WRITE_BYTE:
211
+ ch = run->riscv_sbi.args[0];
212
+ ret = qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch));
213
+
214
+ if (ret < 0) {
215
+ error_report("SBI_EXT_DBCN_CONSOLE_WRITE_BYTE: error when "
216
+ "writing chardev");
217
+ exit(1);
218
+ }
219
+
220
+ run->riscv_sbi.ret[0] = SBI_SUCCESS;
221
+ run->riscv_sbi.ret[1] = 0;
222
+ break;
223
+ default:
224
+ run->riscv_sbi.ret[0] = SBI_ERR_NOT_SUPPORTED;
117
+ }
225
+ }
118
+
119
+ fprintf(stderr, "%s not present in riscv/virt\n", device);
120
+ g_assert_not_reached();
121
+}
226
+}
122
+
227
+
123
+static void riscv_config_qpci_bus(QGenericPCIBus *qpci)
228
static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
124
+{
229
{
125
+ qpci->gpex_pio_base = RISCV_GPEX_PIO_BASE;
230
int ret = 0;
126
+ qpci->bus.pio_limit = RISCV_BUS_PIO_LIMIT;
231
@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
127
+
232
}
128
+ qpci->bus.mmio_alloc_ptr = RISCV_BUS_MMIO_ALLOC_PTR;
233
ret = 0;
129
+ qpci->bus.mmio_limit = RISCV_BUS_MMIO_LIMIT;
234
break;
130
+
235
+ case SBI_EXT_DBCN:
131
+ qpci->ecam_alloc_ptr = RISCV_ECAM_ALLOC_PTR;
236
+ kvm_riscv_handle_sbi_dbcn(cs, run);
132
+}
237
+ break;
133
+
238
default:
134
+static void *qos_create_machine_riscv_virt(QTestState *qts)
239
qemu_log_mask(LOG_UNIMP,
135
+{
240
"%s: un-handled SBI EXIT, specific reasons is %lu\n",
136
+ QVirtMachine *machine = g_new0(QVirtMachine, 1);
137
+
138
+ alloc_init(&machine->alloc, 0,
139
+ RISCV_VIRT_RAM_ADDR,
140
+ RISCV_VIRT_RAM_ADDR + RISCV_VIRT_RAM_SIZE,
141
+ RISCV_PAGE_SIZE);
142
+ qvirtio_mmio_init_device(&machine->virtio_mmio, qts, VIRTIO_MMIO_BASE_ADDR,
143
+ VIRTIO_MMIO_SIZE);
144
+
145
+ qos_create_generic_pcihost(&machine->bridge, qts, &machine->alloc);
146
+ riscv_config_qpci_bus(&machine->bridge.pci);
147
+
148
+ machine->obj.get_device = virt_get_device;
149
+ machine->obj.get_driver = virt_get_driver;
150
+ machine->obj.destructor = virt_destructor;
151
+ return machine;
152
+}
153
+
154
+static void virt_machine_register_nodes(void)
155
+{
156
+ qos_node_create_machine_args("riscv32/virt", qos_create_machine_riscv_virt,
157
+ "aclint=on,aia=aplic-imsic");
158
+ qos_node_contains("riscv32/virt", "virtio-mmio", NULL);
159
+ qos_node_contains("riscv32/virt", "generic-pcihost", NULL);
160
+
161
+ qos_node_create_machine_args("riscv64/virt", qos_create_machine_riscv_virt,
162
+ "aclint=on,aia=aplic-imsic");
163
+ qos_node_contains("riscv64/virt", "virtio-mmio", NULL);
164
+ qos_node_contains("riscv64/virt", "generic-pcihost", NULL);
165
+}
166
+
167
+libqos_init(virt_machine_register_nodes);
168
diff --git a/tests/qtest/libqos/meson.build b/tests/qtest/libqos/meson.build
169
index XXXXXXX..XXXXXXX 100644
170
--- a/tests/qtest/libqos/meson.build
171
+++ b/tests/qtest/libqos/meson.build
172
@@ -XXX,XX +XXX,XX @@ libqos_srcs = files(
173
'arm-xilinx-zynq-a9-machine.c',
174
'ppc64_pseries-machine.c',
175
'x86_64_pc-machine.c',
176
+ 'riscv-virt-machine.c',
177
)
178
179
if have_virtfs
180
--
241
--
181
2.44.0
242
2.45.1
diff view generated by jsdifflib
[PULL 04/34] hw: riscv: Allow large kernels to boot by moving the initrd further away in RAM
[PULL 05/28] hw/riscv/boot.c: Support 64-bit address for initrd
1
From: Alexandre Ghiti <alexghiti@rivosinc.com>
1
From: Cheng Yang <yangcheng.work@foxmail.com>
2
2
3
Currently, the initrd is placed at 128MB, which overlaps with the kernel
3
Use qemu_fdt_setprop_u64() instead of qemu_fdt_setprop_cell()
4
when it is large (for example syzbot kernels are). From the kernel side,
4
to set the address of initrd in FDT to support 64-bit address.
5
there is no reason we could not push the initrd further away in memory
6
to accommodate large kernels, so move the initrd at 512MB when possible.
7
5
8
The ideal solution would have been to place the initrd based on the
6
Signed-off-by: Cheng Yang <yangcheng.work@foxmail.com>
9
kernel size but we actually can't since the bss size is not known when
10
the image is loaded by load_image_targphys_as() and the initrd would
11
then overlap with this section.
12
13
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
14
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
15
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
8
Message-ID: <tencent_A4482251DD0890F312758FA6B33F60815609@qq.com>
16
Message-ID: <20240206154042.514698-1-alexghiti@rivosinc.com>
17
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
18
---
10
---
19
hw/riscv/boot.c | 12 ++++++------
11
hw/riscv/boot.c | 4 ++--
20
1 file changed, 6 insertions(+), 6 deletions(-)
12
1 file changed, 2 insertions(+), 2 deletions(-)
21
13
22
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
14
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
23
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
24
--- a/hw/riscv/boot.c
16
--- a/hw/riscv/boot.c
25
+++ b/hw/riscv/boot.c
17
+++ b/hw/riscv/boot.c
26
@@ -XXX,XX +XXX,XX @@ static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry)
18
@@ -XXX,XX +XXX,XX @@ static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry)
27
* kernel is uncompressed it will not clobber the initrd. However
19
/* Some RISC-V machines (e.g. opentitan) don't have a fdt. */
28
* on boards without much RAM we must ensure that we still leave
20
if (fdt) {
29
* enough room for a decent sized initrd, and on boards with large
21
end = start + size;
30
- * amounts of RAM we must avoid the initrd being so far up in RAM
22
- qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start);
31
- * that it is outside lowmem and inaccessible to the kernel.
23
- qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end);
32
- * So for boards with less than 256MB of RAM we put the initrd
24
+ qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-start", start);
33
- * halfway into RAM, and for boards with 256MB of RAM or more we put
25
+ qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-end", end);
34
- * the initrd at 128MB.
26
}
35
+ * amounts of RAM, we put the initrd at 512MB to allow large kernels
27
}
36
+ * to boot.
28
37
+ * So for boards with less than 1GB of RAM we put the initrd
38
+ * halfway into RAM, and for boards with 1GB of RAM or more we put
39
+ * the initrd at 512MB.
40
*/
41
- start = kernel_entry + MIN(mem_size / 2, 128 * MiB);
42
+ start = kernel_entry + MIN(mem_size / 2, 512 * MiB);
43
44
size = load_ramdisk(filename, start, mem_size - start);
45
if (size == -1) {
46
--
29
--
47
2.44.0
30
2.45.1
diff view generated by jsdifflib
[PULL 23/34] tests: riscv64: Use 'zfa' instead of 'Zfa'
[PULL 06/28] target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63
1
From: Christoph Müllner <christoph.muellner@vrull.eu>
1
From: Clément Léger <cleger@rivosinc.com>
2
2
3
Running test-fcvtmod triggers the following deprecation warning:
3
The current semihost exception number (16) is a reserved number (range
4
warning: CPU property 'Zfa' is deprecated. Please use 'zfa' instead
4
[16-17]). The upcoming double trap specification uses that number for
5
Let's fix that.
5
the double trap exception. Since the privileged spec (Table 22) defines
6
ranges for custom uses change the semihosting exception number to 63
7
which belongs to the range [48-63] in order to avoid any future
8
collisions with reserved exception.
6
9
7
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
10
Signed-off-by: Clément Léger <cleger@rivosinc.com>
11
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
12
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
13
Message-ID: <20240422135840.1959967-1-cleger@rivosinc.com>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-ID: <20240229180656.1208881-1-christoph.muellner@vrull.eu>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
---
15
---
14
tests/tcg/riscv64/Makefile.target | 2 +-
16
target/riscv/cpu_bits.h | 2 +-
15
1 file changed, 1 insertion(+), 1 deletion(-)
17
1 file changed, 1 insertion(+), 1 deletion(-)
16
18
17
diff --git a/tests/tcg/riscv64/Makefile.target b/tests/tcg/riscv64/Makefile.target
19
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
18
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
19
--- a/tests/tcg/riscv64/Makefile.target
21
--- a/target/riscv/cpu_bits.h
20
+++ b/tests/tcg/riscv64/Makefile.target
22
+++ b/target/riscv/cpu_bits.h
21
@@ -XXX,XX +XXX,XX @@ run-test-aes: QEMU_OPTS += -cpu rv64,zk=on
23
@@ -XXX,XX +XXX,XX @@ typedef enum RISCVException {
22
TESTS += test-fcvtmod
24
RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */
23
test-fcvtmod: CFLAGS += -march=rv64imafdc
25
RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */
24
test-fcvtmod: LDFLAGS += -static
26
RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */
25
-run-test-fcvtmod: QEMU_OPTS += -cpu rv64,d=true,Zfa=true
27
- RISCV_EXCP_SEMIHOST = 0x10,
26
+run-test-fcvtmod: QEMU_OPTS += -cpu rv64,d=true,zfa=true
28
RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14,
29
RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT = 0x15,
30
RISCV_EXCP_VIRT_INSTRUCTION_FAULT = 0x16,
31
RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT = 0x17,
32
+ RISCV_EXCP_SEMIHOST = 0x3f,
33
} RISCVException;
34
35
#define RISCV_EXCP_INT_FLAG 0x80000000
27
--
36
--
28
2.44.0
37
2.45.1
29
38
30
39
diff view generated by jsdifflib
[PULL 25/34] target/riscv/kvm: update KVM exts to Linux 6.8
[PULL 07/28] target/riscv/kvm: tolerate KVM disable ext errors
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
2
2
3
The last KVM extensions added were back in 6.6. Sync them to Linux 6.8.
3
Running a KVM guest using a 6.9-rc3 kernel, in a 6.8 host that has zkr
4
enabled, will fail with a kernel oops SIGILL right at the start. The
5
reason is that we can't expose zkr without implementing the SEED CSR.
6
Disabling zkr in the guest would be a workaround, but if the KVM doesn't
7
allow it we'll error out and never boot.
4
8
9
In hindsight this is too strict. If we keep proceeding, despite not
10
disabling the extension in the KVM vcpu, we'll not add the extension in
11
the riscv,isa. The guest kernel will be unaware of the extension, i.e.
12
it doesn't matter if the KVM vcpu has it enabled underneath or not. So
13
it's ok to keep booting in this case.
14
15
Change our current logic to not error out if we fail to disable an
16
extension in kvm_set_one_reg(), but show a warning and keep booting. It
17
is important to throw a warning because we must make the user aware that
18
the extension is still available in the vcpu, meaning that an
19
ill-behaved guest can ignore the riscv,isa settings and use the
20
extension.
21
22
The case we're handling happens with an EINVAL error code. If we fail to
23
disable the extension in KVM for any other reason, error out.
24
25
We'll also keep erroring out when we fail to enable an extension in KVM,
26
since adding the extension in riscv,isa at this point will cause a guest
27
malfunction because the extension isn't enabled in the vcpu.
28
29
Suggested-by: Andrew Jones <ajones@ventanamicro.com>
5
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
30
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
6
Acked-by: Alistair Francis <alistair.francis@wdc.com>
31
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
7
Message-ID: <20240304134732.386590-3-dbarboza@ventanamicro.com>
32
Cc: qemu-stable <qemu-stable@nongnu.org>
33
Message-ID: <20240422171425.333037-2-dbarboza@ventanamicro.com>
8
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
34
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
9
---
35
---
10
target/riscv/kvm/kvm-cpu.c | 29 +++++++++++++++++++++++++++++
36
target/riscv/kvm/kvm-cpu.c | 12 ++++++++----
11
1 file changed, 29 insertions(+)
37
1 file changed, 8 insertions(+), 4 deletions(-)
12
38
13
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
39
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
14
index XXXXXXX..XXXXXXX 100644
40
index XXXXXXX..XXXXXXX 100644
15
--- a/target/riscv/kvm/kvm-cpu.c
41
--- a/target/riscv/kvm/kvm-cpu.c
16
+++ b/target/riscv/kvm/kvm-cpu.c
42
+++ b/target/riscv/kvm/kvm-cpu.c
17
@@ -XXX,XX +XXX,XX @@ static KVMCPUConfig kvm_multi_ext_cfgs[] = {
43
@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs)
18
KVM_EXT_CFG("zicbom", ext_zicbom, KVM_RISCV_ISA_EXT_ZICBOM),
44
reg = kvm_cpu_cfg_get(cpu, multi_ext_cfg);
19
KVM_EXT_CFG("zicboz", ext_zicboz, KVM_RISCV_ISA_EXT_ZICBOZ),
45
ret = kvm_set_one_reg(cs, id, &reg);
20
KVM_EXT_CFG("zicntr", ext_zicntr, KVM_RISCV_ISA_EXT_ZICNTR),
46
if (ret != 0) {
21
+ KVM_EXT_CFG("zicond", ext_zicond, KVM_RISCV_ISA_EXT_ZICOND),
47
- error_report("Unable to %s extension %s in KVM, error %d",
22
KVM_EXT_CFG("zicsr", ext_zicsr, KVM_RISCV_ISA_EXT_ZICSR),
48
- reg ? "enable" : "disable",
23
KVM_EXT_CFG("zifencei", ext_zifencei, KVM_RISCV_ISA_EXT_ZIFENCEI),
49
- multi_ext_cfg->name, ret);
24
+ KVM_EXT_CFG("zihintntl", ext_zihintntl, KVM_RISCV_ISA_EXT_ZIHINTNTL),
50
- exit(EXIT_FAILURE);
25
KVM_EXT_CFG("zihintpause", ext_zihintpause, KVM_RISCV_ISA_EXT_ZIHINTPAUSE),
51
+ if (!reg && ret == -EINVAL) {
26
KVM_EXT_CFG("zihpm", ext_zihpm, KVM_RISCV_ISA_EXT_ZIHPM),
52
+ warn_report("KVM cannot disable extension %s",
27
+ KVM_EXT_CFG("zfa", ext_zfa, KVM_RISCV_ISA_EXT_ZFA),
53
+ multi_ext_cfg->name);
28
+ KVM_EXT_CFG("zfh", ext_zfh, KVM_RISCV_ISA_EXT_ZFH),
54
+ } else {
29
+ KVM_EXT_CFG("zfhmin", ext_zfhmin, KVM_RISCV_ISA_EXT_ZFHMIN),
55
+ error_report("Unable to enable extension %s in KVM, error %d",
30
KVM_EXT_CFG("zba", ext_zba, KVM_RISCV_ISA_EXT_ZBA),
56
+ multi_ext_cfg->name, ret);
31
KVM_EXT_CFG("zbb", ext_zbb, KVM_RISCV_ISA_EXT_ZBB),
57
+ exit(EXIT_FAILURE);
32
+ KVM_EXT_CFG("zbc", ext_zbc, KVM_RISCV_ISA_EXT_ZBC),
58
+ }
33
+ KVM_EXT_CFG("zbkb", ext_zbkb, KVM_RISCV_ISA_EXT_ZBKB),
59
}
34
+ KVM_EXT_CFG("zbkc", ext_zbkc, KVM_RISCV_ISA_EXT_ZBKC),
60
}
35
+ KVM_EXT_CFG("zbkx", ext_zbkx, KVM_RISCV_ISA_EXT_ZBKX),
61
}
36
KVM_EXT_CFG("zbs", ext_zbs, KVM_RISCV_ISA_EXT_ZBS),
37
+ KVM_EXT_CFG("zknd", ext_zknd, KVM_RISCV_ISA_EXT_ZKND),
38
+ KVM_EXT_CFG("zkne", ext_zkne, KVM_RISCV_ISA_EXT_ZKNE),
39
+ KVM_EXT_CFG("zknh", ext_zknh, KVM_RISCV_ISA_EXT_ZKNH),
40
+ KVM_EXT_CFG("zkr", ext_zkr, KVM_RISCV_ISA_EXT_ZKR),
41
+ KVM_EXT_CFG("zksed", ext_zksed, KVM_RISCV_ISA_EXT_ZKSED),
42
+ KVM_EXT_CFG("zksh", ext_zksh, KVM_RISCV_ISA_EXT_ZKSH),
43
+ KVM_EXT_CFG("zkt", ext_zkt, KVM_RISCV_ISA_EXT_ZKT),
44
+ KVM_EXT_CFG("zvbb", ext_zvbb, KVM_RISCV_ISA_EXT_ZVBB),
45
+ KVM_EXT_CFG("zvbc", ext_zvbc, KVM_RISCV_ISA_EXT_ZVBC),
46
+ KVM_EXT_CFG("zvfh", ext_zvfh, KVM_RISCV_ISA_EXT_ZVFH),
47
+ KVM_EXT_CFG("zvfhmin", ext_zvfhmin, KVM_RISCV_ISA_EXT_ZVFHMIN),
48
+ KVM_EXT_CFG("zvkb", ext_zvkb, KVM_RISCV_ISA_EXT_ZVKB),
49
+ KVM_EXT_CFG("zvkg", ext_zvkg, KVM_RISCV_ISA_EXT_ZVKG),
50
+ KVM_EXT_CFG("zvkned", ext_zvkned, KVM_RISCV_ISA_EXT_ZVKNED),
51
+ KVM_EXT_CFG("zvknha", ext_zvknha, KVM_RISCV_ISA_EXT_ZVKNHA),
52
+ KVM_EXT_CFG("zvknhb", ext_zvknhb, KVM_RISCV_ISA_EXT_ZVKNHB),
53
+ KVM_EXT_CFG("zvksed", ext_zvksed, KVM_RISCV_ISA_EXT_ZVKSED),
54
+ KVM_EXT_CFG("zvksh", ext_zvksh, KVM_RISCV_ISA_EXT_ZVKSH),
55
+ KVM_EXT_CFG("zvkt", ext_zvkt, KVM_RISCV_ISA_EXT_ZVKT),
56
+ KVM_EXT_CFG("smstateen", ext_smstateen, KVM_RISCV_ISA_EXT_SMSTATEEN),
57
KVM_EXT_CFG("ssaia", ext_ssaia, KVM_RISCV_ISA_EXT_SSAIA),
58
KVM_EXT_CFG("sstc", ext_sstc, KVM_RISCV_ISA_EXT_SSTC),
59
KVM_EXT_CFG("svinval", ext_svinval, KVM_RISCV_ISA_EXT_SVINVAL),
60
--
62
--
61
2.44.0
63
2.45.1
diff view generated by jsdifflib
[PULL 17/34] hw/riscv/virt.c: create '/soc/pci@...' fdt node earlier
[PULL 08/28] target/riscv/debug: set tval=pc in breakpoint exceptions
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
2
2
3
Hotplugged FDT nodes will attempt to write this node that, at this
3
We're not setting (s/m)tval when triggering breakpoints of type 2
4
moment, is being created only in create_fdt_pcie() during
4
(mcontrol) and 6 (mcontrol6). According to the debug spec section
5
finalize_fdt().
5
5.7.12, "Match Control Type 6":
6
6
7
Create it earlier.
7
"The Privileged Spec says that breakpoint exceptions that occur on
8
instruction fetches, loads, or stores update the tval CSR with either
9
zero or the faulting virtual address. The faulting virtual address for
10
an mcontrol6 trigger with action = 0 is the address being accessed and
11
which caused that trigger to fire."
12
13
A similar text is also found in the Debug spec section 5.7.11 w.r.t.
14
mcontrol.
15
16
Note that what we're doing ATM is not violating the spec, but it's
17
simple enough to set mtval/stval and it makes life easier for any
18
software that relies on this info.
19
20
Given that we always use action = 0, save the faulting address for the
21
mcontrol and mcontrol6 trigger breakpoints into env->badaddr, which is
22
used as as scratch area for traps with address information. 'tval' is
23
then set during riscv_cpu_do_interrupt().
8
24
9
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
25
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
10
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
26
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
11
Message-ID: <20240217192607.32565-4-dbarboza@ventanamicro.com>
27
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
28
Message-ID: <20240416230437.1869024-2-dbarboza@ventanamicro.com>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
29
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
---
30
---
14
hw/riscv/virt.c | 9 ++++++++-
31
target/riscv/cpu_helper.c | 1 +
15
1 file changed, 8 insertions(+), 1 deletion(-)
32
target/riscv/debug.c | 3 +++
33
2 files changed, 4 insertions(+)
16
34
17
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
35
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
18
index XXXXXXX..XXXXXXX 100644
36
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/riscv/virt.c
37
--- a/target/riscv/cpu_helper.c
20
+++ b/hw/riscv/virt.c
38
+++ b/target/riscv/cpu_helper.c
21
@@ -XXX,XX +XXX,XX @@ static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap,
39
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
22
40
tval = env->bins;
23
name = g_strdup_printf("/soc/pci@%lx",
41
break;
24
(long) memmap[VIRT_PCIE_ECAM].base);
42
case RISCV_EXCP_BREAKPOINT:
25
- qemu_fdt_add_subnode(ms->fdt, name);
43
+ tval = env->badaddr;
26
qemu_fdt_setprop_cell(ms->fdt, name, "#address-cells",
44
if (cs->watchpoint_hit) {
27
FDT_PCI_ADDR_CELLS);
45
tval = cs->watchpoint_hit->hitaddr;
28
qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells",
46
cs->watchpoint_hit = NULL;
29
@@ -XXX,XX +XXX,XX @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap)
47
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
30
{
48
index XXXXXXX..XXXXXXX 100644
31
MachineState *ms = MACHINE(s);
49
--- a/target/riscv/debug.c
32
uint8_t rng_seed[32];
50
+++ b/target/riscv/debug.c
33
+ g_autofree char *name = NULL;
51
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
34
52
if ((ctrl & TYPE2_EXEC) && (bp->pc == pc)) {
35
ms->fdt = create_device_tree(&s->fdt_size);
53
/* check U/S/M bit against current privilege level */
36
if (!ms->fdt) {
54
if ((ctrl >> 3) & BIT(env->priv)) {
37
@@ -XXX,XX +XXX,XX @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap)
55
+ env->badaddr = pc;
38
qemu_fdt_setprop_cell(ms->fdt, "/soc", "#size-cells", 0x2);
56
return true;
39
qemu_fdt_setprop_cell(ms->fdt, "/soc", "#address-cells", 0x2);
57
}
40
58
}
41
+ /*
59
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
42
+ * The "/soc/pci@..." node is needed for PCIE hotplugs
60
if (env->virt_enabled) {
43
+ * that might happen before finalize_fdt().
61
/* check VU/VS bit against current privilege level */
44
+ */
62
if ((ctrl >> 23) & BIT(env->priv)) {
45
+ name = g_strdup_printf("/soc/pci@%lx", (long) memmap[VIRT_PCIE_ECAM].base);
63
+ env->badaddr = pc;
46
+ qemu_fdt_add_subnode(ms->fdt, name);
64
return true;
47
+
65
}
48
qemu_fdt_add_subnode(ms->fdt, "/chosen");
66
} else {
49
67
/* check U/S/M bit against current privilege level */
50
/* Pass seed to RNG */
68
if ((ctrl >> 3) & BIT(env->priv)) {
69
+ env->badaddr = pc;
70
return true;
71
}
72
}
51
--
73
--
52
2.44.0
74
2.45.1
diff view generated by jsdifflib
[PULL 09/34] target/riscv: add remaining named features
[PULL 09/28] trans_privileged.c.inc: set (m|s)tval on ebreak breakpoint
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
2
2
3
The RVA22U64 and RVA22S64 profiles mandates certain extensions that,
3
Privileged spec section 4.1.9 mentions:
4
until now, we were implying that they were available.
5
4
6
We can't do this anymore since named features also has a riscv,isa
5
"When a trap is taken into S-mode, stval is written with
7
entry. Let's add them to riscv_cpu_named_features[].
6
exception-specific information to assist software in handling the trap.
7
(...)
8
8
9
Instead of adding one bool for each named feature that we'll always
9
If stval is written with a nonzero value when a breakpoint,
10
implement, i.e. can't be turned off, add a 'ext_always_enabled' bool in
10
address-misaligned, access-fault, or page-fault exception occurs on an
11
cpu->cfg. This bool will be set to 'true' in TCG accel init, and all
11
instruction fetch, load, or store, then stval will contain the faulting
12
named features will point to it. This also means that KVM won't see
12
virtual address."
13
these features as always enable, which is our intention.
14
13
15
If any accelerator adds support to disable one of these features, we'll
14
A similar text is found for mtval in section 3.1.16.
16
have to promote them to regular extensions and allow users to disable it
17
via command line.
18
15
19
After this patch, here's the riscv,isa from a buildroot using the
16
Setting mtval/stval in this scenario is optional, but some softwares read
20
'rva22s64' CPU:
17
these regs when handling ebreaks.
21
18
22
# cat /proc/device-tree/cpus/cpu@0/riscv,isa
19
Write 'badaddr' in all ebreak breakpoints to write the appropriate
23
rv64imafdc_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_
20
'tval' during riscv_do_cpu_interrrupt().
24
zicntr_zicsr_zifencei_zihintpause_zihpm_za64rs_zfhmin_zca_zcd_zba_zbb_
25
zbs_zkt_ssccptr_sscounterenw_sstvala_sstvecd_svade_svinval_svpbmt#
26
21
27
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
22
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
28
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
23
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
29
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
24
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
30
Message-ID: <20240215223955.969568-4-dbarboza@ventanamicro.com>
25
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
26
Message-ID: <20240416230437.1869024-3-dbarboza@ventanamicro.com>
31
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
27
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
32
---
28
---
33
target/riscv/cpu_cfg.h | 6 ++++++
29
target/riscv/insn_trans/trans_privileged.c.inc | 2 ++
34
target/riscv/cpu.c | 42 +++++++++++++++++++++++++++++++-------
30
1 file changed, 2 insertions(+)
35
target/riscv/tcg/tcg-cpu.c | 2 ++
36
3 files changed, 43 insertions(+), 7 deletions(-)
37
31
38
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
32
diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
39
index XXXXXXX..XXXXXXX 100644
33
index XXXXXXX..XXXXXXX 100644
40
--- a/target/riscv/cpu_cfg.h
34
--- a/target/riscv/insn_trans/trans_privileged.c.inc
41
+++ b/target/riscv/cpu_cfg.h
35
+++ b/target/riscv/insn_trans/trans_privileged.c.inc
42
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
36
@@ -XXX,XX +XXX,XX @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)
43
bool ext_svade;
37
if (pre == 0x01f01013 && ebreak == 0x00100073 && post == 0x40705013) {
44
bool ext_zic64b;
38
generate_exception(ctx, RISCV_EXCP_SEMIHOST);
45
39
} else {
46
+ /*
40
+ tcg_gen_st_tl(tcg_constant_tl(ebreak_addr), tcg_env,
47
+ * Always 'true' boolean for named features
41
+ offsetof(CPURISCVState, badaddr));
48
+ * TCG always implement/can't be disabled.
42
generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
49
+ */
43
}
50
+ bool ext_always_enabled;
44
return true;
51
+
52
/* Vendor-specific custom extensions */
53
bool ext_xtheadba;
54
bool ext_xtheadbb;
55
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
56
index XXXXXXX..XXXXXXX 100644
57
--- a/target/riscv/cpu.c
58
+++ b/target/riscv/cpu.c
59
@@ -XXX,XX +XXX,XX @@ const RISCVIsaExtData isa_edata_arr[] = {
60
ISA_EXT_DATA_ENTRY(zicbom, PRIV_VERSION_1_12_0, ext_zicbom),
61
ISA_EXT_DATA_ENTRY(zicbop, PRIV_VERSION_1_12_0, ext_zicbop),
62
ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_zicboz),
63
+ ISA_EXT_DATA_ENTRY(ziccamoa, PRIV_VERSION_1_11_0, ext_always_enabled),
64
+ ISA_EXT_DATA_ENTRY(ziccif, PRIV_VERSION_1_11_0, ext_always_enabled),
65
+ ISA_EXT_DATA_ENTRY(zicclsm, PRIV_VERSION_1_11_0, ext_always_enabled),
66
+ ISA_EXT_DATA_ENTRY(ziccrse, PRIV_VERSION_1_11_0, ext_always_enabled),
67
ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond),
68
ISA_EXT_DATA_ENTRY(zicntr, PRIV_VERSION_1_12_0, ext_zicntr),
69
ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_zicsr),
70
@@ -XXX,XX +XXX,XX @@ const RISCVIsaExtData isa_edata_arr[] = {
71
ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause),
72
ISA_EXT_DATA_ENTRY(zihpm, PRIV_VERSION_1_12_0, ext_zihpm),
73
ISA_EXT_DATA_ENTRY(zmmul, PRIV_VERSION_1_12_0, ext_zmmul),
74
+ ISA_EXT_DATA_ENTRY(za64rs, PRIV_VERSION_1_12_0, ext_always_enabled),
75
ISA_EXT_DATA_ENTRY(zaamo, PRIV_VERSION_1_12_0, ext_zaamo),
76
ISA_EXT_DATA_ENTRY(zacas, PRIV_VERSION_1_12_0, ext_zacas),
77
ISA_EXT_DATA_ENTRY(zalrsc, PRIV_VERSION_1_12_0, ext_zalrsc),
78
@@ -XXX,XX +XXX,XX @@ const RISCVIsaExtData isa_edata_arr[] = {
79
ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp),
80
ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen),
81
ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia),
82
+ ISA_EXT_DATA_ENTRY(ssccptr, PRIV_VERSION_1_11_0, ext_always_enabled),
83
ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf),
84
+ ISA_EXT_DATA_ENTRY(sscounterenw, PRIV_VERSION_1_12_0, ext_always_enabled),
85
ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc),
86
+ ISA_EXT_DATA_ENTRY(sstvala, PRIV_VERSION_1_12_0, ext_always_enabled),
87
+ ISA_EXT_DATA_ENTRY(sstvecd, PRIV_VERSION_1_12_0, ext_always_enabled),
88
ISA_EXT_DATA_ENTRY(svade, PRIV_VERSION_1_11_0, ext_svade),
89
ISA_EXT_DATA_ENTRY(svadu, PRIV_VERSION_1_12_0, ext_svadu),
90
ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval),
91
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
92
DEFINE_PROP_END_OF_LIST(),
93
};
94
95
+#define ALWAYS_ENABLED_FEATURE(_name) \
96
+ {.name = _name, \
97
+ .offset = CPU_CFG_OFFSET(ext_always_enabled), \
98
+ .enabled = true}
99
+
100
/*
101
* 'Named features' is the name we give to extensions that we
102
* don't want to expose to users. They are either immutable
103
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_named_features[] = {
104
MULTI_EXT_CFG_BOOL("svade", ext_svade, true),
105
MULTI_EXT_CFG_BOOL("zic64b", ext_zic64b, true),
106
107
+ /*
108
+ * cache-related extensions that are always enabled
109
+ * in TCG since QEMU RISC-V does not have a cache
110
+ * model.
111
+ */
112
+ ALWAYS_ENABLED_FEATURE("za64rs"),
113
+ ALWAYS_ENABLED_FEATURE("ziccif"),
114
+ ALWAYS_ENABLED_FEATURE("ziccrse"),
115
+ ALWAYS_ENABLED_FEATURE("ziccamoa"),
116
+ ALWAYS_ENABLED_FEATURE("zicclsm"),
117
+ ALWAYS_ENABLED_FEATURE("ssccptr"),
118
+
119
+ /* Other named features that TCG always implements */
120
+ ALWAYS_ENABLED_FEATURE("sstvecd"),
121
+ ALWAYS_ENABLED_FEATURE("sstvala"),
122
+ ALWAYS_ENABLED_FEATURE("sscounterenw"),
123
+
124
DEFINE_PROP_END_OF_LIST(),
125
};
126
127
@@ -XXX,XX +XXX,XX @@ static const PropertyInfo prop_marchid = {
128
};
129
130
/*
131
- * RVA22U64 defines some 'named features' or 'synthetic extensions'
132
- * that are cache related: Za64rs, Zic64b, Ziccif, Ziccrse, Ziccamoa
133
- * and Zicclsm. We do not implement caching in QEMU so we'll consider
134
- * all these named features as always enabled.
135
- *
136
- * There's no riscv,isa update for them (nor for zic64b, despite it
137
- * having a cfg offset) at this moment.
138
+ * RVA22U64 defines some 'named features' that are cache
139
+ * related: Za64rs, Zic64b, Ziccif, Ziccrse, Ziccamoa
140
+ * and Zicclsm. They are always implemented in TCG and
141
+ * doesn't need to be manually enabled by the profile.
142
*/
143
static RISCVCPUProfile RVA22U64 = {
144
.parent = NULL,
145
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
146
index XXXXXXX..XXXXXXX 100644
147
--- a/target/riscv/tcg/tcg-cpu.c
148
+++ b/target/riscv/tcg/tcg-cpu.c
149
@@ -XXX,XX +XXX,XX @@ static void riscv_tcg_cpu_instance_init(CPUState *cs)
150
RISCVCPU *cpu = RISCV_CPU(cs);
151
Object *obj = OBJECT(cpu);
152
153
+ cpu->cfg.ext_always_enabled = true;
154
+
155
misa_ext_user_opts = g_hash_table_new(NULL, g_direct_equal);
156
multi_ext_user_opts = g_hash_table_new(NULL, g_direct_equal);
157
riscv_cpu_add_user_properties(obj);
158
--
45
--
159
2.44.0
46
2.45.1
diff view generated by jsdifflib
[PULL 21/34] RISC-V: Add support for Ztso
[PULL 10/28] target/riscv: Add support for Zve32x extension
1
From: Palmer Dabbelt <palmer@rivosinc.com>
1
From: Jason Chien <jason.chien@sifive.com>
2
2
3
The Ztso extension is already ratified, this adds it as a CPU property
3
Add support for Zve32x extension and replace some checks for Zve32f with
4
and adds various fences throughout the port in order to allow TSO
4
Zve32x, since Zve32f depends on Zve32x.
5
targets to function on weaker hosts. We need no fences for AMOs as
6
they're already SC, the places we need barriers are described.
7
These fences are placed in the RISC-V backend rather than TCG as is
8
planned for x86-on-arm64 because RISC-V allows heterogeneous (and
9
likely soon dynamic) hart memory models.
10
5
6
Signed-off-by: Jason Chien <jason.chien@sifive.com>
7
Reviewed-by: Frank Chang <frank.chang@sifive.com>
8
Reviewed-by: Max Chou <max.chou@sifive.com>
11
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
9
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
12
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
10
Message-ID: <20240328022343.6871-2-jason.chien@sifive.com>
13
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
14
Message-ID: <20240207122256.902627-2-christoph.muellner@vrull.eu>
15
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
16
---
12
---
17
target/riscv/cpu_cfg.h | 1 +
13
target/riscv/cpu_cfg.h | 1 +
18
target/riscv/cpu.c | 2 ++
14
target/riscv/cpu.c | 2 ++
19
target/riscv/translate.c | 3 +++
15
target/riscv/cpu_helper.c | 2 +-
20
target/riscv/insn_trans/trans_rva.c.inc | 11 ++++++++---
16
target/riscv/csr.c | 2 +-
21
target/riscv/insn_trans/trans_rvi.c.inc | 16 ++++++++++++++--
17
target/riscv/tcg/tcg-cpu.c | 16 ++++++++--------
22
target/riscv/insn_trans/trans_rvv.c.inc | 20 ++++++++++++++++++++
18
target/riscv/insn_trans/trans_rvv.c.inc | 4 ++--
23
6 files changed, 48 insertions(+), 5 deletions(-)
19
6 files changed, 15 insertions(+), 12 deletions(-)
24
20
25
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
21
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
26
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
27
--- a/target/riscv/cpu_cfg.h
23
--- a/target/riscv/cpu_cfg.h
28
+++ b/target/riscv/cpu_cfg.h
24
+++ b/target/riscv/cpu_cfg.h
29
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
25
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
30
bool ext_zihintntl;
26
bool ext_zhinx;
31
bool ext_zihintpause;
27
bool ext_zhinxmin;
32
bool ext_zihpm;
28
bool ext_zve32f;
33
+ bool ext_ztso;
29
+ bool ext_zve32x;
34
bool ext_smstateen;
30
bool ext_zve64f;
35
bool ext_sstc;
31
bool ext_zve64d;
36
bool ext_svadu;
32
bool ext_zvbb;
37
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
33
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
38
index XXXXXXX..XXXXXXX 100644
34
index XXXXXXX..XXXXXXX 100644
39
--- a/target/riscv/cpu.c
35
--- a/target/riscv/cpu.c
40
+++ b/target/riscv/cpu.c
36
+++ b/target/riscv/cpu.c
41
@@ -XXX,XX +XXX,XX @@ const RISCVIsaExtData isa_edata_arr[] = {
37
@@ -XXX,XX +XXX,XX @@ const RISCVIsaExtData isa_edata_arr[] = {
42
ISA_EXT_DATA_ENTRY(zksed, PRIV_VERSION_1_12_0, ext_zksed),
43
ISA_EXT_DATA_ENTRY(zksh, PRIV_VERSION_1_12_0, ext_zksh),
44
ISA_EXT_DATA_ENTRY(zkt, PRIV_VERSION_1_12_0, ext_zkt),
45
+ ISA_EXT_DATA_ENTRY(ztso, PRIV_VERSION_1_12_0, ext_ztso),
46
ISA_EXT_DATA_ENTRY(zvbb, PRIV_VERSION_1_12_0, ext_zvbb),
38
ISA_EXT_DATA_ENTRY(zvbb, PRIV_VERSION_1_12_0, ext_zvbb),
47
ISA_EXT_DATA_ENTRY(zvbc, PRIV_VERSION_1_12_0, ext_zvbc),
39
ISA_EXT_DATA_ENTRY(zvbc, PRIV_VERSION_1_12_0, ext_zvbc),
48
ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f),
40
ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f),
41
+ ISA_EXT_DATA_ENTRY(zve32x, PRIV_VERSION_1_10_0, ext_zve32x),
42
ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
43
ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),
44
ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin),
49
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
45
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
50
MULTI_EXT_CFG_BOOL("zksed", ext_zksed, false),
46
MULTI_EXT_CFG_BOOL("zfh", ext_zfh, false),
51
MULTI_EXT_CFG_BOOL("zksh", ext_zksh, false),
47
MULTI_EXT_CFG_BOOL("zfhmin", ext_zfhmin, false),
52
MULTI_EXT_CFG_BOOL("zkt", ext_zkt, false),
48
MULTI_EXT_CFG_BOOL("zve32f", ext_zve32f, false),
53
+ MULTI_EXT_CFG_BOOL("ztso", ext_ztso, false),
49
+ MULTI_EXT_CFG_BOOL("zve32x", ext_zve32x, false),
54
50
MULTI_EXT_CFG_BOOL("zve64f", ext_zve64f, false),
55
MULTI_EXT_CFG_BOOL("zdinx", ext_zdinx, false),
51
MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false),
56
MULTI_EXT_CFG_BOOL("zfinx", ext_zfinx, false),
52
MULTI_EXT_CFG_BOOL("zvfbfmin", ext_zvfbfmin, false),
57
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
53
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
58
index XXXXXXX..XXXXXXX 100644
54
index XXXXXXX..XXXXXXX 100644
59
--- a/target/riscv/translate.c
55
--- a/target/riscv/cpu_helper.c
60
+++ b/target/riscv/translate.c
56
+++ b/target/riscv/cpu_helper.c
61
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
57
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
62
/* PointerMasking extension */
58
*pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
63
bool pm_mask_enabled;
59
*cs_base = 0;
64
bool pm_base_enabled;
60
65
+ /* Ztso */
61
- if (cpu->cfg.ext_zve32f) {
66
+ bool ztso;
62
+ if (cpu->cfg.ext_zve32x) {
67
/* Use icount trigger for native debug */
63
/*
68
bool itrigger;
64
* If env->vl equals to VLMAX, we can use generic vector operation
69
/* FRM is known to contain a valid value. */
65
* expanders (GVEC) to accerlate the vector operations.
70
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
66
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
71
ctx->cs = cs;
72
ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED);
73
ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED);
74
+ ctx->ztso = cpu->cfg.ext_ztso;
75
ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER);
76
ctx->zero = tcg_constant_tl(0);
77
ctx->virt_inst_excp = false;
78
diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_trans/trans_rva.c.inc
79
index XXXXXXX..XXXXXXX 100644
67
index XXXXXXX..XXXXXXX 100644
80
--- a/target/riscv/insn_trans/trans_rva.c.inc
68
--- a/target/riscv/csr.c
81
+++ b/target/riscv/insn_trans/trans_rva.c.inc
69
+++ b/target/riscv/csr.c
82
@@ -XXX,XX +XXX,XX @@ static bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop)
70
@@ -XXX,XX +XXX,XX @@ static RISCVException fs(CPURISCVState *env, int csrno)
83
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
71
72
static RISCVException vs(CPURISCVState *env, int csrno)
73
{
74
- if (riscv_cpu_cfg(env)->ext_zve32f) {
75
+ if (riscv_cpu_cfg(env)->ext_zve32x) {
76
#if !defined(CONFIG_USER_ONLY)
77
if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
78
return RISCV_EXCP_ILLEGAL_INST;
79
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
80
index XXXXXXX..XXXXXXX 100644
81
--- a/target/riscv/tcg/tcg-cpu.c
82
+++ b/target/riscv/tcg/tcg-cpu.c
83
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
84
return;
84
}
85
}
85
tcg_gen_qemu_ld_tl(load_val, src1, ctx->mem_idx, mop);
86
86
- if (a->aq) {
87
- if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) {
87
+ /*
88
- error_setg(errp, "Zve32f/Zve64f extensions require F extension");
88
+ * TSO defines AMOs as acquire+release-RCsc, but does not define LR/SC as
89
- return;
89
+ * AMOs. Instead treat them like loads.
90
+ /* The Zve32f extension depends on the Zve32x extension */
90
+ */
91
+ if (cpu->cfg.ext_zve32f) {
91
+ if (a->aq || ctx->ztso) {
92
+ if (!riscv_has_ext(env, RVF)) {
92
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
93
+ error_setg(errp, "Zve32f/Zve64f extensions require F extension");
94
+ return;
95
+ }
96
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32x), true);
93
}
97
}
94
98
95
@@ -XXX,XX +XXX,XX @@ static bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
99
if (cpu->cfg.ext_zvfh) {
96
gen_set_label(l1);
100
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
97
/*
101
cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true);
98
* Address comparison failure. However, we still need to
99
- * provide the memory barrier implied by AQ/RL.
100
+ * provide the memory barrier implied by AQ/RL/TSO.
101
*/
102
- tcg_gen_mb(TCG_MO_ALL + a->aq * TCG_BAR_LDAQ + a->rl * TCG_BAR_STRL);
103
+ TCGBar bar_strl = (ctx->ztso || a->rl) ? TCG_BAR_STRL : 0;
104
+ tcg_gen_mb(TCG_MO_ALL + a->aq * TCG_BAR_LDAQ + bar_strl);
105
gen_set_gpr(ctx, a->rd, tcg_constant_tl(1));
106
107
gen_set_label(l2);
108
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
109
index XXXXXXX..XXXXXXX 100644
110
--- a/target/riscv/insn_trans/trans_rvi.c.inc
111
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
112
@@ -XXX,XX +XXX,XX @@ static bool gen_load_i128(DisasContext *ctx, arg_lb *a, MemOp memop)
113
114
static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop)
115
{
116
+ bool out;
117
+
118
decode_save_opc(ctx);
119
if (get_xl(ctx) == MXL_RV128) {
120
- return gen_load_i128(ctx, a, memop);
121
+ out = gen_load_i128(ctx, a, memop);
122
} else {
123
- return gen_load_tl(ctx, a, memop);
124
+ out = gen_load_tl(ctx, a, memop);
125
+ }
126
+
127
+ if (ctx->ztso) {
128
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
129
}
102
}
130
+
103
131
+ return out;
104
- /*
132
}
105
- * In principle Zve*x would also suffice here, were they supported
133
106
- * in qemu
134
static bool trans_lb(DisasContext *ctx, arg_lb *a)
107
- */
135
@@ -XXX,XX +XXX,XX @@ static bool gen_store_tl(DisasContext *ctx, arg_sb *a, MemOp memop)
108
if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkg ||
136
TCGv addr = get_address(ctx, a->rs1, a->imm);
109
cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed ||
137
TCGv data = get_gpr(ctx, a->rs2, EXT_NONE);
110
- cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32f) {
138
111
+ cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32x) {
139
+ if (ctx->ztso) {
112
error_setg(errp,
140
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
113
"Vector crypto extensions require V or Zve* extensions");
141
+ }
114
return;
142
+
143
tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop);
144
return true;
145
}
146
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
115
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
147
index XXXXXXX..XXXXXXX 100644
116
index XXXXXXX..XXXXXXX 100644
148
--- a/target/riscv/insn_trans/trans_rvv.c.inc
117
--- a/target/riscv/insn_trans/trans_rvv.c.inc
149
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
118
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
150
@@ -XXX,XX +XXX,XX @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
119
@@ -XXX,XX +XXX,XX @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
151
tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd));
120
{
152
tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0));
121
TCGv s1, dst;
153
122
154
+ /*
123
- if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
155
+ * According to the specification
124
+ if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) {
156
+ *
125
return false;
157
+ * Additionally, if the Ztso extension is implemented, then vector memory
158
+ * instructions in the V extension and Zve family of extensions follow
159
+ * RVTSO at the instruction level. The Ztso extension does not
160
+ * strengthen the ordering of intra-instruction element accesses.
161
+ *
162
+ * as a result neither ordered nor unordered accesses from the V
163
+ * instructions need ordering within the loop but we do still need barriers
164
+ * around the loop.
165
+ */
166
+ if (is_store && s->ztso) {
167
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
168
+ }
169
+
170
fn(dest, mask, base, tcg_env, desc);
171
172
+ if (!is_store && s->ztso) {
173
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
174
+ }
175
+
176
if (!is_store) {
177
mark_vs_dirty(s);
178
}
126
}
127
128
@@ -XXX,XX +XXX,XX @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2)
129
{
130
TCGv dst;
131
132
- if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
133
+ if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) {
134
return false;
135
}
136
179
--
137
--
180
2.44.0
138
2.45.1
181
182
diff view generated by jsdifflib
[PULL 08/34] target/riscv: add riscv,isa to named features
[PULL 11/28] target/riscv: Add support for Zve64x extension
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
1
From: Jason Chien <jason.chien@sifive.com>
2
2
3
Further discussions after the introduction of rva22 support in QEMU
3
Add support for Zve64x extension. Enabling Zve64f enables Zve64x and
4
revealed that what we've been calling 'named features' are actually
4
enabling Zve64x enables Zve32x according to their dependency.
5
regular extensions, with their respective riscv,isa DTs. This is
6
clarified in [1]. [2] is a bug tracker asking for the profile spec to be
7
less cryptic about it.
8
5
9
As far as QEMU goes we understand extensions as something that the user
6
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2107
10
can enable/disable in the command line. This isn't the case for named
7
Signed-off-by: Jason Chien <jason.chien@sifive.com>
11
features, so we'll have to reach a middle ground.
8
Reviewed-by: Frank Chang <frank.chang@sifive.com>
12
9
Reviewed-by: Max Chou <max.chou@sifive.com>
13
We'll keep our existing nomenclature 'named features' to refer to any
10
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
14
extension that the user can't control in the command line. We'll also do
11
Message-ID: <20240328022343.6871-3-jason.chien@sifive.com>
15
the following:
16
17
- 'svade' and 'zic64b' flags are renamed to 'ext_svade' and
18
'ext_zic64b'. 'ext_svade' and 'ext_zic64b' now have riscv,isa strings and
19
priv_spec versions;
20
21
- skip name feature check in cpu_bump_multi_ext_priv_ver(). Now that
22
named features have a riscv,isa and an entry in isa_edata_arr[] we
23
don't need to gate the call to cpu_cfg_ext_get_min_version() anymore.
24
25
[1] https://github.com/riscv/riscv-profiles/issues/121
26
[2] https://github.com/riscv/riscv-profiles/issues/142
27
28
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
29
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
30
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
31
Message-ID: <20240215223955.969568-3-dbarboza@ventanamicro.com>
32
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
33
---
13
---
34
target/riscv/cpu_cfg.h | 6 ++++--
14
target/riscv/cpu_cfg.h | 1 +
35
target/riscv/cpu.c | 17 +++++++++++++----
15
target/riscv/cpu.c | 2 ++
36
target/riscv/tcg/tcg-cpu.c | 16 ++++++----------
16
target/riscv/tcg/tcg-cpu.c | 17 +++++++++++------
37
3 files changed, 23 insertions(+), 16 deletions(-)
17
3 files changed, 14 insertions(+), 6 deletions(-)
38
18
39
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
19
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
40
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
41
--- a/target/riscv/cpu_cfg.h
21
--- a/target/riscv/cpu_cfg.h
42
+++ b/target/riscv/cpu_cfg.h
22
+++ b/target/riscv/cpu_cfg.h
43
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
23
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
44
bool ext_smepmp;
24
bool ext_zve32x;
45
bool rvv_ta_all_1s;
25
bool ext_zve64f;
46
bool rvv_ma_all_1s;
26
bool ext_zve64d;
47
- bool svade;
27
+ bool ext_zve64x;
48
- bool zic64b;
28
bool ext_zvbb;
49
29
bool ext_zvbc;
50
uint32_t mvendorid;
30
bool ext_zvkb;
51
uint64_t marchid;
52
uint64_t mimpid;
53
54
+ /* Named features */
55
+ bool ext_svade;
56
+ bool ext_zic64b;
57
+
58
/* Vendor-specific custom extensions */
59
bool ext_xtheadba;
60
bool ext_xtheadbb;
61
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
31
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
62
index XXXXXXX..XXXXXXX 100644
32
index XXXXXXX..XXXXXXX 100644
63
--- a/target/riscv/cpu.c
33
--- a/target/riscv/cpu.c
64
+++ b/target/riscv/cpu.c
34
+++ b/target/riscv/cpu.c
65
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_option_set(const char *optname)
66
* instead.
67
*/
68
const RISCVIsaExtData isa_edata_arr[] = {
69
+ ISA_EXT_DATA_ENTRY(zic64b, PRIV_VERSION_1_12_0, ext_zic64b),
70
ISA_EXT_DATA_ENTRY(zicbom, PRIV_VERSION_1_12_0, ext_zicbom),
71
ISA_EXT_DATA_ENTRY(zicbop, PRIV_VERSION_1_12_0, ext_zicbop),
72
ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_zicboz),
73
@@ -XXX,XX +XXX,XX @@ const RISCVIsaExtData isa_edata_arr[] = {
35
@@ -XXX,XX +XXX,XX @@ const RISCVIsaExtData isa_edata_arr[] = {
74
ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia),
36
ISA_EXT_DATA_ENTRY(zve32x, PRIV_VERSION_1_10_0, ext_zve32x),
75
ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf),
37
ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
76
ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc),
38
ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),
77
+ ISA_EXT_DATA_ENTRY(svade, PRIV_VERSION_1_11_0, ext_svade),
39
+ ISA_EXT_DATA_ENTRY(zve64x, PRIV_VERSION_1_10_0, ext_zve64x),
78
ISA_EXT_DATA_ENTRY(svadu, PRIV_VERSION_1_12_0, ext_svadu),
40
ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin),
79
ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval),
41
ISA_EXT_DATA_ENTRY(zvfbfwma, PRIV_VERSION_1_12_0, ext_zvfbfwma),
80
ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot),
42
ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh),
81
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
43
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
82
DEFINE_PROP_END_OF_LIST(),
44
MULTI_EXT_CFG_BOOL("zve32x", ext_zve32x, false),
83
};
45
MULTI_EXT_CFG_BOOL("zve64f", ext_zve64f, false),
84
46
MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false),
85
+/*
47
+ MULTI_EXT_CFG_BOOL("zve64x", ext_zve64x, false),
86
+ * 'Named features' is the name we give to extensions that we
48
MULTI_EXT_CFG_BOOL("zvfbfmin", ext_zvfbfmin, false),
87
+ * don't want to expose to users. They are either immutable
49
MULTI_EXT_CFG_BOOL("zvfbfwma", ext_zvfbfwma, false),
88
+ * (always enabled/disable) or they'll vary depending on
50
MULTI_EXT_CFG_BOOL("zvfh", ext_zvfh, false),
89
+ * the resulting CPU state. They have riscv,isa strings
90
+ * and priv_ver like regular extensions.
91
+ */
92
const RISCVCPUMultiExtConfig riscv_cpu_named_features[] = {
93
- MULTI_EXT_CFG_BOOL("svade", svade, true),
94
- MULTI_EXT_CFG_BOOL("zic64b", zic64b, true),
95
+ MULTI_EXT_CFG_BOOL("svade", ext_svade, true),
96
+ MULTI_EXT_CFG_BOOL("zic64b", ext_zic64b, true),
97
98
DEFINE_PROP_END_OF_LIST(),
99
};
100
@@ -XXX,XX +XXX,XX @@ static RISCVCPUProfile RVA22U64 = {
101
CPU_CFG_OFFSET(ext_zicbop), CPU_CFG_OFFSET(ext_zicboz),
102
103
/* mandatory named features for this profile */
104
- CPU_CFG_OFFSET(zic64b),
105
+ CPU_CFG_OFFSET(ext_zic64b),
106
107
RISCV_PROFILE_EXT_LIST_END
108
}
109
@@ -XXX,XX +XXX,XX @@ static RISCVCPUProfile RVA22S64 = {
110
CPU_CFG_OFFSET(ext_svinval),
111
112
/* rva22s64 named features */
113
- CPU_CFG_OFFSET(svade),
114
+ CPU_CFG_OFFSET(ext_svade),
115
116
RISCV_PROFILE_EXT_LIST_END
117
}
118
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
51
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
119
index XXXXXXX..XXXXXXX 100644
52
index XXXXXXX..XXXXXXX 100644
120
--- a/target/riscv/tcg/tcg-cpu.c
53
--- a/target/riscv/tcg/tcg-cpu.c
121
+++ b/target/riscv/tcg/tcg-cpu.c
54
+++ b/target/riscv/tcg/tcg-cpu.c
122
@@ -XXX,XX +XXX,XX @@ static bool cpu_cfg_offset_is_named_feat(uint32_t ext_offset)
55
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
123
static void riscv_cpu_enable_named_feat(RISCVCPU *cpu, uint32_t feat_offset)
56
124
{
57
/* The Zve64d extension depends on the Zve64f extension */
125
switch (feat_offset) {
58
if (cpu->cfg.ext_zve64d) {
126
- case CPU_CFG_OFFSET(zic64b):
59
+ if (!riscv_has_ext(env, RVD)) {
127
+ case CPU_CFG_OFFSET(ext_zic64b):
60
+ error_setg(errp, "Zve64d/V extensions require D extension");
128
cpu->cfg.cbom_blocksize = 64;
61
+ return;
129
cpu->cfg.cbop_blocksize = 64;
62
+ }
130
cpu->cfg.cboz_blocksize = 64;
63
cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64f), true);
131
break;
64
}
132
- case CPU_CFG_OFFSET(svade):
65
133
+ case CPU_CFG_OFFSET(ext_svade):
66
- /* The Zve64f extension depends on the Zve32f extension */
134
cpu->cfg.ext_svadu = false;
67
+ /* The Zve64f extension depends on the Zve64x and Zve32f extensions */
135
break;
68
if (cpu->cfg.ext_zve64f) {
136
default:
69
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64x), true);
137
@@ -XXX,XX +XXX,XX @@ static void cpu_bump_multi_ext_priv_ver(CPURISCVState *env,
70
cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32f), true);
71
}
72
73
- if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) {
74
- error_setg(errp, "Zve64d/V extensions require D extension");
75
- return;
76
+ /* The Zve64x extension depends on the Zve32x extension */
77
+ if (cpu->cfg.ext_zve64x) {
78
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32x), true);
79
}
80
81
/* The Zve32f extension depends on the Zve32x extension */
82
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
138
return;
83
return;
139
}
84
}
140
85
141
- if (cpu_cfg_offset_is_named_feat(ext_offset)) {
86
- if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64f) {
142
- return;
87
+ if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64x) {
143
- }
88
error_setg(
144
-
89
errp,
145
ext_priv_ver = cpu_cfg_ext_get_min_version(ext_offset);
90
- "Zvbc and Zvknhb extensions require V or Zve64{f,d} extensions");
146
91
+ "Zvbc and Zvknhb extensions require V or Zve64x extensions");
147
if (env->priv_ver < ext_priv_ver) {
92
return;
148
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
93
}
149
94
150
static void riscv_cpu_update_named_features(RISCVCPU *cpu)
151
{
152
- cpu->cfg.zic64b = cpu->cfg.cbom_blocksize == 64 &&
153
- cpu->cfg.cbop_blocksize == 64 &&
154
- cpu->cfg.cboz_blocksize == 64;
155
+ cpu->cfg.ext_zic64b = cpu->cfg.cbom_blocksize == 64 &&
156
+ cpu->cfg.cbop_blocksize == 64 &&
157
+ cpu->cfg.cboz_blocksize == 64;
158
159
- cpu->cfg.svade = !cpu->cfg.ext_svadu;
160
+ cpu->cfg.ext_svade = !cpu->cfg.ext_svadu;
161
}
162
163
static void riscv_cpu_validate_g(RISCVCPU *cpu)
164
--
95
--
165
2.44.0
96
2.45.1
diff view generated by jsdifflib
[PULL 01/34] target/riscv: Update $ra with current $pc in trans_cm_jalt()
[PULL 12/28] target/riscv: Relax vector register check in RISCV gdbstub
1
From: Jason Chien <jason.chien@sifive.com>
1
From: Jason Chien <jason.chien@sifive.com>
2
2
3
The original implementation sets $pc to the address read from the jump
3
In current implementation, the gdbstub allows reading vector registers
4
vector table first and links $ra with the address of the next instruction
4
only if V extension is supported. However, all vector extensions and
5
after the updated $pc. After jumping to the updated $pc and executing the
5
vector crypto extensions have the vector registers and they all depend
6
next ret instruction, the program jumps to $ra, which is in the same
6
on Zve32x. The gdbstub should check for Zve32x instead.
7
function currently executing, which results in an infinite loop.
8
This commit stores the jump address in a temporary, updates $ra with the
9
current $pc, and copies the temporary to $pc.
10
7
11
Signed-off-by: Jason Chien <jason.chien@sifive.com>
8
Signed-off-by: Jason Chien <jason.chien@sifive.com>
12
Reviewed-by: Frank Chang <frank.chang@sifive.com>
9
Reviewed-by: Frank Chang <frank.chang@sifive.com>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Max Chou <max.chou@sifive.com>
14
Message-ID: <20240207081820.28559-1-jason.chien@sifive.com>
11
Message-ID: <20240328022343.6871-4-jason.chien@sifive.com>
15
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
16
---
13
---
17
target/riscv/insn_trans/trans_rvzce.c.inc | 6 +++++-
14
target/riscv/gdbstub.c | 2 +-
18
1 file changed, 5 insertions(+), 1 deletion(-)
15
1 file changed, 1 insertion(+), 1 deletion(-)
19
16
20
diff --git a/target/riscv/insn_trans/trans_rvzce.c.inc b/target/riscv/insn_trans/trans_rvzce.c.inc
17
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
21
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
22
--- a/target/riscv/insn_trans/trans_rvzce.c.inc
19
--- a/target/riscv/gdbstub.c
23
+++ b/target/riscv/insn_trans/trans_rvzce.c.inc
20
+++ b/target/riscv/gdbstub.c
24
@@ -XXX,XX +XXX,XX @@ static bool trans_cm_jalt(DisasContext *ctx, arg_cm_jalt *a)
21
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
25
{
22
gdb_find_static_feature("riscv-32bit-fpu.xml"),
26
REQUIRE_ZCMT(ctx);
23
0);
27
28
+ TCGv addr = tcg_temp_new();
29
+
30
/*
31
* Update pc to current for the non-unwinding exception
32
* that might come from cpu_ld*_code() in the helper.
33
*/
34
gen_update_pc(ctx, 0);
35
- gen_helper_cm_jalt(cpu_pc, tcg_env, tcg_constant_i32(a->index));
36
+ gen_helper_cm_jalt(addr, tcg_env, tcg_constant_i32(a->index));
37
38
/* c.jt vs c.jalt depends on the index. */
39
if (a->index >= 32) {
40
@@ -XXX,XX +XXX,XX @@ static bool trans_cm_jalt(DisasContext *ctx, arg_cm_jalt *a)
41
gen_set_gpr(ctx, xRA, succ_pc);
42
}
24
}
43
25
- if (env->misa_ext & RVV) {
44
+ tcg_gen_mov_tl(cpu_pc, addr);
26
+ if (cpu->cfg.ext_zve32x) {
45
+
27
gdb_register_coprocessor(cs, riscv_gdb_get_vector,
46
tcg_gen_lookup_and_goto_ptr();
28
riscv_gdb_set_vector,
47
ctx->base.is_jmp = DISAS_NORETURN;
29
ricsv_gen_dynamic_vector_feature(cs, cs->gdb_num_regs),
48
return true;
49
--
30
--
50
2.44.0
31
2.45.1
diff view generated by jsdifflib
[PULL 02/34] hw/arm/virt-acpi-build.c: Migrate SPCR creation to common location
Deleted patch
1
From: Sia Jee Heng <jeeheng.sia@starfivetech.com>
2
1
3
RISC-V should also generate the SPCR in a manner similar to ARM.
4
Therefore, instead of replicating the code, relocate this function
5
to the common AML build.
6
7
Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-ID: <20240129021440.17640-2-jeeheng.sia@starfivetech.com>
10
[ Changes by AF:
11
- Add missing Language SPCR entry
12
]
13
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
---
15
include/hw/acpi/acpi-defs.h | 33 ++++++++++++++++++
16
include/hw/acpi/aml-build.h | 4 +++
17
hw/acpi/aml-build.c | 53 +++++++++++++++++++++++++++++
18
hw/arm/virt-acpi-build.c | 68 +++++++++++++++----------------------
19
4 files changed, 117 insertions(+), 41 deletions(-)
20
21
diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h
22
index XXXXXXX..XXXXXXX 100644
23
--- a/include/hw/acpi/acpi-defs.h
24
+++ b/include/hw/acpi/acpi-defs.h
25
@@ -XXX,XX +XXX,XX @@ typedef struct AcpiFadtData {
26
unsigned *xdsdt_tbl_offset;
27
} AcpiFadtData;
28
29
+typedef struct AcpiGas {
30
+ uint8_t id; /* Address space ID */
31
+ uint8_t width; /* Register bit width */
32
+ uint8_t offset; /* Register bit offset */
33
+ uint8_t size; /* Access size */
34
+ uint64_t addr; /* Address */
35
+} AcpiGas;
36
+
37
+/* SPCR (Serial Port Console Redirection table) */
38
+typedef struct AcpiSpcrData {
39
+ uint8_t interface_type;
40
+ uint8_t reserved[3];
41
+ struct AcpiGas base_addr;
42
+ uint8_t interrupt_type;
43
+ uint8_t pc_interrupt;
44
+ uint32_t interrupt; /* Global system interrupt */
45
+ uint8_t baud_rate;
46
+ uint8_t parity;
47
+ uint8_t stop_bits;
48
+ uint8_t flow_control;
49
+ uint8_t terminal_type;
50
+ uint8_t language;
51
+ uint8_t reserved1;
52
+ uint16_t pci_device_id; /* Must be 0xffff if not PCI device */
53
+ uint16_t pci_vendor_id; /* Must be 0xffff if not PCI device */
54
+ uint8_t pci_bus;
55
+ uint8_t pci_device;
56
+ uint8_t pci_function;
57
+ uint32_t pci_flags;
58
+ uint8_t pci_segment;
59
+ uint32_t reserved2;
60
+} AcpiSpcrData;
61
+
62
#define ACPI_FADT_ARM_PSCI_COMPLIANT (1 << 0)
63
#define ACPI_FADT_ARM_PSCI_USE_HVC (1 << 1)
64
65
diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
66
index XXXXXXX..XXXXXXX 100644
67
--- a/include/hw/acpi/aml-build.h
68
+++ b/include/hw/acpi/aml-build.h
69
@@ -XXX,XX +XXX,XX @@ void build_fadt(GArray *tbl, BIOSLinker *linker, const AcpiFadtData *f,
70
71
void build_tpm2(GArray *table_data, BIOSLinker *linker, GArray *tcpalog,
72
const char *oem_id, const char *oem_table_id);
73
+
74
+void build_spcr(GArray *table_data, BIOSLinker *linker,
75
+ const AcpiSpcrData *f, const uint8_t rev,
76
+ const char *oem_id, const char *oem_table_id);
77
#endif
78
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
79
index XXXXXXX..XXXXXXX 100644
80
--- a/hw/acpi/aml-build.c
81
+++ b/hw/acpi/aml-build.c
82
@@ -XXX,XX +XXX,XX @@ static void build_processor_hierarchy_node(GArray *tbl, uint32_t flags,
83
}
84
}
85
86
+void build_spcr(GArray *table_data, BIOSLinker *linker,
87
+ const AcpiSpcrData *f, const uint8_t rev,
88
+ const char *oem_id, const char *oem_table_id)
89
+{
90
+ AcpiTable table = { .sig = "SPCR", .rev = rev, .oem_id = oem_id,
91
+ .oem_table_id = oem_table_id };
92
+
93
+ acpi_table_begin(&table, table_data);
94
+ /* Interface type */
95
+ build_append_int_noprefix(table_data, f->interface_type, 1);
96
+ /* Reserved */
97
+ build_append_int_noprefix(table_data, 0, 3);
98
+ /* Base Address */
99
+ build_append_gas(table_data, f->base_addr.id, f->base_addr.width,
100
+ f->base_addr.offset, f->base_addr.size,
101
+ f->base_addr.addr);
102
+ /* Interrupt type */
103
+ build_append_int_noprefix(table_data, f->interrupt_type, 1);
104
+ /* IRQ */
105
+ build_append_int_noprefix(table_data, f->pc_interrupt, 1);
106
+ /* Global System Interrupt */
107
+ build_append_int_noprefix(table_data, f->interrupt, 4);
108
+ /* Baud Rate */
109
+ build_append_int_noprefix(table_data, f->baud_rate, 1);
110
+ /* Parity */
111
+ build_append_int_noprefix(table_data, f->parity, 1);
112
+ /* Stop Bits */
113
+ build_append_int_noprefix(table_data, f->stop_bits, 1);
114
+ /* Flow Control */
115
+ build_append_int_noprefix(table_data, f->flow_control, 1);
116
+ /* Language */
117
+ build_append_int_noprefix(table_data, f->language, 1);
118
+ /* Terminal Type */
119
+ build_append_int_noprefix(table_data, f->terminal_type, 1);
120
+ /* PCI Device ID */
121
+ build_append_int_noprefix(table_data, f->pci_device_id, 2);
122
+ /* PCI Vendor ID */
123
+ build_append_int_noprefix(table_data, f->pci_vendor_id, 2);
124
+ /* PCI Bus Number */
125
+ build_append_int_noprefix(table_data, f->pci_bus, 1);
126
+ /* PCI Device Number */
127
+ build_append_int_noprefix(table_data, f->pci_device, 1);
128
+ /* PCI Function Number */
129
+ build_append_int_noprefix(table_data, f->pci_function, 1);
130
+ /* PCI Flags */
131
+ build_append_int_noprefix(table_data, f->pci_flags, 4);
132
+ /* PCI Segment */
133
+ build_append_int_noprefix(table_data, f->pci_segment, 1);
134
+ /* Reserved */
135
+ build_append_int_noprefix(table_data, 0, 4);
136
+
137
+ acpi_table_end(linker, &table);
138
+}
139
/*
140
* ACPI spec, Revision 6.3
141
* 5.2.29 Processor Properties Topology Table (PPTT)
142
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
143
index XXXXXXX..XXXXXXX 100644
144
--- a/hw/arm/virt-acpi-build.c
145
+++ b/hw/arm/virt-acpi-build.c
146
@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
147
* Rev: 1.07
148
*/
149
static void
150
-build_spcr(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
151
+spcr_setup(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
152
{
153
- AcpiTable table = { .sig = "SPCR", .rev = 2, .oem_id = vms->oem_id,
154
- .oem_table_id = vms->oem_table_id };
155
-
156
- acpi_table_begin(&table, table_data);
157
-
158
- /* Interface Type */
159
- build_append_int_noprefix(table_data, 3, 1); /* ARM PL011 UART */
160
- build_append_int_noprefix(table_data, 0, 3); /* Reserved */
161
- /* Base Address */
162
- build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 32, 0, 3,
163
- vms->memmap[VIRT_UART].base);
164
- /* Interrupt Type */
165
- build_append_int_noprefix(table_data,
166
- (1 << 3) /* Bit[3] ARMH GIC interrupt */, 1);
167
- build_append_int_noprefix(table_data, 0, 1); /* IRQ */
168
- /* Global System Interrupt */
169
- build_append_int_noprefix(table_data,
170
- vms->irqmap[VIRT_UART] + ARM_SPI_BASE, 4);
171
- build_append_int_noprefix(table_data, 3 /* 9600 */, 1); /* Baud Rate */
172
- build_append_int_noprefix(table_data, 0 /* No Parity */, 1); /* Parity */
173
- /* Stop Bits */
174
- build_append_int_noprefix(table_data, 1 /* 1 Stop bit */, 1);
175
- /* Flow Control */
176
- build_append_int_noprefix(table_data,
177
- (1 << 1) /* RTS/CTS hardware flow control */, 1);
178
- /* Terminal Type */
179
- build_append_int_noprefix(table_data, 0 /* VT100 */, 1);
180
- build_append_int_noprefix(table_data, 0, 1); /* Language */
181
- /* PCI Device ID */
182
- build_append_int_noprefix(table_data, 0xffff /* not a PCI device*/, 2);
183
- /* PCI Vendor ID */
184
- build_append_int_noprefix(table_data, 0xffff /* not a PCI device*/, 2);
185
- build_append_int_noprefix(table_data, 0, 1); /* PCI Bus Number */
186
- build_append_int_noprefix(table_data, 0, 1); /* PCI Device Number */
187
- build_append_int_noprefix(table_data, 0, 1); /* PCI Function Number */
188
- build_append_int_noprefix(table_data, 0, 4); /* PCI Flags */
189
- build_append_int_noprefix(table_data, 0, 1); /* PCI Segment */
190
- build_append_int_noprefix(table_data, 0, 4); /* Reserved */
191
+ AcpiSpcrData serial = {
192
+ .interface_type = 3, /* ARM PL011 UART */
193
+ .base_addr.id = AML_AS_SYSTEM_MEMORY,
194
+ .base_addr.width = 32,
195
+ .base_addr.offset = 0,
196
+ .base_addr.size = 3,
197
+ .base_addr.addr = vms->memmap[VIRT_UART].base,
198
+ .interrupt_type = (1 << 3),/* Bit[3] ARMH GIC interrupt*/
199
+ .pc_interrupt = 0, /* IRQ */
200
+ .interrupt = (vms->irqmap[VIRT_UART] + ARM_SPI_BASE),
201
+ .baud_rate = 3, /* 9600 */
202
+ .parity = 0, /* No Parity */
203
+ .stop_bits = 1, /* 1 Stop bit */
204
+ .flow_control = 1 << 1, /* RTS/CTS hardware flow control */
205
+ .terminal_type = 0, /* VT100 */
206
+ .language = 0, /* Language */
207
+ .pci_device_id = 0xffff, /* not a PCI device*/
208
+ .pci_vendor_id = 0xffff, /* not a PCI device*/
209
+ .pci_bus = 0,
210
+ .pci_device = 0,
211
+ .pci_function = 0,
212
+ .pci_flags = 0,
213
+ .pci_segment = 0,
214
+ };
215
216
- acpi_table_end(linker, &table);
217
+ build_spcr(table_data, linker, &serial, 2, vms->oem_id, vms->oem_table_id);
218
}
219
220
/*
221
@@ -XXX,XX +XXX,XX @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables)
222
}
223
224
acpi_add_table(table_offsets, tables_blob);
225
- build_spcr(tables_blob, tables->linker, vms);
226
+ spcr_setup(tables_blob, tables->linker, vms);
227
228
acpi_add_table(table_offsets, tables_blob);
229
build_dbg2(tables_blob, tables->linker, vms);
230
--
231
2.44.0
diff view generated by jsdifflib
[PULL 03/34] hw/riscv/virt-acpi-build.c: Generate SPCR table
Deleted patch
1
From: Sia Jee Heng <jeeheng.sia@starfivetech.com>
2
1
3
Generate Serial Port Console Redirection Table (SPCR) for RISC-V
4
virtual machine.
5
6
Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com>
7
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
8
Message-ID: <20240129021440.17640-3-jeeheng.sia@starfivetech.com>
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
---
11
hw/riscv/virt-acpi-build.c | 39 ++++++++++++++++++++++++++++++++++++++
12
1 file changed, 39 insertions(+)
13
14
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/riscv/virt-acpi-build.c
17
+++ b/hw/riscv/virt-acpi-build.c
18
@@ -XXX,XX +XXX,XX @@ acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap,
19
aml_append(scope, dev);
20
}
21
22
+/*
23
+ * Serial Port Console Redirection Table (SPCR)
24
+ * Rev: 1.07
25
+ */
26
+
27
+static void
28
+spcr_setup(GArray *table_data, BIOSLinker *linker, RISCVVirtState *s)
29
+{
30
+ AcpiSpcrData serial = {
31
+ .interface_type = 0, /* 16550 compatible */
32
+ .base_addr.id = AML_AS_SYSTEM_MEMORY,
33
+ .base_addr.width = 32,
34
+ .base_addr.offset = 0,
35
+ .base_addr.size = 1,
36
+ .base_addr.addr = s->memmap[VIRT_UART0].base,
37
+ .interrupt_type = (1 << 4),/* Bit[4] RISC-V PLIC/APLIC */
38
+ .pc_interrupt = 0,
39
+ .interrupt = UART0_IRQ,
40
+ .baud_rate = 7, /* 15200 */
41
+ .parity = 0,
42
+ .stop_bits = 1,
43
+ .flow_control = 0,
44
+ .terminal_type = 3, /* ANSI */
45
+ .language = 0, /* Language */
46
+ .pci_device_id = 0xffff, /* not a PCI device*/
47
+ .pci_vendor_id = 0xffff, /* not a PCI device*/
48
+ .pci_bus = 0,
49
+ .pci_device = 0,
50
+ .pci_function = 0,
51
+ .pci_flags = 0,
52
+ .pci_segment = 0,
53
+ };
54
+
55
+ build_spcr(table_data, linker, &serial, 2, s->oem_id, s->oem_table_id);
56
+}
57
+
58
/* RHCT Node[N] starts at offset 56 */
59
#define RHCT_NODE_ARRAY_OFFSET 56
60
61
@@ -XXX,XX +XXX,XX @@ static void virt_acpi_build(RISCVVirtState *s, AcpiBuildTables *tables)
62
acpi_add_table(table_offsets, tables_blob);
63
build_rhct(tables_blob, tables->linker, s);
64
65
+ acpi_add_table(table_offsets, tables_blob);
66
+ spcr_setup(tables_blob, tables->linker, s);
67
+
68
acpi_add_table(table_offsets, tables_blob);
69
{
70
AcpiMcfgInfo mcfg = {
71
--
72
2.44.0
diff view generated by jsdifflib
[PULL 05/34] linux-user/riscv: Add Zicboz extensions to hwprobe
Deleted patch
1
From: Christoph Müllner <christoph.muellner@vrull.eu>
2
1
3
Upstream Linux recently added RISC-V Zicboz support to the hwprobe API.
4
This patch introduces this for QEMU's user space emulator.
5
6
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
7
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
8
Message-ID: <20240207115926.887816-2-christoph.muellner@vrull.eu>
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
---
11
linux-user/syscall.c | 3 +++
12
1 file changed, 3 insertions(+)
13
14
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/linux-user/syscall.c
17
+++ b/linux-user/syscall.c
18
@@ -XXX,XX +XXX,XX @@ static int do_getdents64(abi_long dirfd, abi_long arg2, abi_long count)
19
#define RISCV_HWPROBE_EXT_ZBA (1 << 3)
20
#define RISCV_HWPROBE_EXT_ZBB (1 << 4)
21
#define RISCV_HWPROBE_EXT_ZBS (1 << 5)
22
+#define RISCV_HWPROBE_EXT_ZICBOZ (1 << 6)
23
24
#define RISCV_HWPROBE_KEY_CPUPERF_0 5
25
#define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
26
@@ -XXX,XX +XXX,XX @@ static void risc_hwprobe_fill_pairs(CPURISCVState *env,
27
RISCV_HWPROBE_EXT_ZBB : 0;
28
value |= cfg->ext_zbs ?
29
RISCV_HWPROBE_EXT_ZBS : 0;
30
+ value |= cfg->ext_zicboz ?
31
+ RISCV_HWPROBE_EXT_ZICBOZ : 0;
32
__put_user(value, &pair->value);
33
break;
34
case RISCV_HWPROBE_KEY_CPUPERF_0:
35
--
36
2.44.0
37
38
diff view generated by jsdifflib
[PULL 06/34] linux-user/riscv: Sync hwprobe keys with Linux
Deleted patch
1
From: Christoph Müllner <christoph.muellner@vrull.eu>
2
1
3
Upstream Linux recently added many additional keys to the hwprobe API.
4
This patch adds support for all of them with the exception of Ztso,
5
which is currently not supported in QEMU.
6
7
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
8
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
9
Message-ID: <20240207115926.887816-3-christoph.muellner@vrull.eu>
10
[ Changes by AF:
11
- Fixup whitespace
12
]
13
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
---
15
linux-user/syscall.c | 100 +++++++++++++++++++++++++++++++++++++++----
16
1 file changed, 92 insertions(+), 8 deletions(-)
17
18
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/linux-user/syscall.c
21
+++ b/linux-user/syscall.c
22
@@ -XXX,XX +XXX,XX @@ static int do_getdents64(abi_long dirfd, abi_long arg2, abi_long count)
23
#define RISCV_HWPROBE_KEY_BASE_BEHAVIOR 3
24
#define RISCV_HWPROBE_BASE_BEHAVIOR_IMA (1 << 0)
25
26
-#define RISCV_HWPROBE_KEY_IMA_EXT_0 4
27
-#define RISCV_HWPROBE_IMA_FD (1 << 0)
28
-#define RISCV_HWPROBE_IMA_C (1 << 1)
29
-#define RISCV_HWPROBE_IMA_V (1 << 2)
30
-#define RISCV_HWPROBE_EXT_ZBA (1 << 3)
31
-#define RISCV_HWPROBE_EXT_ZBB (1 << 4)
32
-#define RISCV_HWPROBE_EXT_ZBS (1 << 5)
33
-#define RISCV_HWPROBE_EXT_ZICBOZ (1 << 6)
34
+#define RISCV_HWPROBE_KEY_IMA_EXT_0 4
35
+#define RISCV_HWPROBE_IMA_FD (1 << 0)
36
+#define RISCV_HWPROBE_IMA_C (1 << 1)
37
+#define RISCV_HWPROBE_IMA_V (1 << 2)
38
+#define RISCV_HWPROBE_EXT_ZBA (1 << 3)
39
+#define RISCV_HWPROBE_EXT_ZBB (1 << 4)
40
+#define RISCV_HWPROBE_EXT_ZBS (1 << 5)
41
+#define RISCV_HWPROBE_EXT_ZICBOZ (1 << 6)
42
+#define RISCV_HWPROBE_EXT_ZBC (1 << 7)
43
+#define RISCV_HWPROBE_EXT_ZBKB (1 << 8)
44
+#define RISCV_HWPROBE_EXT_ZBKC (1 << 9)
45
+#define RISCV_HWPROBE_EXT_ZBKX (1 << 10)
46
+#define RISCV_HWPROBE_EXT_ZKND (1 << 11)
47
+#define RISCV_HWPROBE_EXT_ZKNE (1 << 12)
48
+#define RISCV_HWPROBE_EXT_ZKNH (1 << 13)
49
+#define RISCV_HWPROBE_EXT_ZKSED (1 << 14)
50
+#define RISCV_HWPROBE_EXT_ZKSH (1 << 15)
51
+#define RISCV_HWPROBE_EXT_ZKT (1 << 16)
52
+#define RISCV_HWPROBE_EXT_ZVBB (1 << 17)
53
+#define RISCV_HWPROBE_EXT_ZVBC (1 << 18)
54
+#define RISCV_HWPROBE_EXT_ZVKB (1 << 19)
55
+#define RISCV_HWPROBE_EXT_ZVKG (1 << 20)
56
+#define RISCV_HWPROBE_EXT_ZVKNED (1 << 21)
57
+#define RISCV_HWPROBE_EXT_ZVKNHA (1 << 22)
58
+#define RISCV_HWPROBE_EXT_ZVKNHB (1 << 23)
59
+#define RISCV_HWPROBE_EXT_ZVKSED (1 << 24)
60
+#define RISCV_HWPROBE_EXT_ZVKSH (1 << 25)
61
+#define RISCV_HWPROBE_EXT_ZVKT (1 << 26)
62
+#define RISCV_HWPROBE_EXT_ZFH (1 << 27)
63
+#define RISCV_HWPROBE_EXT_ZFHMIN (1 << 28)
64
+#define RISCV_HWPROBE_EXT_ZIHINTNTL (1 << 29)
65
+#define RISCV_HWPROBE_EXT_ZVFH (1 << 30)
66
+#define RISCV_HWPROBE_EXT_ZVFHMIN (1 << 31)
67
+#define RISCV_HWPROBE_EXT_ZFA (1ULL << 32)
68
+#define RISCV_HWPROBE_EXT_ZACAS (1ULL << 34)
69
+#define RISCV_HWPROBE_EXT_ZICOND (1ULL << 35)
70
71
#define RISCV_HWPROBE_KEY_CPUPERF_0 5
72
#define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
73
@@ -XXX,XX +XXX,XX @@ static void risc_hwprobe_fill_pairs(CPURISCVState *env,
74
RISCV_HWPROBE_EXT_ZBS : 0;
75
value |= cfg->ext_zicboz ?
76
RISCV_HWPROBE_EXT_ZICBOZ : 0;
77
+ value |= cfg->ext_zbc ?
78
+ RISCV_HWPROBE_EXT_ZBC : 0;
79
+ value |= cfg->ext_zbkb ?
80
+ RISCV_HWPROBE_EXT_ZBKB : 0;
81
+ value |= cfg->ext_zbkc ?
82
+ RISCV_HWPROBE_EXT_ZBKC : 0;
83
+ value |= cfg->ext_zbkx ?
84
+ RISCV_HWPROBE_EXT_ZBKX : 0;
85
+ value |= cfg->ext_zknd ?
86
+ RISCV_HWPROBE_EXT_ZKND : 0;
87
+ value |= cfg->ext_zkne ?
88
+ RISCV_HWPROBE_EXT_ZKNE : 0;
89
+ value |= cfg->ext_zknh ?
90
+ RISCV_HWPROBE_EXT_ZKNH : 0;
91
+ value |= cfg->ext_zksed ?
92
+ RISCV_HWPROBE_EXT_ZKSED : 0;
93
+ value |= cfg->ext_zksh ?
94
+ RISCV_HWPROBE_EXT_ZKSH : 0;
95
+ value |= cfg->ext_zkt ?
96
+ RISCV_HWPROBE_EXT_ZKT : 0;
97
+ value |= cfg->ext_zvbb ?
98
+ RISCV_HWPROBE_EXT_ZVBB : 0;
99
+ value |= cfg->ext_zvbc ?
100
+ RISCV_HWPROBE_EXT_ZVBC : 0;
101
+ value |= cfg->ext_zvkb ?
102
+ RISCV_HWPROBE_EXT_ZVKB : 0;
103
+ value |= cfg->ext_zvkg ?
104
+ RISCV_HWPROBE_EXT_ZVKG : 0;
105
+ value |= cfg->ext_zvkned ?
106
+ RISCV_HWPROBE_EXT_ZVKNED : 0;
107
+ value |= cfg->ext_zvknha ?
108
+ RISCV_HWPROBE_EXT_ZVKNHA : 0;
109
+ value |= cfg->ext_zvknhb ?
110
+ RISCV_HWPROBE_EXT_ZVKNHB : 0;
111
+ value |= cfg->ext_zvksed ?
112
+ RISCV_HWPROBE_EXT_ZVKSED : 0;
113
+ value |= cfg->ext_zvksh ?
114
+ RISCV_HWPROBE_EXT_ZVKSH : 0;
115
+ value |= cfg->ext_zvkt ?
116
+ RISCV_HWPROBE_EXT_ZVKT : 0;
117
+ value |= cfg->ext_zfh ?
118
+ RISCV_HWPROBE_EXT_ZFH : 0;
119
+ value |= cfg->ext_zfhmin ?
120
+ RISCV_HWPROBE_EXT_ZFHMIN : 0;
121
+ value |= cfg->ext_zihintntl ?
122
+ RISCV_HWPROBE_EXT_ZIHINTNTL : 0;
123
+ value |= cfg->ext_zvfh ?
124
+ RISCV_HWPROBE_EXT_ZVFH : 0;
125
+ value |= cfg->ext_zvfhmin ?
126
+ RISCV_HWPROBE_EXT_ZVFHMIN : 0;
127
+ value |= cfg->ext_zfa ?
128
+ RISCV_HWPROBE_EXT_ZFA : 0;
129
+ value |= cfg->ext_zacas ?
130
+ RISCV_HWPROBE_EXT_ZACAS : 0;
131
+ value |= cfg->ext_zicond ?
132
+ RISCV_HWPROBE_EXT_ZICOND : 0;
133
__put_user(value, &pair->value);
134
break;
135
case RISCV_HWPROBE_KEY_CPUPERF_0:
136
--
137
2.44.0
138
139
diff view generated by jsdifflib
[PULL 31/34] hw/intc/riscv_aplic: Fix setipnum_le write emulation for APLIC MSI-mode
[PULL 13/28] target/riscv: Fix the element agnostic function problem
1
From: Anup Patel <apatel@ventanamicro.com>
1
From: Huang Tao <eric.huang@linux.alibaba.com>
2
2
3
The writes to setipnum_le register in APLIC MSI-mode have special
3
In RVV and vcrypto instructions, the masked and tail elements are set to 1s
4
consideration for level-triggered interrupts as-per section "4.9.2
4
using vext_set_elems_1s function if the vma/vta bit is set. It is the element
5
Special consideration for level-sensitive interrupt sources" of the
5
agnostic policy.
6
RISC-V AIA specification.
7
6
8
Particularly, the below text from the RISC-V specification defines
7
However, this function can't deal the big endian situation. This patch fixes
9
the behaviour of writes to setipnum_le for level-triggered interrupts:
8
the problem by adding handling of such case.
10
9
11
"A second option is for the interrupt service routine to write the
10
Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
12
APLIC’s source identity number for the interrupt to the domain’s
11
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
13
setipnum register just before exiting. This will cause the interrupt’s
12
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
14
pending bit to be set to one again if the source is still asserting
13
Cc: qemu-stable <qemu-stable@nongnu.org>
15
an interrupt, but not if the source is not asserting an interrupt."
14
Message-ID: <20240325021654.6594-1-eric.huang@linux.alibaba.com>
16
17
Fix setipnum_le write emulation for APLIC MSI-mode by implementing
18
the above behaviour in riscv_aplic_set_pending() function.
19
20
Fixes: e8f79343cfc8 ("hw/intc: Add RISC-V AIA APLIC device emulation")
21
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
22
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
23
Message-ID: <20240306095722.463296-2-apatel@ventanamicro.com>
24
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
15
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
25
---
16
---
26
hw/intc/riscv_aplic.c | 20 ++++++++++++++++----
17
target/riscv/vector_internals.c | 22 ++++++++++++++++++++++
27
1 file changed, 16 insertions(+), 4 deletions(-)
18
1 file changed, 22 insertions(+)
28
19
29
diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
20
diff --git a/target/riscv/vector_internals.c b/target/riscv/vector_internals.c
30
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
31
--- a/hw/intc/riscv_aplic.c
22
--- a/target/riscv/vector_internals.c
32
+++ b/hw/intc/riscv_aplic.c
23
+++ b/target/riscv/vector_internals.c
33
@@ -XXX,XX +XXX,XX @@ static void riscv_aplic_set_pending(RISCVAPLICState *aplic,
24
@@ -XXX,XX +XXX,XX @@ void vext_set_elems_1s(void *base, uint32_t is_agnostic, uint32_t cnt,
25
if (tot - cnt == 0) {
26
return ;
34
}
27
}
35
28
+
36
sm = sourcecfg & APLIC_SOURCECFG_SM_MASK;
29
+ if (HOST_BIG_ENDIAN) {
37
- if ((sm == APLIC_SOURCECFG_SM_INACTIVE) ||
30
+ /*
38
- ((!aplic->msimode || (aplic->msimode && !pending)) &&
31
+ * Deal the situation when the elements are insdie
39
- ((sm == APLIC_SOURCECFG_SM_LEVEL_HIGH) ||
32
+ * only one uint64 block including setting the
40
- (sm == APLIC_SOURCECFG_SM_LEVEL_LOW)))) {
33
+ * masked-off element.
41
+ if (sm == APLIC_SOURCECFG_SM_INACTIVE) {
34
+ */
42
return;
35
+ if (((tot - 1) ^ cnt) < 8) {
43
}
36
+ memset(base + H1(tot - 1), -1, tot - cnt);
44
45
+ if ((sm == APLIC_SOURCECFG_SM_LEVEL_HIGH) ||
46
+ (sm == APLIC_SOURCECFG_SM_LEVEL_LOW)) {
47
+ if (!aplic->msimode || (aplic->msimode && !pending)) {
48
+ return;
37
+ return;
49
+ }
38
+ }
50
+ if ((aplic->state[irq] & APLIC_ISTATE_INPUT) &&
39
+ /*
51
+ (sm == APLIC_SOURCECFG_SM_LEVEL_LOW)) {
40
+ * Otherwise, at least cross two uint64_t blocks.
52
+ return;
41
+ * Set first unaligned block.
42
+ */
43
+ if (cnt % 8 != 0) {
44
+ uint32_t j = ROUND_UP(cnt, 8);
45
+ memset(base + H1(j - 1), -1, j - cnt);
46
+ cnt = j;
53
+ }
47
+ }
54
+ if (!(aplic->state[irq] & APLIC_ISTATE_INPUT) &&
48
+ /* Set other 64bit aligend blocks */
55
+ (sm == APLIC_SOURCECFG_SM_LEVEL_HIGH)) {
56
+ return;
57
+ }
58
+ }
49
+ }
59
+
50
memset(base + cnt, -1, tot - cnt);
60
riscv_aplic_set_pending_raw(aplic, irq, pending);
61
}
51
}
62
52
63
--
53
--
64
2.44.0
54
2.45.1
65
66
diff view generated by jsdifflib
[PULL 26/34] target/riscv: move ratified/frozen exts to non-experimental
[PULL 14/28] target/riscv/cpu.c: fix Zvkb extension config
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
1
From: Yangyu Chen <cyy@cyyself.name>
2
2
3
smaia and ssaia were ratified in August 25th 2023 [1].
3
This code has a typo that writes zvkb to zvkg, causing users can't
4
enable zvkb through the config. This patch gets this fixed.
4
5
5
zvfh and zvfhmin were ratified in August 2nd 2023 [2].
6
Signed-off-by: Yangyu Chen <cyy@cyyself.name>
6
7
Fixes: ea61ef7097d0 ("target/riscv: Move vector crypto extensions to riscv_cpu_extensions")
7
zfbfmin and zvfbf(min|wma) are frozen and moved to public review since
8
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
8
Dec 16th 2023 [3].
9
10
zaamo and zalrsc are both marked as "Frozen" since January 24th 2024
11
[4].
12
13
[1] https://jira.riscv.org/browse/RVS-438
14
[2] https://jira.riscv.org/browse/RVS-871
15
[3] https://jira.riscv.org/browse/RVS-704
16
[4] https://jira.riscv.org/browse/RVS-1995
17
18
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
19
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
20
Message-ID: <20240301144053.265964-1-dbarboza@ventanamicro.com>
10
Reviewed-by: Max Chou <max.chou@sifive.com>
11
Reviewed-by:  Weiwei Li <liwei1518@gmail.com>
12
Message-ID: <tencent_7E34EEF0F90B9A68BF38BEE09EC6D4877C0A@qq.com>
13
Cc: qemu-stable <qemu-stable@nongnu.org>
21
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
22
---
15
---
23
target/riscv/cpu.c | 22 +++++++++-------------
16
target/riscv/cpu.c | 2 +-
24
1 file changed, 9 insertions(+), 13 deletions(-)
17
1 file changed, 1 insertion(+), 1 deletion(-)
25
18
26
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
19
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
27
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
28
--- a/target/riscv/cpu.c
21
--- a/target/riscv/cpu.c
29
+++ b/target/riscv/cpu.c
22
+++ b/target/riscv/cpu.c
30
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
23
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
31
MULTI_EXT_CFG_BOOL("zihintntl", ext_zihintntl, true),
24
/* Vector cryptography extensions */
32
MULTI_EXT_CFG_BOOL("zihintpause", ext_zihintpause, true),
25
MULTI_EXT_CFG_BOOL("zvbb", ext_zvbb, false),
33
MULTI_EXT_CFG_BOOL("zacas", ext_zacas, false),
26
MULTI_EXT_CFG_BOOL("zvbc", ext_zvbc, false),
34
+ MULTI_EXT_CFG_BOOL("zaamo", ext_zaamo, false),
27
- MULTI_EXT_CFG_BOOL("zvkb", ext_zvkg, false),
35
+ MULTI_EXT_CFG_BOOL("zalrsc", ext_zalrsc, false),
28
+ MULTI_EXT_CFG_BOOL("zvkb", ext_zvkb, false),
36
MULTI_EXT_CFG_BOOL("zawrs", ext_zawrs, true),
29
MULTI_EXT_CFG_BOOL("zvkg", ext_zvkg, false),
37
MULTI_EXT_CFG_BOOL("zfa", ext_zfa, true),
30
MULTI_EXT_CFG_BOOL("zvkned", ext_zvkned, false),
38
+ MULTI_EXT_CFG_BOOL("zfbfmin", ext_zfbfmin, false),
31
MULTI_EXT_CFG_BOOL("zvknha", ext_zvknha, false),
39
MULTI_EXT_CFG_BOOL("zfh", ext_zfh, false),
40
MULTI_EXT_CFG_BOOL("zfhmin", ext_zfhmin, false),
41
MULTI_EXT_CFG_BOOL("zve32f", ext_zve32f, false),
42
MULTI_EXT_CFG_BOOL("zve64f", ext_zve64f, false),
43
MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false),
44
+ MULTI_EXT_CFG_BOOL("zvfbfmin", ext_zvfbfmin, false),
45
+ MULTI_EXT_CFG_BOOL("zvfbfwma", ext_zvfbfwma, false),
46
+ MULTI_EXT_CFG_BOOL("zvfh", ext_zvfh, false),
47
+ MULTI_EXT_CFG_BOOL("zvfhmin", ext_zvfhmin, false),
48
MULTI_EXT_CFG_BOOL("sstc", ext_sstc, true),
49
50
+ MULTI_EXT_CFG_BOOL("smaia", ext_smaia, false),
51
MULTI_EXT_CFG_BOOL("smepmp", ext_smepmp, false),
52
MULTI_EXT_CFG_BOOL("smstateen", ext_smstateen, false),
53
+ MULTI_EXT_CFG_BOOL("ssaia", ext_ssaia, false),
54
MULTI_EXT_CFG_BOOL("svade", ext_svade, false),
55
MULTI_EXT_CFG_BOOL("svadu", ext_svadu, true),
56
MULTI_EXT_CFG_BOOL("svinval", ext_svinval, false),
57
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
58
59
/* These are experimental so mark with 'x-' */
60
const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
61
- MULTI_EXT_CFG_BOOL("x-smaia", ext_smaia, false),
62
- MULTI_EXT_CFG_BOOL("x-ssaia", ext_ssaia, false),
63
-
64
- MULTI_EXT_CFG_BOOL("x-zaamo", ext_zaamo, false),
65
- MULTI_EXT_CFG_BOOL("x-zalrsc", ext_zalrsc, false),
66
-
67
- MULTI_EXT_CFG_BOOL("x-zvfh", ext_zvfh, false),
68
- MULTI_EXT_CFG_BOOL("x-zvfhmin", ext_zvfhmin, false),
69
-
70
- MULTI_EXT_CFG_BOOL("x-zfbfmin", ext_zfbfmin, false),
71
- MULTI_EXT_CFG_BOOL("x-zvfbfmin", ext_zvfbfmin, false),
72
- MULTI_EXT_CFG_BOOL("x-zvfbfwma", ext_zvfbfwma, false),
73
-
74
DEFINE_PROP_END_OF_LIST(),
75
};
76
77
--
32
--
78
2.44.0
33
2.45.1
34
35
diff view generated by jsdifflib
[PULL 11/34] target/riscv: Gate hardware A/D PTE bit updating
[PULL 15/28] target/riscv: Implement dynamic establishment of custom decoder
1
From: Andrew Jones <ajones@ventanamicro.com>
1
From: Huang Tao <eric.huang@linux.alibaba.com>
2
2
3
Gate hardware A/D PTE bit updating on {m,h}envcfg.ADUE and only
3
In this patch, we modify the decoder to be a freely composable data
4
enable menvcfg.ADUE on reset if svade has not been selected. Now
4
structure instead of a hardcoded one. It can be dynamically builded up
5
that we also consider svade, we have four possible configurations:
5
according to the extensions.
6
This approach has several benefits:
7
1. Provides support for heterogeneous cpu architectures. As we add decoder in
8
RISCVCPU, each cpu can have their own decoder, and the decoders can be
9
different due to cpu's features.
10
2. Improve the decoding efficiency. We run the guard_func to see if the decoder
11
can be added to the dynamic_decoder when building up the decoder. Therefore,
12
there is no need to run the guard_func when decoding each instruction. It can
13
improve the decoding efficiency
14
3. For vendor or dynamic cpus, it allows them to customize their own decoder
15
functions to improve decoding efficiency, especially when vendor-defined
16
instruction sets increase. Because of dynamic building up, it can skip the other
17
decoder guard functions when decoding.
18
4. Pre patch for allowing adding a vendor decoder before decode_insn32() with minimal
19
overhead for users that don't need this particular vendor decoder.
6
20
7
1) !svade && !svadu
21
Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
8
use hardware updating and there's no way to disable it
22
Suggested-by: Christoph Muellner <christoph.muellner@vrull.eu>
9
(the default, which maintains past behavior. Maintaining
23
Co-authored-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
10
the default, even with !svadu is a change that fixes [1])
24
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
12
2) !svade && svadu
13
use hardware updating, but also provide {m,h}envcfg.ADUE,
14
allowing software to switch to exception mode
15
(being able to switch is a change which fixes [1])
16
17
3) svade && !svadu
18
use exception mode and there's no way to switch to hardware
19
updating
20
(this behavior change fixes [2])
21
22
4) svade && svadu
23
use exception mode, but also provide {m,h}envcfg.ADUE,
24
allowing software to switch to hardware updating
25
(this behavior change fixes [2])
26
27
Fixes: 0af3f115e68e ("target/riscv: Add *envcfg.HADE related check in address translation") [1]
28
Fixes: 48531f5adb2a ("target/riscv: implement svade") [2]
29
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
30
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
31
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
25
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
32
Message-ID: <20240215223955.969568-6-dbarboza@ventanamicro.com>
26
Message-ID: <20240506023607.29544-1-eric.huang@linux.alibaba.com>
33
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
27
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
34
---
28
---
35
target/riscv/cpu.c | 3 ++-
29
target/riscv/cpu.h | 1 +
36
target/riscv/cpu_helper.c | 19 +++++++++++++++----
30
target/riscv/tcg/tcg-cpu.h | 15 +++++++++++++++
37
target/riscv/tcg/tcg-cpu.c | 15 +++++----------
31
target/riscv/cpu.c | 1 +
38
3 files changed, 22 insertions(+), 15 deletions(-)
32
target/riscv/tcg/tcg-cpu.c | 15 +++++++++++++++
33
target/riscv/translate.c | 31 +++++++++++++++----------------
34
5 files changed, 47 insertions(+), 16 deletions(-)
39
35
36
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
37
index XXXXXXX..XXXXXXX 100644
38
--- a/target/riscv/cpu.h
39
+++ b/target/riscv/cpu.h
40
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
41
uint32_t pmu_avail_ctrs;
42
/* Mapping of events to counters */
43
GHashTable *pmu_event_ctr_map;
44
+ const GPtrArray *decoders;
45
};
46
47
/**
48
diff --git a/target/riscv/tcg/tcg-cpu.h b/target/riscv/tcg/tcg-cpu.h
49
index XXXXXXX..XXXXXXX 100644
50
--- a/target/riscv/tcg/tcg-cpu.h
51
+++ b/target/riscv/tcg/tcg-cpu.h
52
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp);
53
void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp);
54
bool riscv_cpu_tcg_compatible(RISCVCPU *cpu);
55
56
+struct DisasContext;
57
+struct RISCVCPUConfig;
58
+typedef struct RISCVDecoder {
59
+ bool (*guard_func)(const struct RISCVCPUConfig *);
60
+ bool (*riscv_cpu_decode_fn)(struct DisasContext *, uint32_t);
61
+} RISCVDecoder;
62
+
63
+typedef bool (*riscv_cpu_decode_fn)(struct DisasContext *, uint32_t);
64
+
65
+extern const size_t decoder_table_size;
66
+
67
+extern const RISCVDecoder decoder_table[];
68
+
69
+void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu);
70
+
71
#endif
40
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
72
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
41
index XXXXXXX..XXXXXXX 100644
73
index XXXXXXX..XXXXXXX 100644
42
--- a/target/riscv/cpu.c
74
--- a/target/riscv/cpu.c
43
+++ b/target/riscv/cpu.c
75
+++ b/target/riscv/cpu.c
44
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset_hold(Object *obj)
76
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
45
env->two_stage_lookup = false;
77
error_propagate(errp, local_err);
46
78
return;
47
env->menvcfg = (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0) |
79
}
48
- (cpu->cfg.ext_svadu ? MENVCFG_ADUE : 0);
80
+ riscv_tcg_cpu_finalize_dynamic_decoder(cpu);
49
+ (!cpu->cfg.ext_svade && cpu->cfg.ext_svadu ?
81
} else if (kvm_enabled()) {
50
+ MENVCFG_ADUE : 0);
82
riscv_kvm_cpu_finalize_features(cpu, &local_err);
51
env->henvcfg = 0;
83
if (local_err != NULL) {
52
53
/* Initialized default priorities of local interrupts. */
54
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
55
index XXXXXXX..XXXXXXX 100644
56
--- a/target/riscv/cpu_helper.c
57
+++ b/target/riscv/cpu_helper.c
58
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
59
}
60
61
bool pbmte = env->menvcfg & MENVCFG_PBMTE;
62
- bool adue = env->menvcfg & MENVCFG_ADUE;
63
+ bool svade = riscv_cpu_cfg(env)->ext_svade;
64
+ bool svadu = riscv_cpu_cfg(env)->ext_svadu;
65
+ bool adue = svadu ? env->menvcfg & MENVCFG_ADUE : !svade;
66
67
if (first_stage && two_stage && env->virt_enabled) {
68
pbmte = pbmte && (env->henvcfg & HENVCFG_PBMTE);
69
@@ -XXX,XX +XXX,XX @@ restart:
70
return TRANSLATE_FAIL;
71
}
72
73
- /* If necessary, set accessed and dirty bits. */
74
- target_ulong updated_pte = pte | PTE_A |
75
- (access_type == MMU_DATA_STORE ? PTE_D : 0);
76
+ target_ulong updated_pte = pte;
77
+
78
+ /*
79
+ * If ADUE is enabled, set accessed and dirty bits.
80
+ * Otherwise raise an exception if necessary.
81
+ */
82
+ if (adue) {
83
+ updated_pte |= PTE_A | (access_type == MMU_DATA_STORE ? PTE_D : 0);
84
+ } else if (!(pte & PTE_A) ||
85
+ (access_type == MMU_DATA_STORE && !(pte & PTE_D))) {
86
+ return TRANSLATE_FAIL;
87
+ }
88
89
/* Page table updates need to be atomic with MTTCG enabled */
90
if (updated_pte != pte && !is_debug) {
91
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
84
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
92
index XXXXXXX..XXXXXXX 100644
85
index XXXXXXX..XXXXXXX 100644
93
--- a/target/riscv/tcg/tcg-cpu.c
86
--- a/target/riscv/tcg/tcg-cpu.c
94
+++ b/target/riscv/tcg/tcg-cpu.c
87
+++ b/target/riscv/tcg/tcg-cpu.c
95
@@ -XXX,XX +XXX,XX @@ static bool cpu_cfg_offset_is_named_feat(uint32_t ext_offset)
88
@@ -XXX,XX +XXX,XX @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
96
97
static void riscv_cpu_enable_named_feat(RISCVCPU *cpu, uint32_t feat_offset)
98
{
99
- switch (feat_offset) {
100
- case CPU_CFG_OFFSET(ext_zic64b):
101
+ /*
102
+ * All other named features are already enabled
103
+ * in riscv_tcg_cpu_instance_init().
104
+ */
105
+ if (feat_offset == CPU_CFG_OFFSET(ext_zic64b)) {
106
cpu->cfg.cbom_blocksize = 64;
107
cpu->cfg.cbop_blocksize = 64;
108
cpu->cfg.cboz_blocksize = 64;
109
- break;
110
- case CPU_CFG_OFFSET(ext_svade):
111
- cpu->cfg.ext_svadu = false;
112
- break;
113
- default:
114
- g_assert_not_reached();
115
}
89
}
116
}
90
}
117
91
118
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_update_named_features(RISCVCPU *cpu)
92
+void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu)
119
cpu->cfg.ext_zic64b = cpu->cfg.cbom_blocksize == 64 &&
93
+{
120
cpu->cfg.cbop_blocksize == 64 &&
94
+ GPtrArray *dynamic_decoders;
121
cpu->cfg.cboz_blocksize == 64;
95
+ dynamic_decoders = g_ptr_array_sized_new(decoder_table_size);
96
+ for (size_t i = 0; i < decoder_table_size; ++i) {
97
+ if (decoder_table[i].guard_func &&
98
+ decoder_table[i].guard_func(&cpu->cfg)) {
99
+ g_ptr_array_add(dynamic_decoders,
100
+ (gpointer)decoder_table[i].riscv_cpu_decode_fn);
101
+ }
102
+ }
103
+
104
+ cpu->decoders = dynamic_decoders;
105
+}
106
+
107
bool riscv_cpu_tcg_compatible(RISCVCPU *cpu)
108
{
109
return object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST) == NULL;
110
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
111
index XXXXXXX..XXXXXXX 100644
112
--- a/target/riscv/translate.c
113
+++ b/target/riscv/translate.c
114
@@ -XXX,XX +XXX,XX @@
115
#include "exec/helper-info.c.inc"
116
#undef HELPER_H
117
118
+#include "tcg/tcg-cpu.h"
119
+
120
/* global register indices */
121
static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart;
122
static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
123
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
124
/* FRM is known to contain a valid value. */
125
bool frm_valid;
126
bool insn_start_updated;
127
+ const GPtrArray *decoders;
128
} DisasContext;
129
130
static inline bool has_ext(DisasContext *ctx, uint32_t ext)
131
@@ -XXX,XX +XXX,XX @@ static inline int insn_len(uint16_t first_word)
132
return (first_word & 3) == 3 ? 4 : 2;
133
}
134
135
+const RISCVDecoder decoder_table[] = {
136
+ { always_true_p, decode_insn32 },
137
+ { has_xthead_p, decode_xthead},
138
+ { has_XVentanaCondOps_p, decode_XVentanaCodeOps},
139
+};
140
+
141
+const size_t decoder_table_size = ARRAY_SIZE(decoder_table);
142
+
143
static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
144
{
145
- /*
146
- * A table with predicate (i.e., guard) functions and decoder functions
147
- * that are tested in-order until a decoder matches onto the opcode.
148
- */
149
- static const struct {
150
- bool (*guard_func)(const RISCVCPUConfig *);
151
- bool (*decode_func)(DisasContext *, uint32_t);
152
- } decoders[] = {
153
- { always_true_p, decode_insn32 },
154
- { has_xthead_p, decode_xthead },
155
- { has_XVentanaCondOps_p, decode_XVentanaCodeOps },
156
- };
122
-
157
-
123
- cpu->cfg.ext_svade = !cpu->cfg.ext_svadu;
158
ctx->virt_inst_excp = false;
159
ctx->cur_insn_len = insn_len(opcode);
160
/* Check for compressed insn */
161
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
162
ctx->base.pc_next + 2));
163
ctx->opcode = opcode32;
164
165
- for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) {
166
- if (decoders[i].guard_func(ctx->cfg_ptr) &&
167
- decoders[i].decode_func(ctx, opcode32)) {
168
+ for (guint i = 0; i < ctx->decoders->len; ++i) {
169
+ riscv_cpu_decode_fn func = g_ptr_array_index(ctx->decoders, i);
170
+ if (func(ctx, opcode32)) {
171
return;
172
}
173
}
174
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
175
ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER);
176
ctx->zero = tcg_constant_tl(0);
177
ctx->virt_inst_excp = false;
178
+ ctx->decoders = cpu->decoders;
124
}
179
}
125
180
126
static void riscv_cpu_validate_g(RISCVCPU *cpu)
181
static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)
127
--
182
--
128
2.44.0
183
2.45.1
diff view generated by jsdifflib
[PULL 22/34] linux-user/riscv: Add Ztso extension to hwprobe
[PULL 16/28] riscv: thead: Add th.sxstatus CSR emulation
1
From: Christoph Müllner <christoph.muellner@vrull.eu>
1
From: Christoph Müllner <christoph.muellner@vrull.eu>
2
2
3
This patch exposes Ztso via hwprobe in QEMU's user space emulator.
3
The th.sxstatus CSR can be used to identify available custom extension
4
on T-Head CPUs. The CSR is documented here:
5
https://github.com/T-head-Semi/thead-extension-spec/blob/master/xtheadsxstatus.adoc
4
6
7
An important property of this patch is, that the th.sxstatus MAEE field
8
is not set (indicating that XTheadMae is not available).
9
XTheadMae is a memory attribute extension (similar to Svpbmt) which is
10
implemented in many T-Head CPUs (C906, C910, etc.) and utilizes bits
11
in PTEs that are marked as reserved. QEMU maintainers prefer to not
12
implement XTheadMae, so we need give kernels a mechanism to identify
13
if XTheadMae is available in a system or not. And this patch introduces
14
this mechanism in QEMU in a way that's compatible with real HW
15
(i.e., probing the th.sxstatus.MAEE bit).
16
17
Further context can be found on the list:
18
https://lists.gnu.org/archive/html/qemu-devel/2024-02/msg00775.html
19
20
Reviewed-by: LIU Zhiwei <zhiwe_liu@linux.alibaba.com>
21
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
5
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
22
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
6
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
23
Message-ID: <20240429073656.2486732-1-christoph.muellner@vrull.eu>
7
Message-ID: <20240207122256.902627-3-christoph.muellner@vrull.eu>
8
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
24
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
9
---
25
---
10
linux-user/syscall.c | 3 +++
26
MAINTAINERS | 1 +
11
1 file changed, 3 insertions(+)
27
target/riscv/cpu.h | 3 ++
28
target/riscv/cpu.c | 1 +
29
target/riscv/th_csr.c | 79 ++++++++++++++++++++++++++++++++++++++++
30
target/riscv/meson.build | 1 +
31
5 files changed, 85 insertions(+)
32
create mode 100644 target/riscv/th_csr.c
12
33
13
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
34
diff --git a/MAINTAINERS b/MAINTAINERS
14
index XXXXXXX..XXXXXXX 100644
35
index XXXXXXX..XXXXXXX 100644
15
--- a/linux-user/syscall.c
36
--- a/MAINTAINERS
16
+++ b/linux-user/syscall.c
37
+++ b/MAINTAINERS
17
@@ -XXX,XX +XXX,XX @@ static int do_getdents64(abi_long dirfd, abi_long arg2, abi_long count)
38
@@ -XXX,XX +XXX,XX @@ L: qemu-riscv@nongnu.org
18
#define RISCV_HWPROBE_EXT_ZVFH (1 << 30)
39
S: Supported
19
#define RISCV_HWPROBE_EXT_ZVFHMIN (1 << 31)
40
F: target/riscv/insn_trans/trans_xthead.c.inc
20
#define RISCV_HWPROBE_EXT_ZFA (1ULL << 32)
41
F: target/riscv/xthead*.decode
21
+#define RISCV_HWPROBE_EXT_ZTSO (1ULL << 33)
42
+F: target/riscv/th_*
22
#define RISCV_HWPROBE_EXT_ZACAS (1ULL << 34)
43
F: disas/riscv-xthead*
23
#define RISCV_HWPROBE_EXT_ZICOND (1ULL << 35)
44
24
45
RISC-V XVentanaCondOps extension
25
@@ -XXX,XX +XXX,XX @@ static void risc_hwprobe_fill_pairs(CPURISCVState *env,
46
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
26
RISCV_HWPROBE_EXT_ZVFHMIN : 0;
47
index XXXXXXX..XXXXXXX 100644
27
value |= cfg->ext_zfa ?
48
--- a/target/riscv/cpu.h
28
RISCV_HWPROBE_EXT_ZFA : 0;
49
+++ b/target/riscv/cpu.h
29
+ value |= cfg->ext_ztso ?
50
@@ -XXX,XX +XXX,XX @@ target_ulong riscv_new_csr_seed(target_ulong new_value,
30
+ RISCV_HWPROBE_EXT_ZTSO : 0;
51
uint8_t satp_mode_max_from_map(uint32_t map);
31
value |= cfg->ext_zacas ?
52
const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
32
RISCV_HWPROBE_EXT_ZACAS : 0;
53
33
value |= cfg->ext_zicond ?
54
+/* Implemented in th_csr.c */
55
+void th_register_custom_csrs(RISCVCPU *cpu);
56
+
57
#endif /* RISCV_CPU_H */
58
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
59
index XXXXXXX..XXXXXXX 100644
60
--- a/target/riscv/cpu.c
61
+++ b/target/riscv/cpu.c
62
@@ -XXX,XX +XXX,XX @@ static void rv64_thead_c906_cpu_init(Object *obj)
63
cpu->cfg.mvendorid = THEAD_VENDOR_ID;
64
#ifndef CONFIG_USER_ONLY
65
set_satp_mode_max_supported(cpu, VM_1_10_SV39);
66
+ th_register_custom_csrs(cpu);
67
#endif
68
69
/* inherited from parent obj via riscv_cpu_init() */
70
diff --git a/target/riscv/th_csr.c b/target/riscv/th_csr.c
71
new file mode 100644
72
index XXXXXXX..XXXXXXX
73
--- /dev/null
74
+++ b/target/riscv/th_csr.c
75
@@ -XXX,XX +XXX,XX @@
76
+/*
77
+ * T-Head-specific CSRs.
78
+ *
79
+ * Copyright (c) 2024 VRULL GmbH
80
+ *
81
+ * This program is free software; you can redistribute it and/or modify it
82
+ * under the terms and conditions of the GNU General Public License,
83
+ * version 2 or later, as published by the Free Software Foundation.
84
+ *
85
+ * This program is distributed in the hope it will be useful, but WITHOUT
86
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
87
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
88
+ * more details.
89
+ *
90
+ * You should have received a copy of the GNU General Public License along with
91
+ * this program. If not, see <http://www.gnu.org/licenses/>.
92
+ */
93
+
94
+#include "qemu/osdep.h"
95
+#include "cpu.h"
96
+#include "cpu_vendorid.h"
97
+
98
+#define CSR_TH_SXSTATUS 0x5c0
99
+
100
+/* TH_SXSTATUS bits */
101
+#define TH_SXSTATUS_UCME BIT(16)
102
+#define TH_SXSTATUS_MAEE BIT(21)
103
+#define TH_SXSTATUS_THEADISAEE BIT(22)
104
+
105
+typedef struct {
106
+ int csrno;
107
+ int (*insertion_test)(RISCVCPU *cpu);
108
+ riscv_csr_operations csr_ops;
109
+} riscv_csr;
110
+
111
+static RISCVException smode(CPURISCVState *env, int csrno)
112
+{
113
+ if (riscv_has_ext(env, RVS)) {
114
+ return RISCV_EXCP_NONE;
115
+ }
116
+
117
+ return RISCV_EXCP_ILLEGAL_INST;
118
+}
119
+
120
+static int test_thead_mvendorid(RISCVCPU *cpu)
121
+{
122
+ if (cpu->cfg.mvendorid != THEAD_VENDOR_ID) {
123
+ return -1;
124
+ }
125
+
126
+ return 0;
127
+}
128
+
129
+static RISCVException read_th_sxstatus(CPURISCVState *env, int csrno,
130
+ target_ulong *val)
131
+{
132
+ /* We don't set MAEE here, because QEMU does not implement MAEE. */
133
+ *val = TH_SXSTATUS_UCME | TH_SXSTATUS_THEADISAEE;
134
+ return RISCV_EXCP_NONE;
135
+}
136
+
137
+static riscv_csr th_csr_list[] = {
138
+ {
139
+ .csrno = CSR_TH_SXSTATUS,
140
+ .insertion_test = test_thead_mvendorid,
141
+ .csr_ops = { "th.sxstatus", smode, read_th_sxstatus }
142
+ }
143
+};
144
+
145
+void th_register_custom_csrs(RISCVCPU *cpu)
146
+{
147
+ for (size_t i = 0; i < ARRAY_SIZE(th_csr_list); i++) {
148
+ int csrno = th_csr_list[i].csrno;
149
+ riscv_csr_operations *csr_ops = &th_csr_list[i].csr_ops;
150
+ if (!th_csr_list[i].insertion_test(cpu)) {
151
+ riscv_set_csr_ops(csrno, csr_ops);
152
+ }
153
+ }
154
+}
155
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
156
index XXXXXXX..XXXXXXX 100644
157
--- a/target/riscv/meson.build
158
+++ b/target/riscv/meson.build
159
@@ -XXX,XX +XXX,XX @@ riscv_system_ss.add(files(
160
'monitor.c',
161
'machine.c',
162
'pmu.c',
163
+ 'th_csr.c',
164
'time_helper.c',
165
'riscv-qmp-cmds.c',
166
))
34
--
167
--
35
2.44.0
168
2.45.1
36
169
37
170
diff view generated by jsdifflib
[PULL 16/34] hw/riscv/virt-acpi-build.c: Add SRAT and SLIT ACPI tables
[PULL 17/28] target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
1
From: Haibo Xu <haibo1.xu@intel.com>
1
From: Max Chou <max.chou@sifive.com>
2
2
3
Enable ACPI NUMA support by adding the following 2 ACPI tables:
3
According v spec 18.4, only the vfwcvt.f.f.v and vfncvt.f.f.w
4
SRAT: provides the association for memory/Harts and Proximity Domains
4
instructions will be affected by Zvfhmin extension.
5
SLIT: provides the relative distance between Proximity Domains
5
And the vfwcvt.f.f.v and vfncvt.f.f.w instructions only support the
6
conversions of
6
7
7
The SRAT RINTC Affinity Structure definition[1] was based on the recently
8
* From 1*SEW(16/32) to 2*SEW(32/64)
8
approved ACPI CodeFirst ECR[2].
9
* From 2*SEW(32/64) to 1*SEW(16/32)
9
10
10
[1] https://github.com/riscv-non-isa/riscv-acpi/issues/25
11
Signed-off-by: Max Chou <max.chou@sifive.com>
11
[2] https://mantis.uefi.org/mantis/view.php?id=2433
12
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
12
13
Cc: qemu-stable <qemu-stable@nongnu.org>
13
Signed-off-by: Haibo Xu <haibo1.xu@intel.com>
14
Message-ID: <20240322092600.1198921-2-max.chou@sifive.com>
14
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
15
Message-ID: <20240129094200.3581037-1-haibo1.xu@intel.com>
16
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
15
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
17
---
16
---
18
hw/riscv/virt-acpi-build.c | 60 ++++++++++++++++++++++++++++++++++++++
17
target/riscv/insn_trans/trans_rvv.c.inc | 20 ++++++++++++++++++--
19
1 file changed, 60 insertions(+)
18
1 file changed, 18 insertions(+), 2 deletions(-)
20
19
21
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
20
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
22
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
23
--- a/hw/riscv/virt-acpi-build.c
22
--- a/target/riscv/insn_trans/trans_rvv.c.inc
24
+++ b/hw/riscv/virt-acpi-build.c
23
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
25
@@ -XXX,XX +XXX,XX @@ static void build_madt(GArray *table_data,
24
@@ -XXX,XX +XXX,XX @@ static bool require_rvf(DisasContext *s)
26
acpi_table_end(linker, &table);
25
}
27
}
26
}
28
27
29
+/*
28
+static bool require_rvfmin(DisasContext *s)
30
+ * ACPI spec, Revision 6.5+
31
+ * 5.2.16 System Resource Affinity Table (SRAT)
32
+ * REF: https://github.com/riscv-non-isa/riscv-acpi/issues/25
33
+ * https://drive.google.com/file/d/1YTdDx2IPm5IeZjAW932EYU-tUtgS08tX/view
34
+ */
35
+static void
36
+build_srat(GArray *table_data, BIOSLinker *linker, RISCVVirtState *vms)
37
+{
29
+{
38
+ int i;
30
+ if (s->mstatus_fs == EXT_STATUS_DISABLED) {
39
+ uint64_t mem_base;
31
+ return false;
40
+ MachineClass *mc = MACHINE_GET_CLASS(vms);
41
+ MachineState *ms = MACHINE(vms);
42
+ const CPUArchIdList *cpu_list = mc->possible_cpu_arch_ids(ms);
43
+ AcpiTable table = { .sig = "SRAT", .rev = 3, .oem_id = vms->oem_id,
44
+ .oem_table_id = vms->oem_table_id };
45
+
46
+ acpi_table_begin(&table, table_data);
47
+ build_append_int_noprefix(table_data, 1, 4); /* Reserved */
48
+ build_append_int_noprefix(table_data, 0, 8); /* Reserved */
49
+
50
+ for (i = 0; i < cpu_list->len; ++i) {
51
+ uint32_t nodeid = cpu_list->cpus[i].props.node_id;
52
+ /*
53
+ * 5.2.16.8 RINTC Affinity Structure
54
+ */
55
+ build_append_int_noprefix(table_data, 7, 1); /* Type */
56
+ build_append_int_noprefix(table_data, 20, 1); /* Length */
57
+ build_append_int_noprefix(table_data, 0, 2); /* Reserved */
58
+ build_append_int_noprefix(table_data, nodeid, 4); /* Proximity Domain */
59
+ build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */
60
+ /* Flags, Table 5-70 */
61
+ build_append_int_noprefix(table_data, 1 /* Flags: Enabled */, 4);
62
+ build_append_int_noprefix(table_data, 0, 4); /* Clock Domain */
63
+ }
32
+ }
64
+
33
+
65
+ mem_base = vms->memmap[VIRT_DRAM].base;
34
+ switch (s->sew) {
66
+ for (i = 0; i < ms->numa_state->num_nodes; ++i) {
35
+ case MO_16:
67
+ if (ms->numa_state->nodes[i].node_mem > 0) {
36
+ return s->cfg_ptr->ext_zvfhmin;
68
+ build_srat_memory(table_data, mem_base,
37
+ case MO_32:
69
+ ms->numa_state->nodes[i].node_mem, i,
38
+ return s->cfg_ptr->ext_zve32f;
70
+ MEM_AFFINITY_ENABLED);
39
+ default:
71
+ mem_base += ms->numa_state->nodes[i].node_mem;
40
+ return false;
72
+ }
73
+ }
41
+ }
74
+
75
+ acpi_table_end(linker, &table);
76
+}
42
+}
77
+
43
+
78
static void virt_acpi_build(RISCVVirtState *s, AcpiBuildTables *tables)
44
static bool require_scale_rvf(DisasContext *s)
79
{
45
{
80
GArray *table_offsets;
46
if (s->mstatus_fs == EXT_STATUS_DISABLED) {
81
unsigned dsdt, xsdt;
47
@@ -XXX,XX +XXX,XX @@ static bool require_scale_rvfmin(DisasContext *s)
82
GArray *tables_blob = tables->table_data;
83
+ MachineState *ms = MACHINE(s);
84
85
table_offsets = g_array_new(false, true,
86
sizeof(uint32_t));
87
@@ -XXX,XX +XXX,XX @@ static void virt_acpi_build(RISCVVirtState *s, AcpiBuildTables *tables)
88
s->oem_table_id);
89
}
48
}
90
49
91
+ if (ms->numa_state->num_nodes > 0) {
50
switch (s->sew) {
92
+ acpi_add_table(table_offsets, tables_blob);
51
- case MO_8:
93
+ build_srat(tables_blob, tables->linker, s);
52
- return s->cfg_ptr->ext_zvfhmin;
94
+ if (ms->numa_state->have_numa_distance) {
53
case MO_16:
95
+ acpi_add_table(table_offsets, tables_blob);
54
return s->cfg_ptr->ext_zve32f;
96
+ build_slit(tables_blob, tables->linker, ms, s->oem_id,
55
case MO_32:
97
+ s->oem_table_id);
56
@@ -XXX,XX +XXX,XX @@ static bool opxfv_widen_check(DisasContext *s, arg_rmr *a)
98
+ }
57
static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
99
+ }
58
{
100
+
59
return opfv_widen_check(s, a) &&
101
/* XSDT is pointed to by RSDP */
60
+ require_rvfmin(s) &&
102
xsdt = tables_blob->len;
61
require_scale_rvfmin(s) &&
103
build_xsdt(tables_blob, tables->linker, table_offsets, s->oem_id,
62
(s->sew != MO_8);
63
}
64
@@ -XXX,XX +XXX,XX @@ static bool opfxv_narrow_check(DisasContext *s, arg_rmr *a)
65
static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
66
{
67
return opfv_narrow_check(s, a) &&
68
+ require_rvfmin(s) &&
69
require_scale_rvfmin(s) &&
70
(s->sew != MO_8);
71
}
104
--
72
--
105
2.44.0
73
2.45.1
diff view generated by jsdifflib
[PULL 34/34] target/riscv: fix ACPI MCFG table
[PULL 18/28] target/riscv: rvv: Check single width operator for vector fp widen instructions
1
From: Ilya Chugin <danger_mail@list.ru>
1
From: Max Chou <max.chou@sifive.com>
2
2
3
MCFG segments should point to PCI configuration range, not BAR MMIO.
3
The require_scale_rvf function only checks the double width operator for
4
the vector floating point widen instructions, so most of the widen
5
checking functions need to add require_rvf for single width operator.
4
6
5
Signed-off-by: Ilya Chugin <danger_mail@list.ru>
7
The vfwcvt.f.x.v and vfwcvt.f.xu.v instructions convert single width
6
Fixes: 55ecd83b36 ("hw/riscv/virt-acpi-build.c: Add IO controllers and devices")
8
integer to double width float, so the opfxv_widen_check function doesn’t
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
need require_rvf for the single width operator(integer).
8
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
10
9
Message-ID: <180d236d-c8e4-411a-b4d2-632eb82092fa@list.ru>
11
Signed-off-by: Max Chou <max.chou@sifive.com>
12
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
13
Cc: qemu-stable <qemu-stable@nongnu.org>
14
Message-ID: <20240322092600.1198921-3-max.chou@sifive.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
15
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
16
---
12
hw/riscv/virt-acpi-build.c | 4 ++--
17
target/riscv/insn_trans/trans_rvv.c.inc | 5 +++++
13
1 file changed, 2 insertions(+), 2 deletions(-)
18
1 file changed, 5 insertions(+)
14
19
15
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
20
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
16
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/riscv/virt-acpi-build.c
22
--- a/target/riscv/insn_trans/trans_rvv.c.inc
18
+++ b/hw/riscv/virt-acpi-build.c
23
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
19
@@ -XXX,XX +XXX,XX @@ static void virt_acpi_build(RISCVVirtState *s, AcpiBuildTables *tables)
24
@@ -XXX,XX +XXX,XX @@ GEN_OPFVF_TRANS(vfrsub_vf, opfvf_check)
20
acpi_add_table(table_offsets, tables_blob);
25
static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
21
{
26
{
22
AcpiMcfgInfo mcfg = {
27
return require_rvv(s) &&
23
- .base = s->memmap[VIRT_PCIE_MMIO].base,
28
+ require_rvf(s) &&
24
- .size = s->memmap[VIRT_PCIE_MMIO].size,
29
require_scale_rvf(s) &&
25
+ .base = s->memmap[VIRT_PCIE_ECAM].base,
30
(s->sew != MO_8) &&
26
+ .size = s->memmap[VIRT_PCIE_ECAM].size,
31
vext_check_isa_ill(s) &&
27
};
32
@@ -XXX,XX +XXX,XX @@ GEN_OPFVV_WIDEN_TRANS(vfwsub_vv, opfvv_widen_check)
28
build_mcfg(tables_blob, tables->linker, &mcfg, s->oem_id,
33
static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
29
s->oem_table_id);
34
{
35
return require_rvv(s) &&
36
+ require_rvf(s) &&
37
require_scale_rvf(s) &&
38
(s->sew != MO_8) &&
39
vext_check_isa_ill(s) &&
40
@@ -XXX,XX +XXX,XX @@ GEN_OPFVF_WIDEN_TRANS(vfwsub_vf)
41
static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
42
{
43
return require_rvv(s) &&
44
+ require_rvf(s) &&
45
require_scale_rvf(s) &&
46
(s->sew != MO_8) &&
47
vext_check_isa_ill(s) &&
48
@@ -XXX,XX +XXX,XX @@ GEN_OPFWV_WIDEN_TRANS(vfwsub_wv)
49
static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
50
{
51
return require_rvv(s) &&
52
+ require_rvf(s) &&
53
require_scale_rvf(s) &&
54
(s->sew != MO_8) &&
55
vext_check_isa_ill(s) &&
56
@@ -XXX,XX +XXX,XX @@ GEN_OPFVV_TRANS(vfredmin_vs, freduction_check)
57
static bool freduction_widen_check(DisasContext *s, arg_rmrr *a)
58
{
59
return reduction_widen_check(s, a) &&
60
+ require_rvf(s) &&
61
require_scale_rvf(s) &&
62
(s->sew != MO_8);
63
}
30
--
64
--
31
2.44.0
65
2.45.1
32
66
33
67
diff view generated by jsdifflib
[PULL 28/34] trans_rvv.c.inc: mark_vs_dirty() before loads and stores
[PULL 19/28] target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
1
From: Max Chou <max.chou@sifive.com>
2
2
3
While discussing a problem with how we're (not) setting vstart_eq_zero
3
The opfv_narrow_check needs to check the single width float operator by
4
Richard had the following to say w.r.t the conditional mark_vs_dirty()
4
require_rvf.
5
calls on load/store functions [1]:
6
5
7
"I think it's required to have stores set dirty unconditionally, before
6
Signed-off-by: Max Chou <max.chou@sifive.com>
8
the operation.
7
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
9
8
Cc: qemu-stable <qemu-stable@nongnu.org>
10
Consider a store that traps on the 2nd element, leaving vstart = 2, and
9
Message-ID: <20240322092600.1198921-4-max.chou@sifive.com>
11
exiting to the main loop via exception. The exception enters the kernel
12
page fault handler. The kernel may need to fault in the page for the
13
process, and in the meantime task switch.
14
15
If vs dirty is not already set, the kernel won't know to save vector
16
state on task switch."
17
18
Do a mark_vs_dirty() before both loads and stores.
19
20
[1] https://lore.kernel.org/qemu-riscv/72c7503b-0f43-44b8-aa82-fbafed2aac0c@linaro.org/
21
22
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
23
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
24
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
25
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
26
Message-ID: <20240306171932.549549-2-dbarboza@ventanamicro.com>
27
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
28
---
11
---
29
target/riscv/insn_trans/trans_rvv.c.inc | 23 ++++++++---------------
12
target/riscv/insn_trans/trans_rvv.c.inc | 1 +
30
1 file changed, 8 insertions(+), 15 deletions(-)
13
1 file changed, 1 insertion(+)
31
14
32
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
15
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
33
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
34
--- a/target/riscv/insn_trans/trans_rvv.c.inc
17
--- a/target/riscv/insn_trans/trans_rvv.c.inc
35
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
18
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
36
@@ -XXX,XX +XXX,XX @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
19
@@ -XXX,XX +XXX,XX @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
37
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
20
static bool opffv_rod_narrow_check(DisasContext *s, arg_rmr *a)
38
}
21
{
39
22
return opfv_narrow_check(s, a) &&
40
+ mark_vs_dirty(s);
23
+ require_rvf(s) &&
41
+
24
require_scale_rvf(s) &&
42
fn(dest, mask, base, tcg_env, desc);
25
(s->sew != MO_8);
43
44
if (!is_store && s->ztso) {
45
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
46
}
47
48
- if (!is_store) {
49
- mark_vs_dirty(s);
50
- }
51
-
52
gen_set_label(over);
53
return true;
54
}
26
}
55
@@ -XXX,XX +XXX,XX @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
56
tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd));
57
tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0));
58
59
- fn(dest, mask, base, stride, tcg_env, desc);
60
+ mark_vs_dirty(s);
61
62
- if (!is_store) {
63
- mark_vs_dirty(s);
64
- }
65
+ fn(dest, mask, base, stride, tcg_env, desc);
66
67
gen_set_label(over);
68
return true;
69
@@ -XXX,XX +XXX,XX @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
70
tcg_gen_addi_ptr(index, tcg_env, vreg_ofs(s, vs2));
71
tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0));
72
73
- fn(dest, mask, base, index, tcg_env, desc);
74
+ mark_vs_dirty(s);
75
76
- if (!is_store) {
77
- mark_vs_dirty(s);
78
- }
79
+ fn(dest, mask, base, index, tcg_env, desc);
80
81
gen_set_label(over);
82
return true;
83
@@ -XXX,XX +XXX,XX @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf,
84
base = get_gpr(s, rs1, EXT_NONE);
85
tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd));
86
87
+ mark_vs_dirty(s);
88
+
89
fn(dest, base, tcg_env, desc);
90
91
- if (!is_store) {
92
- mark_vs_dirty(s);
93
- }
94
gen_set_label(over);
95
96
return true;
97
--
27
--
98
2.44.0
28
2.45.1
diff view generated by jsdifflib
[PULL 29/34] trans_rvv.c.inc: remove 'is_store' bool from load/store fns
[PULL 20/28] target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
1
From: Max Chou <max.chou@sifive.com>
2
2
3
After the 'mark_vs_dirty' changes from the previous patch the 'is_store'
3
If the checking functions check both the single and double width
4
bool is unused in some load/store functions that were changed. Remove it.
4
operators at the same time, then the single width operator checking
5
functions (require_rvf[min]) will check whether the SEW is 8.
5
6
6
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
7
Signed-off-by: Max Chou <max.chou@sifive.com>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
Cc: qemu-stable <qemu-stable@nongnu.org>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Message-ID: <20240322092600.1198921-5-max.chou@sifive.com>
10
Message-ID: <20240306171932.549549-3-dbarboza@ventanamicro.com>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
---
12
---
13
target/riscv/insn_trans/trans_rvv.c.inc | 58 ++++++++++++-------------
13
target/riscv/insn_trans/trans_rvv.c.inc | 16 ++++------------
14
1 file changed, 29 insertions(+), 29 deletions(-)
14
1 file changed, 4 insertions(+), 12 deletions(-)
15
15
16
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
16
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
17
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/riscv/insn_trans/trans_rvv.c.inc
18
--- a/target/riscv/insn_trans/trans_rvv.c.inc
19
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
19
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
20
@@ -XXX,XX +XXX,XX @@ typedef void gen_helper_ldst_stride(TCGv_ptr, TCGv_ptr, TCGv,
20
@@ -XXX,XX +XXX,XX @@ static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
21
21
return require_rvv(s) &&
22
static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
22
require_rvf(s) &&
23
uint32_t data, gen_helper_ldst_stride *fn,
23
require_scale_rvf(s) &&
24
- DisasContext *s, bool is_store)
24
- (s->sew != MO_8) &&
25
+ DisasContext *s)
25
vext_check_isa_ill(s) &&
26
vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm);
27
}
28
@@ -XXX,XX +XXX,XX @@ static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
29
return require_rvv(s) &&
30
require_rvf(s) &&
31
require_scale_rvf(s) &&
32
- (s->sew != MO_8) &&
33
vext_check_isa_ill(s) &&
34
vext_check_ds(s, a->rd, a->rs2, a->vm);
35
}
36
@@ -XXX,XX +XXX,XX @@ static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
37
return require_rvv(s) &&
38
require_rvf(s) &&
39
require_scale_rvf(s) &&
40
- (s->sew != MO_8) &&
41
vext_check_isa_ill(s) &&
42
vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm);
43
}
44
@@ -XXX,XX +XXX,XX @@ static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
45
return require_rvv(s) &&
46
require_rvf(s) &&
47
require_scale_rvf(s) &&
48
- (s->sew != MO_8) &&
49
vext_check_isa_ill(s) &&
50
vext_check_dd(s, a->rd, a->rs2, a->vm);
51
}
52
@@ -XXX,XX +XXX,XX @@ static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
26
{
53
{
27
TCGv_ptr dest, mask;
54
return opfv_widen_check(s, a) &&
28
TCGv base, stride;
55
require_rvfmin(s) &&
29
@@ -XXX,XX +XXX,XX @@ static bool ld_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t eew)
56
- require_scale_rvfmin(s) &&
30
data = FIELD_DP32(data, VDATA, NF, a->nf);
57
- (s->sew != MO_8);
31
data = FIELD_DP32(data, VDATA, VTA, s->vta);
58
+ require_scale_rvfmin(s);
32
data = FIELD_DP32(data, VDATA, VMA, s->vma);
33
- return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s, false);
34
+ return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s);
35
}
59
}
36
60
37
static bool ld_stride_check(DisasContext *s, arg_rnfvm* a, uint8_t eew)
61
#define GEN_OPFV_WIDEN_TRANS(NAME, CHECK, HELPER, FRM) \
38
@@ -XXX,XX +XXX,XX @@ static bool st_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t eew)
62
@@ -XXX,XX +XXX,XX @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
39
return false;
63
{
40
}
64
return opfv_narrow_check(s, a) &&
41
65
require_rvfmin(s) &&
42
- return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s, true);
66
- require_scale_rvfmin(s) &&
43
+ return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s);
67
- (s->sew != MO_8);
68
+ require_scale_rvfmin(s);
44
}
69
}
45
70
46
static bool st_stride_check(DisasContext *s, arg_rnfvm* a, uint8_t eew)
71
static bool opffv_rod_narrow_check(DisasContext *s, arg_rmr *a)
47
@@ -XXX,XX +XXX,XX @@ typedef void gen_helper_ldst_index(TCGv_ptr, TCGv_ptr, TCGv,
48
49
static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
50
uint32_t data, gen_helper_ldst_index *fn,
51
- DisasContext *s, bool is_store)
52
+ DisasContext *s)
53
{
72
{
54
TCGv_ptr dest, mask, index;
73
return opfv_narrow_check(s, a) &&
55
TCGv base;
74
require_rvf(s) &&
56
@@ -XXX,XX +XXX,XX @@ static bool ld_index_op(DisasContext *s, arg_rnfvm *a, uint8_t eew)
75
- require_scale_rvf(s) &&
57
data = FIELD_DP32(data, VDATA, NF, a->nf);
76
- (s->sew != MO_8);
58
data = FIELD_DP32(data, VDATA, VTA, s->vta);
77
+ require_scale_rvf(s);
59
data = FIELD_DP32(data, VDATA, VMA, s->vma);
60
- return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s, false);
61
+ return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s);
62
}
78
}
63
79
64
static bool ld_index_check(DisasContext *s, arg_rnfvm* a, uint8_t eew)
80
#define GEN_OPFV_NARROW_TRANS(NAME, CHECK, HELPER, FRM) \
65
@@ -XXX,XX +XXX,XX @@ static bool st_index_op(DisasContext *s, arg_rnfvm *a, uint8_t eew)
81
@@ -XXX,XX +XXX,XX @@ static bool freduction_widen_check(DisasContext *s, arg_rmrr *a)
66
data = FIELD_DP32(data, VDATA, VM, a->vm);
82
{
67
data = FIELD_DP32(data, VDATA, LMUL, emul);
83
return reduction_widen_check(s, a) &&
68
data = FIELD_DP32(data, VDATA, NF, a->nf);
84
require_rvf(s) &&
69
- return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s, true);
85
- require_scale_rvf(s) &&
70
+ return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s);
86
- (s->sew != MO_8);
87
+ require_scale_rvf(s);
71
}
88
}
72
89
73
static bool st_index_check(DisasContext *s, arg_rnfvm* a, uint8_t eew)
90
GEN_OPFVV_WIDEN_TRANS(vfwredusum_vs, freduction_widen_check)
74
@@ -XXX,XX +XXX,XX @@ typedef void gen_helper_ldst_whole(TCGv_ptr, TCGv, TCGv_env, TCGv_i32);
75
76
static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf,
77
uint32_t width, gen_helper_ldst_whole *fn,
78
- DisasContext *s, bool is_store)
79
+ DisasContext *s)
80
{
81
uint32_t evl = s->cfg_ptr->vlenb * nf / width;
82
TCGLabel *over = gen_new_label();
83
@@ -XXX,XX +XXX,XX @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf,
84
* load and store whole register instructions ignore vtype and vl setting.
85
* Thus, we don't need to check vill bit. (Section 7.9)
86
*/
87
-#define GEN_LDST_WHOLE_TRANS(NAME, ARG_NF, WIDTH, IS_STORE) \
88
+#define GEN_LDST_WHOLE_TRANS(NAME, ARG_NF, WIDTH) \
89
static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \
90
{ \
91
if (require_rvv(s) && \
92
QEMU_IS_ALIGNED(a->rd, ARG_NF)) { \
93
return ldst_whole_trans(a->rd, a->rs1, ARG_NF, WIDTH, \
94
- gen_helper_##NAME, s, IS_STORE); \
95
+ gen_helper_##NAME, s); \
96
} \
97
return false; \
98
}
99
100
-GEN_LDST_WHOLE_TRANS(vl1re8_v, 1, 1, false)
101
-GEN_LDST_WHOLE_TRANS(vl1re16_v, 1, 2, false)
102
-GEN_LDST_WHOLE_TRANS(vl1re32_v, 1, 4, false)
103
-GEN_LDST_WHOLE_TRANS(vl1re64_v, 1, 8, false)
104
-GEN_LDST_WHOLE_TRANS(vl2re8_v, 2, 1, false)
105
-GEN_LDST_WHOLE_TRANS(vl2re16_v, 2, 2, false)
106
-GEN_LDST_WHOLE_TRANS(vl2re32_v, 2, 4, false)
107
-GEN_LDST_WHOLE_TRANS(vl2re64_v, 2, 8, false)
108
-GEN_LDST_WHOLE_TRANS(vl4re8_v, 4, 1, false)
109
-GEN_LDST_WHOLE_TRANS(vl4re16_v, 4, 2, false)
110
-GEN_LDST_WHOLE_TRANS(vl4re32_v, 4, 4, false)
111
-GEN_LDST_WHOLE_TRANS(vl4re64_v, 4, 8, false)
112
-GEN_LDST_WHOLE_TRANS(vl8re8_v, 8, 1, false)
113
-GEN_LDST_WHOLE_TRANS(vl8re16_v, 8, 2, false)
114
-GEN_LDST_WHOLE_TRANS(vl8re32_v, 8, 4, false)
115
-GEN_LDST_WHOLE_TRANS(vl8re64_v, 8, 8, false)
116
+GEN_LDST_WHOLE_TRANS(vl1re8_v, 1, 1)
117
+GEN_LDST_WHOLE_TRANS(vl1re16_v, 1, 2)
118
+GEN_LDST_WHOLE_TRANS(vl1re32_v, 1, 4)
119
+GEN_LDST_WHOLE_TRANS(vl1re64_v, 1, 8)
120
+GEN_LDST_WHOLE_TRANS(vl2re8_v, 2, 1)
121
+GEN_LDST_WHOLE_TRANS(vl2re16_v, 2, 2)
122
+GEN_LDST_WHOLE_TRANS(vl2re32_v, 2, 4)
123
+GEN_LDST_WHOLE_TRANS(vl2re64_v, 2, 8)
124
+GEN_LDST_WHOLE_TRANS(vl4re8_v, 4, 1)
125
+GEN_LDST_WHOLE_TRANS(vl4re16_v, 4, 2)
126
+GEN_LDST_WHOLE_TRANS(vl4re32_v, 4, 4)
127
+GEN_LDST_WHOLE_TRANS(vl4re64_v, 4, 8)
128
+GEN_LDST_WHOLE_TRANS(vl8re8_v, 8, 1)
129
+GEN_LDST_WHOLE_TRANS(vl8re16_v, 8, 2)
130
+GEN_LDST_WHOLE_TRANS(vl8re32_v, 8, 4)
131
+GEN_LDST_WHOLE_TRANS(vl8re64_v, 8, 8)
132
133
/*
134
* The vector whole register store instructions are encoded similar to
135
* unmasked unit-stride store of elements with EEW=8.
136
*/
137
-GEN_LDST_WHOLE_TRANS(vs1r_v, 1, 1, true)
138
-GEN_LDST_WHOLE_TRANS(vs2r_v, 2, 1, true)
139
-GEN_LDST_WHOLE_TRANS(vs4r_v, 4, 1, true)
140
-GEN_LDST_WHOLE_TRANS(vs8r_v, 8, 1, true)
141
+GEN_LDST_WHOLE_TRANS(vs1r_v, 1, 1)
142
+GEN_LDST_WHOLE_TRANS(vs2r_v, 2, 1)
143
+GEN_LDST_WHOLE_TRANS(vs4r_v, 4, 1)
144
+GEN_LDST_WHOLE_TRANS(vs8r_v, 8, 1)
145
146
/*
147
*** Vector Integer Arithmetic Instructions
148
--
91
--
149
2.44.0
92
2.45.1
150
151
diff view generated by jsdifflib
[PULL 07/34] target/riscv/tcg: set 'mmu' with 'satp' in cpu_set_profile()
[PULL 21/28] target/riscv: prioritize pmp errors in raise_mmu_exception()
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
2
2
3
Recent changes in options handling removed the 'mmu' default the bare
3
raise_mmu_exception(), as is today, is prioritizing guest page faults by
4
CPUs had, meaning that we must enable 'mmu' by hand when using the
4
checking first if virt_enabled && !first_stage, and then considering the
5
rva22s64 profile CPU.
5
regular inst/load/store faults.
6
6
7
Given that this profile is setting a satp mode, it already implies that
7
There's no mention in the spec about guest page fault being a higher
8
we need a 'mmu'. Enable the 'mmu' in this case.
8
priority that PMP faults. In fact, privileged spec section 3.7.1 says:
9
9
10
"Attempting to fetch an instruction from a PMP region that does not have
11
execute permissions raises an instruction access-fault exception.
12
Attempting to execute a load or load-reserved instruction which accesses
13
a physical address within a PMP region without read permissions raises a
14
load access-fault exception. Attempting to execute a store,
15
store-conditional, or AMO instruction which accesses a physical address
16
within a PMP region without write permissions raises a store
17
access-fault exception."
18
19
So, in fact, we're doing it wrong - PMP faults should always be thrown,
20
regardless of also being a first or second stage fault.
21
22
The way riscv_cpu_tlb_fill() and get_physical_address() work is
23
adequate: a TRANSLATE_PMP_FAIL error is immediately reported and
24
reflected in the 'pmp_violation' flag. What we need is to change
25
raise_mmu_exception() to prioritize it.
26
27
Reported-by: Joseph Chan <jchan@ventanamicro.com>
28
Fixes: 82d53adfbb ("target/riscv/cpu_helper.c: Invalid exception on MMU translation stage")
10
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
29
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
11
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
30
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
12
Message-ID: <20240215223955.969568-2-dbarboza@ventanamicro.com>
31
Message-ID: <20240413105929.7030-1-alexei.filippov@syntacore.com>
32
Cc: qemu-stable <qemu-stable@nongnu.org>
13
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
33
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
---
34
---
15
target/riscv/tcg/tcg-cpu.c | 1 +
35
target/riscv/cpu_helper.c | 22 ++++++++++++----------
16
1 file changed, 1 insertion(+)
36
1 file changed, 12 insertions(+), 10 deletions(-)
17
37
18
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
38
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
19
index XXXXXXX..XXXXXXX 100644
39
index XXXXXXX..XXXXXXX 100644
20
--- a/target/riscv/tcg/tcg-cpu.c
40
--- a/target/riscv/cpu_helper.c
21
+++ b/target/riscv/tcg/tcg-cpu.c
41
+++ b/target/riscv/cpu_helper.c
22
@@ -XXX,XX +XXX,XX @@ static void cpu_set_profile(Object *obj, Visitor *v, const char *name,
42
@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
23
43
24
#ifndef CONFIG_USER_ONLY
44
switch (access_type) {
25
if (profile->satp_mode != RISCV_PROFILE_ATTR_UNUSED) {
45
case MMU_INST_FETCH:
26
+ object_property_set_bool(obj, "mmu", true, NULL);
46
- if (env->virt_enabled && !first_stage) {
27
const char *satp_prop = satp_mode_str(profile->satp_mode,
47
+ if (pmp_violation) {
28
riscv_cpu_is_32bit(cpu));
48
+ cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT;
29
object_property_set_bool(obj, satp_prop, profile->enabled, NULL);
49
+ } else if (env->virt_enabled && !first_stage) {
50
cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT;
51
} else {
52
- cs->exception_index = pmp_violation ?
53
- RISCV_EXCP_INST_ACCESS_FAULT : RISCV_EXCP_INST_PAGE_FAULT;
54
+ cs->exception_index = RISCV_EXCP_INST_PAGE_FAULT;
55
}
56
break;
57
case MMU_DATA_LOAD:
58
- if (two_stage && !first_stage) {
59
+ if (pmp_violation) {
60
+ cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT;
61
+ } else if (two_stage && !first_stage) {
62
cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT;
63
} else {
64
- cs->exception_index = pmp_violation ?
65
- RISCV_EXCP_LOAD_ACCESS_FAULT : RISCV_EXCP_LOAD_PAGE_FAULT;
66
+ cs->exception_index = RISCV_EXCP_LOAD_PAGE_FAULT;
67
}
68
break;
69
case MMU_DATA_STORE:
70
- if (two_stage && !first_stage) {
71
+ if (pmp_violation) {
72
+ cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
73
+ } else if (two_stage && !first_stage) {
74
cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT;
75
} else {
76
- cs->exception_index = pmp_violation ?
77
- RISCV_EXCP_STORE_AMO_ACCESS_FAULT :
78
- RISCV_EXCP_STORE_PAGE_FAULT;
79
+ cs->exception_index = RISCV_EXCP_STORE_PAGE_FAULT;
80
}
81
break;
82
default:
30
--
83
--
31
2.44.0
84
2.45.1
diff view generated by jsdifflib
[PULL 33/34] target/riscv: Fix privilege mode of G-stage translation for debugging
[PULL 22/28] target/riscv: do not set mtval2 for non guest-page faults
1
From: Hiroaki Yamamoto <hrak1529@gmail.com>
1
From: Alexei Filippov <alexei.filippov@syntacore.com>
2
2
3
G-stage translation should be considered to be user-level access in
3
Previous patch fixed the PMP priority in raise_mmu_exception() but we're still
4
riscv_cpu_get_phys_page_debug(), as already done in riscv_cpu_tlb_fill().
4
setting mtval2 incorrectly. In riscv_cpu_tlb_fill(), after pmp check in 2 stage
5
translation part, mtval2 will be set in case of successes 2 stage translation but
6
failed pmp check.
5
7
6
This fixes a bug that prevents gdb from reading memory while the VM is
8
In this case we gonna set mtval2 via env->guest_phys_fault_addr in context of
7
running in VS-mode.
9
riscv_cpu_tlb_fill(), as this was a guest-page-fault, but it didn't and mtval2
10
should be zero, according to RISCV privileged spec sect. 9.4.4: When a guest
11
page-fault is taken into M-mode, mtval2 is written with either zero or guest
12
physical address that faulted, shifted by 2 bits. *For other traps, mtval2
13
is set to zero...*
8
14
9
Signed-off-by: Hiroaki Yamamoto <hrak1529@gmail.com>
15
Signed-off-by: Alexei Filippov <alexei.filippov@syntacore.com>
16
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
10
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
17
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
11
Message-ID: <20240228081028.35081-1-hrak1529@gmail.com>
18
Message-ID: <20240503103052.6819-1-alexei.filippov@syntacore.com>
19
Cc: qemu-stable <qemu-stable@nongnu.org>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
20
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
---
21
---
14
target/riscv/cpu_helper.c | 2 +-
22
target/riscv/cpu_helper.c | 12 ++++++------
15
1 file changed, 1 insertion(+), 1 deletion(-)
23
1 file changed, 6 insertions(+), 6 deletions(-)
16
24
17
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
25
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
18
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100644
19
--- a/target/riscv/cpu_helper.c
27
--- a/target/riscv/cpu_helper.c
20
+++ b/target/riscv/cpu_helper.c
28
+++ b/target/riscv/cpu_helper.c
21
@@ -XXX,XX +XXX,XX @@ hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
29
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
22
30
__func__, pa, ret, prot_pmp, tlb_size);
23
if (env->virt_enabled) {
31
24
if (get_physical_address(env, &phys_addr, &prot, phys_addr, NULL,
32
prot &= prot_pmp;
25
- 0, mmu_idx, false, true, true)) {
33
- }
26
+ 0, MMUIdx_U, false, true, true)) {
34
-
27
return -1;
35
- if (ret != TRANSLATE_SUCCESS) {
36
+ } else {
37
/*
38
* Guest physical address translation failed, this is a HS
39
* level exception
40
*/
41
first_stage_error = false;
42
- env->guest_phys_fault_addr = (im_address |
43
- (address &
44
- (TARGET_PAGE_SIZE - 1))) >> 2;
45
+ if (ret != TRANSLATE_PMP_FAIL) {
46
+ env->guest_phys_fault_addr = (im_address |
47
+ (address &
48
+ (TARGET_PAGE_SIZE - 1))) >> 2;
49
+ }
50
}
28
}
51
}
29
}
52
} else {
30
--
53
--
31
2.44.0
54
2.45.1
diff view generated by jsdifflib
[PULL 12/34] target/riscv: Promote svade to a normal extension
[PULL 23/28] target/riscv: Remove experimental prefix from "B" extension
1
From: Andrew Jones <ajones@ventanamicro.com>
1
From: Rob Bradford <rbradford@rivosinc.com>
2
2
3
Named features are extensions which don't make sense for users to
3
This extension has now been ratified:
4
control and are therefore not exposed on the command line. However,
4
https://jira.riscv.org/browse/RVS-2006 so the "x-" prefix can be
5
svade is an extension which makes sense for users to control, so treat
5
removed.
6
it like a "normal" extension. The default is false, even for the max
7
cpu type, since QEMU has always implemented hardware A/D PTE bit
8
updating, so users must opt into svade (or get it from a CPU type
9
which enables it by default).
10
6
7
Since this is now a ratified extension add it to the list of extensions
8
included in the "max" CPU variant.
9
10
Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
11
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
12
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
11
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
13
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
12
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
14
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
13
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
15
Message-ID: <20240514110217.22516-1-rbradford@rivosinc.com>
14
Message-ID: <20240215223955.969568-7-dbarboza@ventanamicro.com>
15
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
16
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
16
---
17
---
17
target/riscv/cpu.c | 9 ++-------
18
target/riscv/cpu.c | 2 +-
18
target/riscv/tcg/tcg-cpu.c | 6 ++++++
19
target/riscv/tcg/tcg-cpu.c | 2 +-
19
2 files changed, 8 insertions(+), 7 deletions(-)
20
2 files changed, 2 insertions(+), 2 deletions(-)
20
21
21
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
22
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
22
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
23
--- a/target/riscv/cpu.c
24
--- a/target/riscv/cpu.c
24
+++ b/target/riscv/cpu.c
25
+++ b/target/riscv/cpu.c
25
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
26
@@ -XXX,XX +XXX,XX @@ static const MISAExtInfo misa_ext_info_arr[] = {
26
27
MISA_EXT_INFO(RVJ, "x-j", "Dynamic translated languages"),
27
MULTI_EXT_CFG_BOOL("smepmp", ext_smepmp, false),
28
MISA_EXT_INFO(RVV, "v", "Vector operations"),
28
MULTI_EXT_CFG_BOOL("smstateen", ext_smstateen, false),
29
MISA_EXT_INFO(RVG, "g", "General purpose (IMAFD_Zicsr_Zifencei)"),
29
+ MULTI_EXT_CFG_BOOL("svade", ext_svade, false),
30
- MISA_EXT_INFO(RVB, "x-b", "Bit manipulation (Zba_Zbb_Zbs)")
30
MULTI_EXT_CFG_BOOL("svadu", ext_svadu, true),
31
+ MISA_EXT_INFO(RVB, "b", "Bit manipulation (Zba_Zbb_Zbs)")
31
MULTI_EXT_CFG_BOOL("svinval", ext_svinval, false),
32
};
32
MULTI_EXT_CFG_BOOL("svnapot", ext_svnapot, false),
33
33
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
34
static void riscv_cpu_validate_misa_mxl(RISCVCPUClass *mcc)
34
* and priv_ver like regular extensions.
35
*/
36
const RISCVCPUMultiExtConfig riscv_cpu_named_features[] = {
37
- MULTI_EXT_CFG_BOOL("svade", ext_svade, true),
38
MULTI_EXT_CFG_BOOL("zic64b", ext_zic64b, true),
39
40
/*
41
@@ -XXX,XX +XXX,XX @@ static RISCVCPUProfile RVA22U64 = {
42
* Other named features that we already implement: Sstvecd, Sstvala,
43
* Sscounterenw
44
*
45
- * Named features that we need to enable: svade
46
- *
47
* The remaining features/extensions comes from RVA22U64.
48
*/
49
static RISCVCPUProfile RVA22S64 = {
50
@@ -XXX,XX +XXX,XX @@ static RISCVCPUProfile RVA22S64 = {
51
.ext_offsets = {
52
/* rva22s64 exts */
53
CPU_CFG_OFFSET(ext_zifencei), CPU_CFG_OFFSET(ext_svpbmt),
54
- CPU_CFG_OFFSET(ext_svinval),
55
-
56
- /* rva22s64 named features */
57
- CPU_CFG_OFFSET(ext_svade),
58
+ CPU_CFG_OFFSET(ext_svinval), CPU_CFG_OFFSET(ext_svade),
59
60
RISCV_PROFILE_EXT_LIST_END
61
}
62
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
35
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
63
index XXXXXXX..XXXXXXX 100644
36
index XXXXXXX..XXXXXXX 100644
64
--- a/target/riscv/tcg/tcg-cpu.c
37
--- a/target/riscv/tcg/tcg-cpu.c
65
+++ b/target/riscv/tcg/tcg-cpu.c
38
+++ b/target/riscv/tcg/tcg-cpu.c
66
@@ -XXX,XX +XXX,XX @@ static void riscv_init_max_cpu_extensions(Object *obj)
39
@@ -XXX,XX +XXX,XX @@ static void riscv_init_max_cpu_extensions(Object *obj)
40
const RISCVCPUMultiExtConfig *prop;
41
42
/* Enable RVG, RVJ and RVV that are disabled by default */
43
- riscv_cpu_set_misa_ext(env, env->misa_ext | RVG | RVJ | RVV);
44
+ riscv_cpu_set_misa_ext(env, env->misa_ext | RVB | RVG | RVJ | RVV);
45
46
for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
67
isa_ext_update_enabled(cpu, prop->offset, true);
47
isa_ext_update_enabled(cpu, prop->offset, true);
68
}
69
70
+ /*
71
+ * Some extensions can't be added without backward compatibilty concerns.
72
+ * Disable those, the user can still opt in to them on the command line.
73
+ */
74
+ cpu->cfg.ext_svade = false;
75
+
76
/* set vector version */
77
env->vext_ver = VEXT_VERSION_1_00_0;
78
79
--
48
--
80
2.44.0
49
2.45.1
diff view generated by jsdifflib
[PULL 13/34] target/riscv: FIX xATP_MODE validation
Deleted patch
1
From: Irina Ryapolova <irina.ryapolova@syntacore.com>
2
1
3
The SATP register is an SXLEN-bit read/write WARL register. It means that CSR fields are only defined
4
for a subset of bit encodings, but allow any value to be written while guaranteeing to return a legal
5
value whenever read (See riscv-privileged-20211203, SATP CSR).
6
7
For example on rv64 we are trying to write to SATP CSR val = 0x1000000000000000 (SATP_MODE = 1 - Reserved for standard use)
8
and after that we are trying to read SATP_CSR. We read from the SATP CSR value = 0x1000000000000000, which is not a correct
9
operation (return illegal value).
10
11
Signed-off-by: Irina Ryapolova <irina.ryapolova@syntacore.com>
12
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
13
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
14
Message-ID: <20240109145923.37893-1-irina.ryapolova@syntacore.com>
15
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
16
---
17
target/riscv/csr.c | 4 ++--
18
1 file changed, 2 insertions(+), 2 deletions(-)
19
20
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/target/riscv/csr.c
23
+++ b/target/riscv/csr.c
24
@@ -XXX,XX +XXX,XX @@ static RISCVException read_mstatus(CPURISCVState *env, int csrno,
25
26
static bool validate_vm(CPURISCVState *env, target_ulong vm)
27
{
28
- return (vm & 0xf) <=
29
- satp_mode_max_from_map(riscv_cpu_cfg(env)->satp_mode.map);
30
+ uint64_t mode_supported = riscv_cpu_cfg(env)->satp_mode.map;
31
+ return get_field(mode_supported, (1 << vm));
32
}
33
34
static target_ulong legalize_mpp(CPURISCVState *env, target_ulong old_mpp,
35
--
36
2.44.0
diff view generated by jsdifflib
[PULL 18/34] hw/riscv/virt.c: add virtio-iommu-pci hotplug support
[PULL 24/28] target/riscv: rvzicbo: Fixup CBO extension register calculation
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
1
From: Alistair Francis <alistair23@gmail.com>
2
2
3
We want to add a RISC-V 'virt' libqos machine to increase our test
3
When running the instruction
4
coverage. Some of the tests will try to plug a virtio-iommu-pci
5
device into the board and do some tests with it.
6
4
7
Enable virtio-iommu-pci in the 'virt' machine.
5
```
6
cbo.flush 0(x0)
7
```
8
8
9
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
9
QEMU would segfault.
10
Acked-by: Alistair Francis <alistair.francis@wdc.com>
10
11
Message-ID: <20240217192607.32565-5-dbarboza@ventanamicro.com>
11
The issue was in cpu_gpr[a->rs1] as QEMU does not have cpu_gpr[0]
12
allocated.
13
14
In order to fix this let's use the existing get_address()
15
helper. This also has the benefit of performing pointer mask
16
calculations on the address specified in rs1.
17
18
The pointer masking specificiation specifically states:
19
20
"""
21
Cache Management Operations: All instructions in Zicbom, Zicbop and Zicboz
22
"""
23
24
So this is the correct behaviour and we previously have been incorrectly
25
not masking the address.
26
27
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
28
Reported-by: Fabian Thomas <fabian.thomas@cispa.de>
29
Fixes: e05da09b7cfd ("target/riscv: implement Zicbom extension")
30
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
31
Cc: qemu-stable <qemu-stable@nongnu.org>
32
Message-ID: <20240514023910.301766-1-alistair.francis@wdc.com>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
33
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
---
34
---
14
hw/riscv/virt.c | 36 +++++++++++++++++++++++++++++++++++-
35
target/riscv/insn_trans/trans_rvzicbo.c.inc | 16 ++++++++++++----
15
1 file changed, 35 insertions(+), 1 deletion(-)
36
1 file changed, 12 insertions(+), 4 deletions(-)
16
37
17
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
38
diff --git a/target/riscv/insn_trans/trans_rvzicbo.c.inc b/target/riscv/insn_trans/trans_rvzicbo.c.inc
18
index XXXXXXX..XXXXXXX 100644
39
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/riscv/virt.c
40
--- a/target/riscv/insn_trans/trans_rvzicbo.c.inc
20
+++ b/hw/riscv/virt.c
41
+++ b/target/riscv/insn_trans/trans_rvzicbo.c.inc
21
@@ -XXX,XX +XXX,XX @@
42
@@ -XXX,XX +XXX,XX @@
22
#include "hw/display/ramfb.h"
43
static bool trans_cbo_clean(DisasContext *ctx, arg_cbo_clean *a)
23
#include "hw/acpi/aml-build.h"
44
{
24
#include "qapi/qapi-visit-common.h"
45
REQUIRE_ZICBOM(ctx);
25
+#include "hw/virtio/virtio-iommu.h"
46
- gen_helper_cbo_clean_flush(tcg_env, cpu_gpr[a->rs1]);
26
47
+ TCGv src = get_address(ctx, a->rs1, 0);
27
/* KVM AIA only supports APLIC MSI. APLIC Wired is always emulated by QEMU. */
48
+
28
static bool virt_use_kvm_aia(RISCVVirtState *s)
49
+ gen_helper_cbo_clean_flush(tcg_env, src);
29
@@ -XXX,XX +XXX,XX @@ static void create_fdt_fw_cfg(RISCVVirtState *s, const MemMapEntry *memmap)
50
return true;
30
qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
31
}
51
}
32
52
33
+static void create_fdt_virtio_iommu(RISCVVirtState *s, uint16_t bdf)
53
static bool trans_cbo_flush(DisasContext *ctx, arg_cbo_flush *a)
34
+{
54
{
35
+ const char compat[] = "virtio,pci-iommu\0pci1af4,1057";
55
REQUIRE_ZICBOM(ctx);
36
+ void *fdt = MACHINE(s)->fdt;
56
- gen_helper_cbo_clean_flush(tcg_env, cpu_gpr[a->rs1]);
37
+ uint32_t iommu_phandle;
57
+ TCGv src = get_address(ctx, a->rs1, 0);
38
+ g_autofree char *iommu_node = NULL;
39
+ g_autofree char *pci_node = NULL;
40
+
58
+
41
+ pci_node = g_strdup_printf("/soc/pci@%lx",
59
+ gen_helper_cbo_clean_flush(tcg_env, src);
42
+ (long) virt_memmap[VIRT_PCIE_ECAM].base);
60
return true;
43
+ iommu_node = g_strdup_printf("%s/virtio_iommu@%x,%x", pci_node,
61
}
44
+ PCI_SLOT(bdf), PCI_FUNC(bdf));
62
45
+ iommu_phandle = qemu_fdt_alloc_phandle(fdt);
63
static bool trans_cbo_inval(DisasContext *ctx, arg_cbo_inval *a)
64
{
65
REQUIRE_ZICBOM(ctx);
66
- gen_helper_cbo_inval(tcg_env, cpu_gpr[a->rs1]);
67
+ TCGv src = get_address(ctx, a->rs1, 0);
46
+
68
+
47
+ qemu_fdt_add_subnode(fdt, iommu_node);
69
+ gen_helper_cbo_inval(tcg_env, src);
70
return true;
71
}
72
73
static bool trans_cbo_zero(DisasContext *ctx, arg_cbo_zero *a)
74
{
75
REQUIRE_ZICBOZ(ctx);
76
- gen_helper_cbo_zero(tcg_env, cpu_gpr[a->rs1]);
77
+ TCGv src = get_address(ctx, a->rs1, 0);
48
+
78
+
49
+ qemu_fdt_setprop(fdt, iommu_node, "compatible", compat, sizeof(compat));
79
+ gen_helper_cbo_zero(tcg_env, src);
50
+ qemu_fdt_setprop_sized_cells(fdt, iommu_node, "reg",
80
return true;
51
+ 1, bdf << 8, 1, 0, 1, 0,
52
+ 1, 0, 1, 0);
53
+ qemu_fdt_setprop_cell(fdt, iommu_node, "#iommu-cells", 1);
54
+ qemu_fdt_setprop_cell(fdt, iommu_node, "phandle", iommu_phandle);
55
+
56
+ qemu_fdt_setprop_cells(fdt, pci_node, "iommu-map",
57
+ 0, iommu_phandle, 0, bdf,
58
+ bdf + 1, iommu_phandle, bdf + 1, 0xffff - bdf);
59
+}
60
+
61
static void finalize_fdt(RISCVVirtState *s)
62
{
63
uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1;
64
@@ -XXX,XX +XXX,XX @@ static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine,
65
{
66
MachineClass *mc = MACHINE_GET_CLASS(machine);
67
68
- if (device_is_dynamic_sysbus(mc, dev)) {
69
+ if (device_is_dynamic_sysbus(mc, dev) ||
70
+ object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
71
return HOTPLUG_HANDLER(machine);
72
}
73
return NULL;
74
@@ -XXX,XX +XXX,XX @@ static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev,
75
SYS_BUS_DEVICE(dev));
76
}
77
}
78
+
79
+ if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
80
+ create_fdt_virtio_iommu(s, pci_get_bdf(PCI_DEVICE(dev)));
81
+ }
82
}
81
}
83
84
static void virt_machine_class_init(ObjectClass *oc, void *data)
85
--
82
--
86
2.44.0
83
2.45.1
diff view generated by jsdifflib
[PULL 30/34] target/riscv: Fix shift count overflow
[PULL 25/28] target/riscv/kvm.c: Fix the hart bit setting of AIA
1
From: "demin.han" <demin.han@starfivetech.com>
1
From: Yong-Xuan Wang <yongxuan.wang@sifive.com>
2
2
3
The result of (8 - 3 - vlmul) is negative when vlmul >= 6,
3
In AIA spec, each hart (or each hart within a group) has a unique hart
4
and results in wrong vill.
4
number to locate the memory pages of interrupt files in the address
5
space. The number of bits required to represent any hart number is equal
6
to ceil(log2(hmax + 1)), where hmax is the largest hart number among
7
groups.
5
8
6
Signed-off-by: demin.han <demin.han@starfivetech.com>
9
However, if the largest hart number among groups is a power of 2, QEMU
7
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
10
will pass an inaccurate hart-index-bit setting to Linux. For example, when
8
Message-ID: <20240225174114.5298-1-demin.han@starfivetech.com>
11
the guest OS has 4 harts, only ceil(log2(3 + 1)) = 2 bits are sufficient
12
to represent 4 harts, but we passes 3 to Linux. The code needs to be
13
updated to ensure accurate hart-index-bit settings.
14
15
Additionally, a Linux patch[1] is necessary to correctly recover the hart
16
index when the guest OS has only 1 hart, where the hart-index-bit is 0.
17
18
[1] https://lore.kernel.org/lkml/20240415064905.25184-1-yongxuan.wang@sifive.com/t/
19
20
Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
21
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
22
Cc: qemu-stable <qemu-stable@nongnu.org>
23
Message-ID: <20240515091129.28116-1-yongxuan.wang@sifive.com>
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
24
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
---
25
---
11
target/riscv/vector_helper.c | 5 ++---
26
target/riscv/kvm/kvm-cpu.c | 9 ++++++++-
12
1 file changed, 2 insertions(+), 3 deletions(-)
27
1 file changed, 8 insertions(+), 1 deletion(-)
13
28
14
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
29
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
15
index XXXXXXX..XXXXXXX 100644
30
index XXXXXXX..XXXXXXX 100644
16
--- a/target/riscv/vector_helper.c
31
--- a/target/riscv/kvm/kvm-cpu.c
17
+++ b/target/riscv/vector_helper.c
32
+++ b/target/riscv/kvm/kvm-cpu.c
18
@@ -XXX,XX +XXX,XX @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
33
@@ -XXX,XX +XXX,XX @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
19
target_ulong reserved = s2 &
20
MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT,
21
xlen - 1 - R_VTYPE_RESERVED_SHIFT);
22
+ uint16_t vlen = cpu->cfg.vlenb << 3;
23
int8_t lmul;
24
25
if (vlmul & 4) {
26
@@ -XXX,XX +XXX,XX @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
27
* VLEN * LMUL >= SEW
28
* VLEN >> (8 - lmul) >= sew
29
* (vlenb << 3) >> (8 - lmul) >= sew
30
- * vlenb >> (8 - 3 - lmul) >= sew
31
*/
32
- if (vlmul == 4 ||
33
- cpu->cfg.vlenb >> (8 - 3 - vlmul) < sew) {
34
+ if (vlmul == 4 || (vlen >> (8 - vlmul)) < sew) {
35
vill = true;
36
}
34
}
37
}
35
}
36
37
- hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1;
38
+
39
+ if (max_hart_per_socket > 1) {
40
+ max_hart_per_socket--;
41
+ hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1;
42
+ } else {
43
+ hart_bits = 0;
44
+ }
45
+
46
ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
47
KVM_DEV_RISCV_AIA_CONFIG_HART_BITS,
48
&hart_bits, true, NULL);
38
--
49
--
39
2.44.0
50
2.45.1
diff view generated by jsdifflib
[PULL 19/34] hw/riscv/virt.c: make aclint compatible with 'qtest' accel
[PULL 26/28] riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature()
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
2
2
3
The 'virt' machine makes assumptions on the Advanced Core-Local
3
Commit 33a24910ae changed 'reg_width' to use 'vlenb', i.e. vector length
4
Interruptor, or aclint, based on 'tcg_enabled()' conditionals. This
4
in bytes, when in this context we want 'reg_width' as the length in
5
will impact MSI related tests support when adding a RISC-V 'virt' libqos
5
bits.
6
machine. The accelerator used in that case, 'qtest', isn't being
7
accounted for and we'll error out if we try to enable aclint.
8
6
9
Create a new virt_aclint_allowed() helper to gate the aclint code
7
Fix 'reg_width' back to the value in bits like 7cb59921c05a
10
considering both TCG and 'qtest' accelerators. The error message is
8
("target/riscv/gdbstub.c: use 'vlenb' instead of shifting 'vlen'") set
11
left untouched, mentioning TCG only, because we don't expect the
9
beforehand.
12
regular user to be aware of 'qtest'.
13
10
14
We want to add 'qtest' support for aclint only, leaving the TCG specific
11
While we're at it, rename 'reg_width' to 'bitsize' to provide a bit more
15
bits out of it. This is done by changing the current format we use
12
clarity about what the variable represents. 'bitsize' is also used in
16
today:
13
riscv_gen_dynamic_csr_feature() with the same purpose, i.e. as an input to
14
gdb_feature_builder_append_reg().
17
15
18
if (tcg_enabled()) {
16
Cc: Akihiko Odaki <akihiko.odaki@daynix.com>
19
if (s->have_aclint) { - aclint logic - }
17
Cc: Alex Bennée <alex.bennee@linaro.org>
20
else { - non-aclint, TCG logic - }
18
Reported-by: Robin Dapp <rdapp.gcc@gmail.com>
21
}
19
Fixes: 33a24910ae ("target/riscv: Use GDBFeature for dynamic XML")
22
23
into:
24
25
if (virt_aclint_allowed() && s->have_aclint) {
26
- aclint logic -
27
} else if (tcg_enabled()) {
28
- non-aclint, TCG logic -
29
}
30
31
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
20
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
21
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
22
Acked-by: Alex Bennée <alex.bennee@linaro.org>
23
Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com>
32
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
24
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
33
Message-ID: <20240217192607.32565-6-dbarboza@ventanamicro.com>
25
Cc: qemu-stable <qemu-stable@nongnu.org>
26
Message-ID: <20240517203054.880861-2-dbarboza@ventanamicro.com>
34
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
27
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
35
---
28
---
36
hw/riscv/virt.c | 52 +++++++++++++++++++++++++------------------------
29
target/riscv/gdbstub.c | 6 +++---
37
1 file changed, 27 insertions(+), 25 deletions(-)
30
1 file changed, 3 insertions(+), 3 deletions(-)
38
31
39
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
32
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
40
index XXXXXXX..XXXXXXX 100644
33
index XXXXXXX..XXXXXXX 100644
41
--- a/hw/riscv/virt.c
34
--- a/target/riscv/gdbstub.c
42
+++ b/hw/riscv/virt.c
35
+++ b/target/riscv/gdbstub.c
43
@@ -XXX,XX +XXX,XX @@
36
@@ -XXX,XX +XXX,XX @@ static GDBFeature *riscv_gen_dynamic_csr_feature(CPUState *cs, int base_reg)
44
#include "sysemu/tcg.h"
37
static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
45
#include "sysemu/kvm.h"
38
{
46
#include "sysemu/tpm.h"
39
RISCVCPU *cpu = RISCV_CPU(cs);
47
+#include "sysemu/qtest.h"
40
- int reg_width = cpu->cfg.vlenb;
48
#include "hw/pci/pci.h"
41
+ int bitsize = cpu->cfg.vlenb << 3;
49
#include "hw/pci-host/gpex.h"
42
GDBFeatureBuilder builder;
50
#include "hw/display/ramfb.h"
43
int i;
51
@@ -XXX,XX +XXX,XX @@ static bool virt_use_kvm_aia(RISCVVirtState *s)
44
52
return kvm_irqchip_in_kernel() && s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC;
45
@@ -XXX,XX +XXX,XX @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
53
}
46
54
47
/* First define types and totals in a whole VL */
55
+static bool virt_aclint_allowed(void)
48
for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
56
+{
49
- int count = reg_width / vec_lanes[i].size;
57
+ return tcg_enabled() || qtest_enabled();
50
+ int count = bitsize / vec_lanes[i].size;
58
+}
51
gdb_feature_builder_append_tag(
59
+
52
&builder, "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
60
static const MemMapEntry virt_memmap[] = {
53
vec_lanes[i].id, vec_lanes[i].gdb_type, count);
61
[VIRT_DEBUG] = { 0x0, 0x100 },
54
@@ -XXX,XX +XXX,XX @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
62
[VIRT_MROM] = { 0x1000, 0xf000 },
55
/* Define vector registers */
63
@@ -XXX,XX +XXX,XX @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
56
for (i = 0; i < 32; i++) {
64
57
gdb_feature_builder_append_reg(&builder, g_strdup_printf("v%d", i),
65
create_fdt_socket_memory(s, memmap, socket);
58
- reg_width, i, "riscv_vector", "vector");
66
59
+ bitsize, i, "riscv_vector", "vector");
67
- if (tcg_enabled()) {
68
- if (s->have_aclint) {
69
- create_fdt_socket_aclint(s, memmap, socket,
70
- &intc_phandles[phandle_pos]);
71
- } else {
72
- create_fdt_socket_clint(s, memmap, socket,
73
- &intc_phandles[phandle_pos]);
74
- }
75
+ if (virt_aclint_allowed() && s->have_aclint) {
76
+ create_fdt_socket_aclint(s, memmap, socket,
77
+ &intc_phandles[phandle_pos]);
78
+ } else if (tcg_enabled()) {
79
+ create_fdt_socket_clint(s, memmap, socket,
80
+ &intc_phandles[phandle_pos]);
81
}
82
}
60
}
83
61
84
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
62
gdb_feature_builder_end(&builder);
85
exit(1);
86
}
87
88
- if (!tcg_enabled() && s->have_aclint) {
89
+ if (!virt_aclint_allowed() && s->have_aclint) {
90
error_report("'aclint' is only available with TCG acceleration");
91
exit(1);
92
}
93
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
94
hart_count, &error_abort);
95
sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_fatal);
96
97
- if (tcg_enabled()) {
98
- if (s->have_aclint) {
99
- if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
100
- /* Per-socket ACLINT MTIMER */
101
- riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base +
102
+ if (virt_aclint_allowed() && s->have_aclint) {
103
+ if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
104
+ /* Per-socket ACLINT MTIMER */
105
+ riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base +
106
i * RISCV_ACLINT_DEFAULT_MTIMER_SIZE,
107
RISCV_ACLINT_DEFAULT_MTIMER_SIZE,
108
base_hartid, hart_count,
109
RISCV_ACLINT_DEFAULT_MTIMECMP,
110
RISCV_ACLINT_DEFAULT_MTIME,
111
RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true);
112
- } else {
113
- /* Per-socket ACLINT MSWI, MTIMER, and SSWI */
114
- riscv_aclint_swi_create(memmap[VIRT_CLINT].base +
115
+ } else {
116
+ /* Per-socket ACLINT MSWI, MTIMER, and SSWI */
117
+ riscv_aclint_swi_create(memmap[VIRT_CLINT].base +
118
i * memmap[VIRT_CLINT].size,
119
base_hartid, hart_count, false);
120
- riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base +
121
+ riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base +
122
i * memmap[VIRT_CLINT].size +
123
RISCV_ACLINT_SWI_SIZE,
124
RISCV_ACLINT_DEFAULT_MTIMER_SIZE,
125
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
126
RISCV_ACLINT_DEFAULT_MTIMECMP,
127
RISCV_ACLINT_DEFAULT_MTIME,
128
RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true);
129
- riscv_aclint_swi_create(memmap[VIRT_ACLINT_SSWI].base +
130
+ riscv_aclint_swi_create(memmap[VIRT_ACLINT_SSWI].base +
131
i * memmap[VIRT_ACLINT_SSWI].size,
132
base_hartid, hart_count, true);
133
- }
134
- } else {
135
- /* Per-socket SiFive CLINT */
136
- riscv_aclint_swi_create(
137
+ }
138
+ } else if (tcg_enabled()) {
139
+ /* Per-socket SiFive CLINT */
140
+ riscv_aclint_swi_create(
141
memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size,
142
base_hartid, hart_count, false);
143
- riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base +
144
+ riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base +
145
i * memmap[VIRT_CLINT].size + RISCV_ACLINT_SWI_SIZE,
146
RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count,
147
RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME,
148
RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true);
149
- }
150
}
151
152
/* Per-socket interrupt controller */
153
--
63
--
154
2.44.0
64
2.45.1
65
66
diff view generated by jsdifflib
[PULL 27/34] target/riscv: mcountinhibit, mcounteren, scounteren, hcounteren is 32-bit
[PULL 27/28] disas/riscv: Decode all of the pmpcfg and pmpaddr CSRs
1
From: Vadim Shakirov <vadim.shakirov@syntacore.com>
1
From: Alistair Francis <alistair23@gmail.com>
2
2
3
mcountinhibit, mcounteren, scounteren and hcounteren must always be 32-bit
3
Previously we only listed a single pmpcfg CSR and the first 16 pmpaddr
4
by privileged spec
4
CSRs. This patch fixes this to list all 16 pmpcfg and all 64 pmpaddr
5
CSRs are part of the disassembly.
5
6
6
Signed-off-by: Vadim Shakirov <vadim.shakirov@syntacore.com>
7
Reported-by: Eric DeVolder <eric_devolder@yahoo.com>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
8
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
9
Fixes: ea10325917 ("RISC-V Disassembler")
9
Message-ID: <20240202113919.18236-1-vadim.shakirov@syntacore.com>
10
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
11
Cc: qemu-stable <qemu-stable@nongnu.org>
12
Message-ID: <20240514051615.330979-1-alistair.francis@wdc.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
14
---
12
target/riscv/cpu.h | 8 ++++----
15
disas/riscv.c | 65 ++++++++++++++++++++++++++++++++++++++++++++++++++-
13
target/riscv/machine.c | 16 ++++++++--------
16
1 file changed, 64 insertions(+), 1 deletion(-)
14
2 files changed, 12 insertions(+), 12 deletions(-)
15
17
16
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
18
diff --git a/disas/riscv.c b/disas/riscv.c
17
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
18
--- a/target/riscv/cpu.h
20
--- a/disas/riscv.c
19
+++ b/target/riscv/cpu.h
21
+++ b/disas/riscv.c
20
@@ -XXX,XX +XXX,XX @@ struct CPUArchState {
22
@@ -XXX,XX +XXX,XX @@ static const char *csr_name(int csrno)
21
target_ulong hstatus;
23
case 0x0383: return "mibound";
22
target_ulong hedeleg;
24
case 0x0384: return "mdbase";
23
uint64_t hideleg;
25
case 0x0385: return "mdbound";
24
- target_ulong hcounteren;
26
- case 0x03a0: return "pmpcfg3";
25
+ uint32_t hcounteren;
27
+ case 0x03a0: return "pmpcfg0";
26
target_ulong htval;
28
+ case 0x03a1: return "pmpcfg1";
27
target_ulong htinst;
29
+ case 0x03a2: return "pmpcfg2";
28
target_ulong hgatp;
30
+ case 0x03a3: return "pmpcfg3";
29
@@ -XXX,XX +XXX,XX @@ struct CPUArchState {
31
+ case 0x03a4: return "pmpcfg4";
30
*/
32
+ case 0x03a5: return "pmpcfg5";
31
bool two_stage_indirect_lookup;
33
+ case 0x03a6: return "pmpcfg6";
32
34
+ case 0x03a7: return "pmpcfg7";
33
- target_ulong scounteren;
35
+ case 0x03a8: return "pmpcfg8";
34
- target_ulong mcounteren;
36
+ case 0x03a9: return "pmpcfg9";
35
+ uint32_t scounteren;
37
+ case 0x03aa: return "pmpcfg10";
36
+ uint32_t mcounteren;
38
+ case 0x03ab: return "pmpcfg11";
37
39
+ case 0x03ac: return "pmpcfg12";
38
- target_ulong mcountinhibit;
40
+ case 0x03ad: return "pmpcfg13";
39
+ uint32_t mcountinhibit;
41
+ case 0x03ae: return "pmpcfg14";
40
42
+ case 0x03af: return "pmpcfg15";
41
/* PMU counter state */
43
case 0x03b0: return "pmpaddr0";
42
PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS];
44
case 0x03b1: return "pmpaddr1";
43
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
45
case 0x03b2: return "pmpaddr2";
44
index XXXXXXX..XXXXXXX 100644
46
@@ -XXX,XX +XXX,XX @@ static const char *csr_name(int csrno)
45
--- a/target/riscv/machine.c
47
case 0x03bd: return "pmpaddr13";
46
+++ b/target/riscv/machine.c
48
case 0x03be: return "pmpaddr14";
47
@@ -XXX,XX +XXX,XX @@ static bool hyper_needed(void *opaque)
49
case 0x03bf: return "pmpaddr15";
48
50
+ case 0x03c0: return "pmpaddr16";
49
static const VMStateDescription vmstate_hyper = {
51
+ case 0x03c1: return "pmpaddr17";
50
.name = "cpu/hyper",
52
+ case 0x03c2: return "pmpaddr18";
51
- .version_id = 3,
53
+ case 0x03c3: return "pmpaddr19";
52
- .minimum_version_id = 3,
54
+ case 0x03c4: return "pmpaddr20";
53
+ .version_id = 4,
55
+ case 0x03c5: return "pmpaddr21";
54
+ .minimum_version_id = 4,
56
+ case 0x03c6: return "pmpaddr22";
55
.needed = hyper_needed,
57
+ case 0x03c7: return "pmpaddr23";
56
.fields = (const VMStateField[]) {
58
+ case 0x03c8: return "pmpaddr24";
57
VMSTATE_UINTTL(env.hstatus, RISCVCPU),
59
+ case 0x03c9: return "pmpaddr25";
58
VMSTATE_UINTTL(env.hedeleg, RISCVCPU),
60
+ case 0x03ca: return "pmpaddr26";
59
VMSTATE_UINT64(env.hideleg, RISCVCPU),
61
+ case 0x03cb: return "pmpaddr27";
60
- VMSTATE_UINTTL(env.hcounteren, RISCVCPU),
62
+ case 0x03cc: return "pmpaddr28";
61
+ VMSTATE_UINT32(env.hcounteren, RISCVCPU),
63
+ case 0x03cd: return "pmpaddr29";
62
VMSTATE_UINTTL(env.htval, RISCVCPU),
64
+ case 0x03ce: return "pmpaddr30";
63
VMSTATE_UINTTL(env.htinst, RISCVCPU),
65
+ case 0x03cf: return "pmpaddr31";
64
VMSTATE_UINTTL(env.hgatp, RISCVCPU),
66
+ case 0x03d0: return "pmpaddr32";
65
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_jvt = {
67
+ case 0x03d1: return "pmpaddr33";
66
68
+ case 0x03d2: return "pmpaddr34";
67
const VMStateDescription vmstate_riscv_cpu = {
69
+ case 0x03d3: return "pmpaddr35";
68
.name = "cpu",
70
+ case 0x03d4: return "pmpaddr36";
69
- .version_id = 9,
71
+ case 0x03d5: return "pmpaddr37";
70
- .minimum_version_id = 9,
72
+ case 0x03d6: return "pmpaddr38";
71
+ .version_id = 10,
73
+ case 0x03d7: return "pmpaddr39";
72
+ .minimum_version_id = 10,
74
+ case 0x03d8: return "pmpaddr40";
73
.post_load = riscv_cpu_post_load,
75
+ case 0x03d9: return "pmpaddr41";
74
.fields = (const VMStateField[]) {
76
+ case 0x03da: return "pmpaddr42";
75
VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
77
+ case 0x03db: return "pmpaddr43";
76
@@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_riscv_cpu = {
78
+ case 0x03dc: return "pmpaddr44";
77
VMSTATE_UINTTL(env.mtval, RISCVCPU),
79
+ case 0x03dd: return "pmpaddr45";
78
VMSTATE_UINTTL(env.miselect, RISCVCPU),
80
+ case 0x03de: return "pmpaddr46";
79
VMSTATE_UINTTL(env.siselect, RISCVCPU),
81
+ case 0x03df: return "pmpaddr47";
80
- VMSTATE_UINTTL(env.scounteren, RISCVCPU),
82
+ case 0x03e0: return "pmpaddr48";
81
- VMSTATE_UINTTL(env.mcounteren, RISCVCPU),
83
+ case 0x03e1: return "pmpaddr49";
82
- VMSTATE_UINTTL(env.mcountinhibit, RISCVCPU),
84
+ case 0x03e2: return "pmpaddr50";
83
+ VMSTATE_UINT32(env.scounteren, RISCVCPU),
85
+ case 0x03e3: return "pmpaddr51";
84
+ VMSTATE_UINT32(env.mcounteren, RISCVCPU),
86
+ case 0x03e4: return "pmpaddr52";
85
+ VMSTATE_UINT32(env.mcountinhibit, RISCVCPU),
87
+ case 0x03e5: return "pmpaddr53";
86
VMSTATE_STRUCT_ARRAY(env.pmu_ctrs, RISCVCPU, RV_MAX_MHPMCOUNTERS, 0,
88
+ case 0x03e6: return "pmpaddr54";
87
vmstate_pmu_ctr_state, PMUCTRState),
89
+ case 0x03e7: return "pmpaddr55";
88
VMSTATE_UINTTL_ARRAY(env.mhpmevent_val, RISCVCPU, RV_MAX_MHPMEVENTS),
90
+ case 0x03e8: return "pmpaddr56";
91
+ case 0x03e9: return "pmpaddr57";
92
+ case 0x03ea: return "pmpaddr58";
93
+ case 0x03eb: return "pmpaddr59";
94
+ case 0x03ec: return "pmpaddr60";
95
+ case 0x03ed: return "pmpaddr61";
96
+ case 0x03ee: return "pmpaddr62";
97
+ case 0x03ef: return "pmpaddr63";
98
case 0x0780: return "mtohost";
99
case 0x0781: return "mfromhost";
100
case 0x0782: return "mreset";
89
--
101
--
90
2.44.0
102
2.45.1
diff view generated by jsdifflib
[PULL 14/34] target/riscv: UPDATE xATP write CSR
[PULL 28/28] target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR
1
From: Irina Ryapolova <irina.ryapolova@syntacore.com>
1
From: Yu-Ming Chang <yumin686@andestech.com>
2
2
3
Added xATP_MODE validation for vsatp/hgatp CSRs.
3
Both CSRRS and CSRRC always read the addressed CSR and cause any read side
4
The xATP register is an SXLEN-bit read/write WARL register, so
4
effects regardless of rs1 and rd fields. Note that if rs1 specifies a register
5
the legal value must be returned (See riscv-privileged-20211203, SATP/VSATP/HGATP CSRs).
5
holding a zero value other than x0, the instruction will still attempt to write
6
the unmodified value back to the CSR and will cause any attendant side effects.
6
7
7
Signed-off-by: Irina Ryapolova <irina.ryapolova@syntacore.com>
8
So if CSRRS or CSRRC tries to write a read-only CSR with rs1 which specifies
8
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
9
a register holding a zero value, an illegal instruction exception should be
10
raised.
11
12
Signed-off-by: Yu-Ming Chang <yumin686@andestech.com>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
13
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Message-ID: <20240109145923.37893-2-irina.ryapolova@syntacore.com>
14
Message-ID: <20240403070823.80897-1-yumin686@andestech.com>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
15
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
---
16
---
13
target/riscv/csr.c | 52 ++++++++++++++++++++++++++--------------------
17
target/riscv/cpu.h | 4 ++++
14
1 file changed, 29 insertions(+), 23 deletions(-)
18
target/riscv/csr.c | 51 ++++++++++++++++++++++++++++++++++++----
19
target/riscv/op_helper.c | 6 ++---
20
3 files changed, 53 insertions(+), 8 deletions(-)
15
21
22
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
23
index XXXXXXX..XXXXXXX 100644
24
--- a/target/riscv/cpu.h
25
+++ b/target/riscv/cpu.h
26
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
27
void riscv_cpu_update_mask(CPURISCVState *env);
28
bool riscv_cpu_is_32bit(RISCVCPU *cpu);
29
30
+RISCVException riscv_csrr(CPURISCVState *env, int csrno,
31
+ target_ulong *ret_value);
32
RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
33
target_ulong *ret_value,
34
target_ulong new_value, target_ulong write_mask);
35
@@ -XXX,XX +XXX,XX @@ typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
36
target_ulong new_value,
37
target_ulong write_mask);
38
39
+RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno,
40
+ Int128 *ret_value);
41
RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
42
Int128 *ret_value,
43
Int128 new_value, Int128 write_mask);
16
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
44
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
17
index XXXXXXX..XXXXXXX 100644
45
index XXXXXXX..XXXXXXX 100644
18
--- a/target/riscv/csr.c
46
--- a/target/riscv/csr.c
19
+++ b/target/riscv/csr.c
47
+++ b/target/riscv/csr.c
20
@@ -XXX,XX +XXX,XX @@ static bool validate_vm(CPURISCVState *env, target_ulong vm)
48
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_seed(CPURISCVState *env, int csrno,
21
return get_field(mode_supported, (1 << vm));
49
50
static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
51
int csrno,
52
- bool write_mask)
53
+ bool write)
54
{
55
/* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */
56
bool read_only = get_field(csrno, 0xC00) == 3;
57
@@ -XXX,XX +XXX,XX @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
58
}
59
60
/* read / write check */
61
- if (write_mask && read_only) {
62
+ if (write && read_only) {
63
return RISCV_EXCP_ILLEGAL_INST;
64
}
65
66
@@ -XXX,XX +XXX,XX @@ static RISCVException riscv_csrrw_do64(CPURISCVState *env, int csrno,
67
return RISCV_EXCP_NONE;
22
}
68
}
23
69
24
+static target_ulong legalize_xatp(CPURISCVState *env, target_ulong old_xatp,
70
+RISCVException riscv_csrr(CPURISCVState *env, int csrno,
25
+ target_ulong val)
71
+ target_ulong *ret_value)
26
+{
72
+{
27
+ target_ulong mask;
73
+ RISCVException ret = riscv_csrrw_check(env, csrno, false);
28
+ bool vm;
74
+ if (ret != RISCV_EXCP_NONE) {
29
+ if (riscv_cpu_mxl(env) == MXL_RV32) {
75
+ return ret;
30
+ vm = validate_vm(env, get_field(val, SATP32_MODE));
31
+ mask = (val ^ old_xatp) & (SATP32_MODE | SATP32_ASID | SATP32_PPN);
32
+ } else {
33
+ vm = validate_vm(env, get_field(val, SATP64_MODE));
34
+ mask = (val ^ old_xatp) & (SATP64_MODE | SATP64_ASID | SATP64_PPN);
35
+ }
76
+ }
36
+
77
+
37
+ if (vm && mask) {
78
+ return riscv_csrrw_do64(env, csrno, ret_value, 0, 0);
38
+ /*
39
+ * The ISA defines SATP.MODE=Bare as "no translation", but we still
40
+ * pass these through QEMU's TLB emulation as it improves
41
+ * performance. Flushing the TLB on SATP writes with paging
42
+ * enabled avoids leaking those invalid cached mappings.
43
+ */
44
+ tlb_flush(env_cpu(env));
45
+ return val;
46
+ }
47
+ return old_xatp;
48
+}
79
+}
49
+
80
+
50
static target_ulong legalize_mpp(CPURISCVState *env, target_ulong old_mpp,
81
RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
51
target_ulong val)
82
target_ulong *ret_value,
83
target_ulong new_value, target_ulong write_mask)
52
{
84
{
53
@@ -XXX,XX +XXX,XX @@ static RISCVException read_satp(CPURISCVState *env, int csrno,
85
- RISCVException ret = riscv_csrrw_check(env, csrno, write_mask);
54
static RISCVException write_satp(CPURISCVState *env, int csrno,
86
+ RISCVException ret = riscv_csrrw_check(env, csrno, true);
55
target_ulong val)
87
if (ret != RISCV_EXCP_NONE) {
56
{
88
return ret;
57
- target_ulong mask;
58
- bool vm;
59
-
60
if (!riscv_cpu_cfg(env)->mmu) {
61
return RISCV_EXCP_NONE;
62
}
89
}
63
90
@@ -XXX,XX +XXX,XX @@ static RISCVException riscv_csrrw_do128(CPURISCVState *env, int csrno,
64
- if (riscv_cpu_mxl(env) == MXL_RV32) {
65
- vm = validate_vm(env, get_field(val, SATP32_MODE));
66
- mask = (val ^ env->satp) & (SATP32_MODE | SATP32_ASID | SATP32_PPN);
67
- } else {
68
- vm = validate_vm(env, get_field(val, SATP64_MODE));
69
- mask = (val ^ env->satp) & (SATP64_MODE | SATP64_ASID | SATP64_PPN);
70
- }
71
-
72
- if (vm && mask) {
73
- /*
74
- * The ISA defines SATP.MODE=Bare as "no translation", but we still
75
- * pass these through QEMU's TLB emulation as it improves
76
- * performance. Flushing the TLB on SATP writes with paging
77
- * enabled avoids leaking those invalid cached mappings.
78
- */
79
- tlb_flush(env_cpu(env));
80
- env->satp = val;
81
- }
82
+ env->satp = legalize_xatp(env, env->satp, val);
83
return RISCV_EXCP_NONE;
91
return RISCV_EXCP_NONE;
84
}
92
}
85
93
86
@@ -XXX,XX +XXX,XX @@ static RISCVException read_hgatp(CPURISCVState *env, int csrno,
94
+RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno,
87
static RISCVException write_hgatp(CPURISCVState *env, int csrno,
95
+ Int128 *ret_value)
88
target_ulong val)
96
+{
97
+ RISCVException ret;
98
+
99
+ ret = riscv_csrrw_check(env, csrno, false);
100
+ if (ret != RISCV_EXCP_NONE) {
101
+ return ret;
102
+ }
103
+
104
+ if (csr_ops[csrno].read128) {
105
+ return riscv_csrrw_do128(env, csrno, ret_value,
106
+ int128_zero(), int128_zero());
107
+ }
108
+
109
+ /*
110
+ * Fall back to 64-bit version for now, if the 128-bit alternative isn't
111
+ * at all defined.
112
+ * Note, some CSRs don't need to extend to MXLEN (64 upper bits non
113
+ * significant), for those, this fallback is correctly handling the
114
+ * accesses
115
+ */
116
+ target_ulong old_value;
117
+ ret = riscv_csrrw_do64(env, csrno, &old_value,
118
+ (target_ulong)0,
119
+ (target_ulong)0);
120
+ if (ret == RISCV_EXCP_NONE && ret_value) {
121
+ *ret_value = int128_make64(old_value);
122
+ }
123
+ return ret;
124
+}
125
+
126
RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
127
Int128 *ret_value,
128
Int128 new_value, Int128 write_mask)
89
{
129
{
90
- env->hgatp = val;
130
RISCVException ret;
91
+ env->hgatp = legalize_xatp(env, env->hgatp, val);
131
92
return RISCV_EXCP_NONE;
132
- ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask));
93
}
133
+ ret = riscv_csrrw_check(env, csrno, true);
94
134
if (ret != RISCV_EXCP_NONE) {
95
@@ -XXX,XX +XXX,XX @@ static RISCVException read_vsatp(CPURISCVState *env, int csrno,
135
return ret;
96
static RISCVException write_vsatp(CPURISCVState *env, int csrno,
136
}
97
target_ulong val)
137
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
138
index XXXXXXX..XXXXXXX 100644
139
--- a/target/riscv/op_helper.c
140
+++ b/target/riscv/op_helper.c
141
@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrr(CPURISCVState *env, int csr)
142
}
143
144
target_ulong val = 0;
145
- RISCVException ret = riscv_csrrw(env, csr, &val, 0, 0);
146
+ RISCVException ret = riscv_csrr(env, csr, &val);
147
148
if (ret != RISCV_EXCP_NONE) {
149
riscv_raise_exception(env, ret, GETPC());
150
@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrrw(CPURISCVState *env, int csr,
151
target_ulong helper_csrr_i128(CPURISCVState *env, int csr)
98
{
152
{
99
- env->vsatp = val;
153
Int128 rv = int128_zero();
100
+ env->vsatp = legalize_xatp(env, env->vsatp, val);
154
- RISCVException ret = riscv_csrrw_i128(env, csr, &rv,
101
return RISCV_EXCP_NONE;
155
- int128_zero(),
102
}
156
- int128_zero());
103
157
+ RISCVException ret = riscv_csrr_i128(env, csr, &rv);
158
159
if (ret != RISCV_EXCP_NONE) {
160
riscv_raise_exception(env, ret, GETPC());
104
--
161
--
105
2.44.0
162
2.45.1
diff view generated by jsdifflib
[PULL 24/34] linux-headers: Update to Linux v6.8-rc6
Deleted patch
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
2
1
3
The idea with this update is to get the latest KVM caps for RISC-V.
4
5
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
6
Acked-by: Alistair Francis <alistair.francis@wdc.com>
7
Message-ID: <20240304134732.386590-2-dbarboza@ventanamicro.com>
8
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
9
---
10
include/standard-headers/drm/drm_fourcc.h | 10 +-
11
include/standard-headers/linux/ethtool.h | 41 +++--
12
.../standard-headers/linux/virtio_config.h | 8 +-
13
include/standard-headers/linux/virtio_pci.h | 68 +++++++++
14
include/standard-headers/linux/virtio_pmem.h | 7 +
15
linux-headers/asm-generic/unistd.h | 15 +-
16
linux-headers/asm-mips/mman.h | 2 +-
17
linux-headers/asm-mips/unistd_n32.h | 5 +
18
linux-headers/asm-mips/unistd_n64.h | 5 +
19
linux-headers/asm-mips/unistd_o32.h | 5 +
20
linux-headers/asm-powerpc/unistd_32.h | 5 +
21
linux-headers/asm-powerpc/unistd_64.h | 5 +
22
linux-headers/asm-riscv/kvm.h | 40 +++++
23
linux-headers/asm-s390/unistd_32.h | 5 +
24
linux-headers/asm-s390/unistd_64.h | 5 +
25
linux-headers/asm-x86/kvm.h | 3 +
26
linux-headers/asm-x86/unistd_32.h | 5 +
27
linux-headers/asm-x86/unistd_64.h | 5 +
28
linux-headers/asm-x86/unistd_x32.h | 5 +
29
linux-headers/linux/iommufd.h | 79 ++++++++++
30
linux-headers/linux/kvm.h | 140 +++++++-----------
31
linux-headers/linux/userfaultfd.h | 29 +++-
32
linux-headers/linux/vfio.h | 1 +
33
23 files changed, 381 insertions(+), 112 deletions(-)
34
35
diff --git a/include/standard-headers/drm/drm_fourcc.h b/include/standard-headers/drm/drm_fourcc.h
36
index XXXXXXX..XXXXXXX 100644
37
--- a/include/standard-headers/drm/drm_fourcc.h
38
+++ b/include/standard-headers/drm/drm_fourcc.h
39
@@ -XXX,XX +XXX,XX @@ extern "C" {
40
* Format modifiers may change any property of the buffer, including the number
41
* of planes and/or the required allocation size. Format modifiers are
42
* vendor-namespaced, and as such the relationship between a fourcc code and a
43
- * modifier is specific to the modifer being used. For example, some modifiers
44
+ * modifier is specific to the modifier being used. For example, some modifiers
45
* may preserve meaning - such as number of planes - from the fourcc code,
46
* whereas others may not.
47
*
48
@@ -XXX,XX +XXX,XX @@ extern "C" {
49
* format.
50
* - Higher-level programs interfacing with KMS/GBM/EGL/Vulkan/etc: these users
51
* see modifiers as opaque tokens they can check for equality and intersect.
52
- * These users musn't need to know to reason about the modifier value
53
+ * These users mustn't need to know to reason about the modifier value
54
* (i.e. they are not expected to extract information out of the modifier).
55
*
56
* Vendors should document their modifier usage in as much detail as
57
@@ -XXX,XX +XXX,XX @@ extern "C" {
58
* This is a tiled layout using 4Kb tiles in row-major layout.
59
* Within the tile pixels are laid out in 16 256 byte units / sub-tiles which
60
* are arranged in four groups (two wide, two high) with column-major layout.
61
- * Each group therefore consits out of four 256 byte units, which are also laid
62
+ * Each group therefore consists out of four 256 byte units, which are also laid
63
* out as 2x2 column-major.
64
* 256 byte units are made out of four 64 byte blocks of pixels, producing
65
* either a square block or a 2:1 unit.
66
@@ -XXX,XX +XXX,XX @@ drm_fourcc_canonicalize_nvidia_format_mod(uint64_t modifier)
67
*/
68
69
/*
70
- * The top 4 bits (out of the 56 bits alloted for specifying vendor specific
71
+ * The top 4 bits (out of the 56 bits allotted for specifying vendor specific
72
* modifiers) denote the category for modifiers. Currently we have three
73
* categories of modifiers ie AFBC, MISC and AFRC. We can have a maximum of
74
* sixteen different categories.
75
@@ -XXX,XX +XXX,XX @@ drm_fourcc_canonicalize_nvidia_format_mod(uint64_t modifier)
76
* Amlogic FBC Memory Saving mode
77
*
78
* Indicates the storage is packed when pixel size is multiple of word
79
- * boudaries, i.e. 8bit should be stored in this mode to save allocation
80
+ * boundaries, i.e. 8bit should be stored in this mode to save allocation
81
* memory.
82
*
83
* This mode reduces body layout to 3072 bytes per 64x32 superblock with
84
diff --git a/include/standard-headers/linux/ethtool.h b/include/standard-headers/linux/ethtool.h
85
index XXXXXXX..XXXXXXX 100644
86
--- a/include/standard-headers/linux/ethtool.h
87
+++ b/include/standard-headers/linux/ethtool.h
88
@@ -XXX,XX +XXX,XX @@ struct ethtool_rxfh_indir {
89
*    hardware hash key.
90
* @hfunc: Defines the current RSS hash function used by HW (or to be set to).
91
*    Valid values are one of the %ETH_RSS_HASH_*.
92
+ * @input_xfrm: Defines how the input data is transformed. Valid values are one
93
+ *    of %RXH_XFRM_*.
94
* @rsvd8: Reserved for future use; see the note on reserved space.
95
* @rsvd32: Reserved for future use; see the note on reserved space.
96
* @rss_config: RX ring/queue index for each hash value i.e., indirection table
97
@@ -XXX,XX +XXX,XX @@ struct ethtool_rxfh {
98
    uint32_t indir_size;
99
    uint32_t key_size;
100
    uint8_t    hfunc;
101
-    uint8_t    rsvd8[3];
102
+    uint8_t    input_xfrm;
103
+    uint8_t    rsvd8[2];
104
    uint32_t    rsvd32;
105
    uint32_t rss_config[];
106
};
107
@@ -XXX,XX +XXX,XX @@ static inline int ethtool_validate_duplex(uint8_t duplex)
108
109
#define WOL_MODE_COUNT        8
110
111
+/* RSS hash function data
112
+ * XOR the corresponding source and destination fields of each specified
113
+ * protocol. Both copies of the XOR'ed fields are fed into the RSS and RXHASH
114
+ * calculation. Note that this XORing reduces the input set entropy and could
115
+ * be exploited to reduce the RSS queue spread.
116
+ */
117
+#define    RXH_XFRM_SYM_XOR    (1 << 0)
118
+#define    RXH_XFRM_NO_CHANGE    0xff
119
+
120
/* L2-L4 network traffic flow types */
121
#define    TCP_V4_FLOW    0x01    /* hash or spec (tcp_ip4_spec) */
122
#define    UDP_V4_FLOW    0x02    /* hash or spec (udp_ip4_spec) */
123
@@ -XXX,XX +XXX,XX @@ enum ethtool_reset_flags {
124
*    refused. For drivers: ignore this field (use kernel's
125
*    __ETHTOOL_LINK_MODE_MASK_NBITS instead), any change to it will
126
*    be overwritten by kernel.
127
- * @supported: Bitmap with each bit meaning given by
128
- *    %ethtool_link_mode_bit_indices for the link modes, physical
129
- *    connectors and other link features for which the interface
130
- *    supports autonegotiation or auto-detection. Read-only.
131
- * @advertising: Bitmap with each bit meaning given by
132
- *    %ethtool_link_mode_bit_indices for the link modes, physical
133
- *    connectors and other link features that are advertised through
134
- *    autonegotiation or enabled for auto-detection.
135
- * @lp_advertising: Bitmap with each bit meaning given by
136
- *    %ethtool_link_mode_bit_indices for the link modes, and other
137
- *    link features that the link partner advertised through
138
- *    autonegotiation; 0 if unknown or not applicable. Read-only.
139
* @transceiver: Used to distinguish different possible PHY types,
140
*    reported consistently by PHYLIB. Read-only.
141
* @master_slave_cfg: Master/slave port mode.
142
@@ -XXX,XX +XXX,XX @@ enum ethtool_reset_flags {
143
* %set_link_ksettings() should validate all fields other than @cmd
144
* and @link_mode_masks_nwords that are not described as read-only or
145
* deprecated, and must ignore all fields described as read-only.
146
+ *
147
+ * @link_mode_masks is divided into three bitfields, each of length
148
+ * @link_mode_masks_nwords:
149
+ * - supported: Bitmap with each bit meaning given by
150
+ *    %ethtool_link_mode_bit_indices for the link modes, physical
151
+ *    connectors and other link features for which the interface
152
+ *    supports autonegotiation or auto-detection. Read-only.
153
+ * - advertising: Bitmap with each bit meaning given by
154
+ *    %ethtool_link_mode_bit_indices for the link modes, physical
155
+ *    connectors and other link features that are advertised through
156
+ *    autonegotiation or enabled for auto-detection.
157
+ * - lp_advertising: Bitmap with each bit meaning given by
158
+ *    %ethtool_link_mode_bit_indices for the link modes, and other
159
+ *    link features that the link partner advertised through
160
+ *    autonegotiation; 0 if unknown or not applicable. Read-only.
161
*/
162
struct ethtool_link_settings {
163
    uint32_t    cmd;
164
diff --git a/include/standard-headers/linux/virtio_config.h b/include/standard-headers/linux/virtio_config.h
165
index XXXXXXX..XXXXXXX 100644
166
--- a/include/standard-headers/linux/virtio_config.h
167
+++ b/include/standard-headers/linux/virtio_config.h
168
@@ -XXX,XX +XXX,XX @@
169
* rest are per-device feature bits.
170
*/
171
#define VIRTIO_TRANSPORT_F_START    28
172
-#define VIRTIO_TRANSPORT_F_END        41
173
+#define VIRTIO_TRANSPORT_F_END        42
174
175
#ifndef VIRTIO_CONFIG_NO_LEGACY
176
/* Do we get callbacks when the ring is completely used, even if we've
177
@@ -XXX,XX +XXX,XX @@
178
* This feature indicates that the driver can reset a queue individually.
179
*/
180
#define VIRTIO_F_RING_RESET        40
181
+
182
+/*
183
+ * This feature indicates that the device support administration virtqueues.
184
+ */
185
+#define VIRTIO_F_ADMIN_VQ        41
186
+
187
#endif /* _LINUX_VIRTIO_CONFIG_H */
188
diff --git a/include/standard-headers/linux/virtio_pci.h b/include/standard-headers/linux/virtio_pci.h
189
index XXXXXXX..XXXXXXX 100644
190
--- a/include/standard-headers/linux/virtio_pci.h
191
+++ b/include/standard-headers/linux/virtio_pci.h
192
@@ -XXX,XX +XXX,XX @@ struct virtio_pci_modern_common_cfg {
193
194
    uint16_t queue_notify_data;    /* read-write */
195
    uint16_t queue_reset;        /* read-write */
196
+
197
+    uint16_t admin_queue_index;    /* read-only */
198
+    uint16_t admin_queue_num;        /* read-only */
199
};
200
201
/* Fields in VIRTIO_PCI_CAP_PCI_CFG: */
202
@@ -XXX,XX +XXX,XX @@ struct virtio_pci_cfg_cap {
203
#define VIRTIO_PCI_COMMON_Q_USEDHI    52
204
#define VIRTIO_PCI_COMMON_Q_NDATA    56
205
#define VIRTIO_PCI_COMMON_Q_RESET    58
206
+#define VIRTIO_PCI_COMMON_ADM_Q_IDX    60
207
+#define VIRTIO_PCI_COMMON_ADM_Q_NUM    62
208
209
#endif /* VIRTIO_PCI_NO_MODERN */
210
211
+/* Admin command status. */
212
+#define VIRTIO_ADMIN_STATUS_OK        0
213
+
214
+/* Admin command opcode. */
215
+#define VIRTIO_ADMIN_CMD_LIST_QUERY    0x0
216
+#define VIRTIO_ADMIN_CMD_LIST_USE    0x1
217
+
218
+/* Admin command group type. */
219
+#define VIRTIO_ADMIN_GROUP_TYPE_SRIOV    0x1
220
+
221
+/* Transitional device admin command. */
222
+#define VIRTIO_ADMIN_CMD_LEGACY_COMMON_CFG_WRITE    0x2
223
+#define VIRTIO_ADMIN_CMD_LEGACY_COMMON_CFG_READ        0x3
224
+#define VIRTIO_ADMIN_CMD_LEGACY_DEV_CFG_WRITE        0x4
225
+#define VIRTIO_ADMIN_CMD_LEGACY_DEV_CFG_READ        0x5
226
+#define VIRTIO_ADMIN_CMD_LEGACY_NOTIFY_INFO        0x6
227
+
228
+struct QEMU_PACKED virtio_admin_cmd_hdr {
229
+    uint16_t opcode;
230
+    /*
231
+     * 1 - SR-IOV
232
+     * 2-65535 - reserved
233
+     */
234
+    uint16_t group_type;
235
+    /* Unused, reserved for future extensions. */
236
+    uint8_t reserved1[12];
237
+    uint64_t group_member_id;
238
+};
239
+
240
+struct QEMU_PACKED virtio_admin_cmd_status {
241
+    uint16_t status;
242
+    uint16_t status_qualifier;
243
+    /* Unused, reserved for future extensions. */
244
+    uint8_t reserved2[4];
245
+};
246
+
247
+struct QEMU_PACKED virtio_admin_cmd_legacy_wr_data {
248
+    uint8_t offset; /* Starting offset of the register(s) to write. */
249
+    uint8_t reserved[7];
250
+    uint8_t registers[];
251
+};
252
+
253
+struct QEMU_PACKED virtio_admin_cmd_legacy_rd_data {
254
+    uint8_t offset; /* Starting offset of the register(s) to read. */
255
+};
256
+
257
+#define VIRTIO_ADMIN_CMD_NOTIFY_INFO_FLAGS_END 0
258
+#define VIRTIO_ADMIN_CMD_NOTIFY_INFO_FLAGS_OWNER_DEV 0x1
259
+#define VIRTIO_ADMIN_CMD_NOTIFY_INFO_FLAGS_OWNER_MEM 0x2
260
+
261
+#define VIRTIO_ADMIN_CMD_MAX_NOTIFY_INFO 4
262
+
263
+struct QEMU_PACKED virtio_admin_cmd_notify_info_data {
264
+    uint8_t flags; /* 0 = end of list, 1 = owner device, 2 = member device */
265
+    uint8_t bar; /* BAR of the member or the owner device */
266
+    uint8_t padding[6];
267
+    uint64_t offset; /* Offset within bar. */
268
+};
269
+
270
+struct virtio_admin_cmd_notify_info_result {
271
+    struct virtio_admin_cmd_notify_info_data entries[VIRTIO_ADMIN_CMD_MAX_NOTIFY_INFO];
272
+};
273
+
274
#endif
275
diff --git a/include/standard-headers/linux/virtio_pmem.h b/include/standard-headers/linux/virtio_pmem.h
276
index XXXXXXX..XXXXXXX 100644
277
--- a/include/standard-headers/linux/virtio_pmem.h
278
+++ b/include/standard-headers/linux/virtio_pmem.h
279
@@ -XXX,XX +XXX,XX @@
280
#include "standard-headers/linux/virtio_ids.h"
281
#include "standard-headers/linux/virtio_config.h"
282
283
+/* Feature bits */
284
+/* guest physical address range will be indicated as shared memory region 0 */
285
+#define VIRTIO_PMEM_F_SHMEM_REGION 0
286
+
287
+/* shmid of the shared memory region corresponding to the pmem */
288
+#define VIRTIO_PMEM_SHMEM_REGION_ID 0
289
+
290
struct virtio_pmem_config {
291
    uint64_t start;
292
    uint64_t size;
293
diff --git a/linux-headers/asm-generic/unistd.h b/linux-headers/asm-generic/unistd.h
294
index XXXXXXX..XXXXXXX 100644
295
--- a/linux-headers/asm-generic/unistd.h
296
+++ b/linux-headers/asm-generic/unistd.h
297
@@ -XXX,XX +XXX,XX @@ __SYSCALL(__NR_futex_wait, sys_futex_wait)
298
#define __NR_futex_requeue 456
299
__SYSCALL(__NR_futex_requeue, sys_futex_requeue)
300
301
+#define __NR_statmount 457
302
+__SYSCALL(__NR_statmount, sys_statmount)
303
+
304
+#define __NR_listmount 458
305
+__SYSCALL(__NR_listmount, sys_listmount)
306
+
307
+#define __NR_lsm_get_self_attr 459
308
+__SYSCALL(__NR_lsm_get_self_attr, sys_lsm_get_self_attr)
309
+#define __NR_lsm_set_self_attr 460
310
+__SYSCALL(__NR_lsm_set_self_attr, sys_lsm_set_self_attr)
311
+#define __NR_lsm_list_modules 461
312
+__SYSCALL(__NR_lsm_list_modules, sys_lsm_list_modules)
313
+
314
#undef __NR_syscalls
315
-#define __NR_syscalls 457
316
+#define __NR_syscalls 462
317
318
/*
319
* 32 bit systems traditionally used different
320
diff --git a/linux-headers/asm-mips/mman.h b/linux-headers/asm-mips/mman.h
321
index XXXXXXX..XXXXXXX 100644
322
--- a/linux-headers/asm-mips/mman.h
323
+++ b/linux-headers/asm-mips/mman.h
324
@@ -XXX,XX +XXX,XX @@
325
#define MADV_HUGEPAGE    14        /* Worth backing with hugepages */
326
#define MADV_NOHUGEPAGE 15        /* Not worth backing with hugepages */
327
328
-#define MADV_DONTDUMP    16        /* Explicity exclude from the core dump,
329
+#define MADV_DONTDUMP    16        /* Explicitly exclude from core dump,
330
                     overrides the coredump filter bits */
331
#define MADV_DODUMP    17        /* Clear the MADV_NODUMP flag */
332
333
diff --git a/linux-headers/asm-mips/unistd_n32.h b/linux-headers/asm-mips/unistd_n32.h
334
index XXXXXXX..XXXXXXX 100644
335
--- a/linux-headers/asm-mips/unistd_n32.h
336
+++ b/linux-headers/asm-mips/unistd_n32.h
337
@@ -XXX,XX +XXX,XX @@
338
#define __NR_futex_wake (__NR_Linux + 454)
339
#define __NR_futex_wait (__NR_Linux + 455)
340
#define __NR_futex_requeue (__NR_Linux + 456)
341
+#define __NR_statmount (__NR_Linux + 457)
342
+#define __NR_listmount (__NR_Linux + 458)
343
+#define __NR_lsm_get_self_attr (__NR_Linux + 459)
344
+#define __NR_lsm_set_self_attr (__NR_Linux + 460)
345
+#define __NR_lsm_list_modules (__NR_Linux + 461)
346
347
#endif /* _ASM_UNISTD_N32_H */
348
diff --git a/linux-headers/asm-mips/unistd_n64.h b/linux-headers/asm-mips/unistd_n64.h
349
index XXXXXXX..XXXXXXX 100644
350
--- a/linux-headers/asm-mips/unistd_n64.h
351
+++ b/linux-headers/asm-mips/unistd_n64.h
352
@@ -XXX,XX +XXX,XX @@
353
#define __NR_futex_wake (__NR_Linux + 454)
354
#define __NR_futex_wait (__NR_Linux + 455)
355
#define __NR_futex_requeue (__NR_Linux + 456)
356
+#define __NR_statmount (__NR_Linux + 457)
357
+#define __NR_listmount (__NR_Linux + 458)
358
+#define __NR_lsm_get_self_attr (__NR_Linux + 459)
359
+#define __NR_lsm_set_self_attr (__NR_Linux + 460)
360
+#define __NR_lsm_list_modules (__NR_Linux + 461)
361
362
#endif /* _ASM_UNISTD_N64_H */
363
diff --git a/linux-headers/asm-mips/unistd_o32.h b/linux-headers/asm-mips/unistd_o32.h
364
index XXXXXXX..XXXXXXX 100644
365
--- a/linux-headers/asm-mips/unistd_o32.h
366
+++ b/linux-headers/asm-mips/unistd_o32.h
367
@@ -XXX,XX +XXX,XX @@
368
#define __NR_futex_wake (__NR_Linux + 454)
369
#define __NR_futex_wait (__NR_Linux + 455)
370
#define __NR_futex_requeue (__NR_Linux + 456)
371
+#define __NR_statmount (__NR_Linux + 457)
372
+#define __NR_listmount (__NR_Linux + 458)
373
+#define __NR_lsm_get_self_attr (__NR_Linux + 459)
374
+#define __NR_lsm_set_self_attr (__NR_Linux + 460)
375
+#define __NR_lsm_list_modules (__NR_Linux + 461)
376
377
#endif /* _ASM_UNISTD_O32_H */
378
diff --git a/linux-headers/asm-powerpc/unistd_32.h b/linux-headers/asm-powerpc/unistd_32.h
379
index XXXXXXX..XXXXXXX 100644
380
--- a/linux-headers/asm-powerpc/unistd_32.h
381
+++ b/linux-headers/asm-powerpc/unistd_32.h
382
@@ -XXX,XX +XXX,XX @@
383
#define __NR_futex_wake 454
384
#define __NR_futex_wait 455
385
#define __NR_futex_requeue 456
386
+#define __NR_statmount 457
387
+#define __NR_listmount 458
388
+#define __NR_lsm_get_self_attr 459
389
+#define __NR_lsm_set_self_attr 460
390
+#define __NR_lsm_list_modules 461
391
392
393
#endif /* _ASM_UNISTD_32_H */
394
diff --git a/linux-headers/asm-powerpc/unistd_64.h b/linux-headers/asm-powerpc/unistd_64.h
395
index XXXXXXX..XXXXXXX 100644
396
--- a/linux-headers/asm-powerpc/unistd_64.h
397
+++ b/linux-headers/asm-powerpc/unistd_64.h
398
@@ -XXX,XX +XXX,XX @@
399
#define __NR_futex_wake 454
400
#define __NR_futex_wait 455
401
#define __NR_futex_requeue 456
402
+#define __NR_statmount 457
403
+#define __NR_listmount 458
404
+#define __NR_lsm_get_self_attr 459
405
+#define __NR_lsm_set_self_attr 460
406
+#define __NR_lsm_list_modules 461
407
408
409
#endif /* _ASM_UNISTD_64_H */
410
diff --git a/linux-headers/asm-riscv/kvm.h b/linux-headers/asm-riscv/kvm.h
411
index XXXXXXX..XXXXXXX 100644
412
--- a/linux-headers/asm-riscv/kvm.h
413
+++ b/linux-headers/asm-riscv/kvm.h
414
@@ -XXX,XX +XXX,XX @@ enum KVM_RISCV_ISA_EXT_ID {
415
    KVM_RISCV_ISA_EXT_ZIHPM,
416
    KVM_RISCV_ISA_EXT_SMSTATEEN,
417
    KVM_RISCV_ISA_EXT_ZICOND,
418
+    KVM_RISCV_ISA_EXT_ZBC,
419
+    KVM_RISCV_ISA_EXT_ZBKB,
420
+    KVM_RISCV_ISA_EXT_ZBKC,
421
+    KVM_RISCV_ISA_EXT_ZBKX,
422
+    KVM_RISCV_ISA_EXT_ZKND,
423
+    KVM_RISCV_ISA_EXT_ZKNE,
424
+    KVM_RISCV_ISA_EXT_ZKNH,
425
+    KVM_RISCV_ISA_EXT_ZKR,
426
+    KVM_RISCV_ISA_EXT_ZKSED,
427
+    KVM_RISCV_ISA_EXT_ZKSH,
428
+    KVM_RISCV_ISA_EXT_ZKT,
429
+    KVM_RISCV_ISA_EXT_ZVBB,
430
+    KVM_RISCV_ISA_EXT_ZVBC,
431
+    KVM_RISCV_ISA_EXT_ZVKB,
432
+    KVM_RISCV_ISA_EXT_ZVKG,
433
+    KVM_RISCV_ISA_EXT_ZVKNED,
434
+    KVM_RISCV_ISA_EXT_ZVKNHA,
435
+    KVM_RISCV_ISA_EXT_ZVKNHB,
436
+    KVM_RISCV_ISA_EXT_ZVKSED,
437
+    KVM_RISCV_ISA_EXT_ZVKSH,
438
+    KVM_RISCV_ISA_EXT_ZVKT,
439
+    KVM_RISCV_ISA_EXT_ZFH,
440
+    KVM_RISCV_ISA_EXT_ZFHMIN,
441
+    KVM_RISCV_ISA_EXT_ZIHINTNTL,
442
+    KVM_RISCV_ISA_EXT_ZVFH,
443
+    KVM_RISCV_ISA_EXT_ZVFHMIN,
444
+    KVM_RISCV_ISA_EXT_ZFA,
445
    KVM_RISCV_ISA_EXT_MAX,
446
};
447
448
@@ -XXX,XX +XXX,XX @@ enum KVM_RISCV_SBI_EXT_ID {
449
    KVM_RISCV_SBI_EXT_EXPERIMENTAL,
450
    KVM_RISCV_SBI_EXT_VENDOR,
451
    KVM_RISCV_SBI_EXT_DBCN,
452
+    KVM_RISCV_SBI_EXT_STA,
453
    KVM_RISCV_SBI_EXT_MAX,
454
};
455
456
+/* SBI STA extension registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
457
+struct kvm_riscv_sbi_sta {
458
+    unsigned long shmem_lo;
459
+    unsigned long shmem_hi;
460
+};
461
+
462
/* Possible states for kvm_riscv_timer */
463
#define KVM_RISCV_TIMER_STATE_OFF    0
464
#define KVM_RISCV_TIMER_STATE_ON    1
465
@@ -XXX,XX +XXX,XX @@ enum KVM_RISCV_SBI_EXT_ID {
466
#define KVM_REG_RISCV_VECTOR_REG(n)    \
467
        ((n) + sizeof(struct __riscv_v_ext_state) / sizeof(unsigned long))
468
469
+/* Registers for specific SBI extensions are mapped as type 10 */
470
+#define KVM_REG_RISCV_SBI_STATE        (0x0a << KVM_REG_RISCV_TYPE_SHIFT)
471
+#define KVM_REG_RISCV_SBI_STA        (0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT)
472
+#define KVM_REG_RISCV_SBI_STA_REG(name)        \
473
+        (offsetof(struct kvm_riscv_sbi_sta, name) / sizeof(unsigned long))
474
+
475
/* Device Control API: RISC-V AIA */
476
#define KVM_DEV_RISCV_APLIC_ALIGN        0x1000
477
#define KVM_DEV_RISCV_APLIC_SIZE        0x4000
478
diff --git a/linux-headers/asm-s390/unistd_32.h b/linux-headers/asm-s390/unistd_32.h
479
index XXXXXXX..XXXXXXX 100644
480
--- a/linux-headers/asm-s390/unistd_32.h
481
+++ b/linux-headers/asm-s390/unistd_32.h
482
@@ -XXX,XX +XXX,XX @@
483
#define __NR_futex_wake 454
484
#define __NR_futex_wait 455
485
#define __NR_futex_requeue 456
486
+#define __NR_statmount 457
487
+#define __NR_listmount 458
488
+#define __NR_lsm_get_self_attr 459
489
+#define __NR_lsm_set_self_attr 460
490
+#define __NR_lsm_list_modules 461
491
492
#endif /* _ASM_S390_UNISTD_32_H */
493
diff --git a/linux-headers/asm-s390/unistd_64.h b/linux-headers/asm-s390/unistd_64.h
494
index XXXXXXX..XXXXXXX 100644
495
--- a/linux-headers/asm-s390/unistd_64.h
496
+++ b/linux-headers/asm-s390/unistd_64.h
497
@@ -XXX,XX +XXX,XX @@
498
#define __NR_futex_wake 454
499
#define __NR_futex_wait 455
500
#define __NR_futex_requeue 456
501
+#define __NR_statmount 457
502
+#define __NR_listmount 458
503
+#define __NR_lsm_get_self_attr 459
504
+#define __NR_lsm_set_self_attr 460
505
+#define __NR_lsm_list_modules 461
506
507
#endif /* _ASM_S390_UNISTD_64_H */
508
diff --git a/linux-headers/asm-x86/kvm.h b/linux-headers/asm-x86/kvm.h
509
index XXXXXXX..XXXXXXX 100644
510
--- a/linux-headers/asm-x86/kvm.h
511
+++ b/linux-headers/asm-x86/kvm.h
512
@@ -XXX,XX +XXX,XX @@ struct kvm_pmu_event_filter {
513
/* x86-specific KVM_EXIT_HYPERCALL flags. */
514
#define KVM_EXIT_HYPERCALL_LONG_MODE    BIT(0)
515
516
+#define KVM_X86_DEFAULT_VM    0
517
+#define KVM_X86_SW_PROTECTED_VM    1
518
+
519
#endif /* _ASM_X86_KVM_H */
520
diff --git a/linux-headers/asm-x86/unistd_32.h b/linux-headers/asm-x86/unistd_32.h
521
index XXXXXXX..XXXXXXX 100644
522
--- a/linux-headers/asm-x86/unistd_32.h
523
+++ b/linux-headers/asm-x86/unistd_32.h
524
@@ -XXX,XX +XXX,XX @@
525
#define __NR_futex_wake 454
526
#define __NR_futex_wait 455
527
#define __NR_futex_requeue 456
528
+#define __NR_statmount 457
529
+#define __NR_listmount 458
530
+#define __NR_lsm_get_self_attr 459
531
+#define __NR_lsm_set_self_attr 460
532
+#define __NR_lsm_list_modules 461
533
534
535
#endif /* _ASM_UNISTD_32_H */
536
diff --git a/linux-headers/asm-x86/unistd_64.h b/linux-headers/asm-x86/unistd_64.h
537
index XXXXXXX..XXXXXXX 100644
538
--- a/linux-headers/asm-x86/unistd_64.h
539
+++ b/linux-headers/asm-x86/unistd_64.h
540
@@ -XXX,XX +XXX,XX @@
541
#define __NR_futex_wake 454
542
#define __NR_futex_wait 455
543
#define __NR_futex_requeue 456
544
+#define __NR_statmount 457
545
+#define __NR_listmount 458
546
+#define __NR_lsm_get_self_attr 459
547
+#define __NR_lsm_set_self_attr 460
548
+#define __NR_lsm_list_modules 461
549
550
551
#endif /* _ASM_UNISTD_64_H */
552
diff --git a/linux-headers/asm-x86/unistd_x32.h b/linux-headers/asm-x86/unistd_x32.h
553
index XXXXXXX..XXXXXXX 100644
554
--- a/linux-headers/asm-x86/unistd_x32.h
555
+++ b/linux-headers/asm-x86/unistd_x32.h
556
@@ -XXX,XX +XXX,XX @@
557
#define __NR_futex_wake (__X32_SYSCALL_BIT + 454)
558
#define __NR_futex_wait (__X32_SYSCALL_BIT + 455)
559
#define __NR_futex_requeue (__X32_SYSCALL_BIT + 456)
560
+#define __NR_statmount (__X32_SYSCALL_BIT + 457)
561
+#define __NR_listmount (__X32_SYSCALL_BIT + 458)
562
+#define __NR_lsm_get_self_attr (__X32_SYSCALL_BIT + 459)
563
+#define __NR_lsm_set_self_attr (__X32_SYSCALL_BIT + 460)
564
+#define __NR_lsm_list_modules (__X32_SYSCALL_BIT + 461)
565
#define __NR_rt_sigaction (__X32_SYSCALL_BIT + 512)
566
#define __NR_rt_sigreturn (__X32_SYSCALL_BIT + 513)
567
#define __NR_ioctl (__X32_SYSCALL_BIT + 514)
568
diff --git a/linux-headers/linux/iommufd.h b/linux-headers/linux/iommufd.h
569
index XXXXXXX..XXXXXXX 100644
570
--- a/linux-headers/linux/iommufd.h
571
+++ b/linux-headers/linux/iommufd.h
572
@@ -XXX,XX +XXX,XX @@ enum {
573
    IOMMUFD_CMD_GET_HW_INFO,
574
    IOMMUFD_CMD_HWPT_SET_DIRTY_TRACKING,
575
    IOMMUFD_CMD_HWPT_GET_DIRTY_BITMAP,
576
+    IOMMUFD_CMD_HWPT_INVALIDATE,
577
};
578
579
/**
580
@@ -XXX,XX +XXX,XX @@ struct iommu_hwpt_get_dirty_bitmap {
581
#define IOMMU_HWPT_GET_DIRTY_BITMAP _IO(IOMMUFD_TYPE, \
582
                    IOMMUFD_CMD_HWPT_GET_DIRTY_BITMAP)
583
584
+/**
585
+ * enum iommu_hwpt_invalidate_data_type - IOMMU HWPT Cache Invalidation
586
+ * Data Type
587
+ * @IOMMU_HWPT_INVALIDATE_DATA_VTD_S1: Invalidation data for VTD_S1
588
+ */
589
+enum iommu_hwpt_invalidate_data_type {
590
+    IOMMU_HWPT_INVALIDATE_DATA_VTD_S1,
591
+};
592
+
593
+/**
594
+ * enum iommu_hwpt_vtd_s1_invalidate_flags - Flags for Intel VT-d
595
+ * stage-1 cache invalidation
596
+ * @IOMMU_VTD_INV_FLAGS_LEAF: Indicates whether the invalidation applies
597
+ * to all-levels page structure cache or just
598
+ * the leaf PTE cache.
599
+ */
600
+enum iommu_hwpt_vtd_s1_invalidate_flags {
601
+    IOMMU_VTD_INV_FLAGS_LEAF = 1 << 0,
602
+};
603
+
604
+/**
605
+ * struct iommu_hwpt_vtd_s1_invalidate - Intel VT-d cache invalidation
606
+ * (IOMMU_HWPT_INVALIDATE_DATA_VTD_S1)
607
+ * @addr: The start address of the range to be invalidated. It needs to
608
+ * be 4KB aligned.
609
+ * @npages: Number of contiguous 4K pages to be invalidated.
610
+ * @flags: Combination of enum iommu_hwpt_vtd_s1_invalidate_flags
611
+ * @__reserved: Must be 0
612
+ *
613
+ * The Intel VT-d specific invalidation data for user-managed stage-1 cache
614
+ * invalidation in nested translation. Userspace uses this structure to
615
+ * tell the impacted cache scope after modifying the stage-1 page table.
616
+ *
617
+ * Invalidating all the caches related to the page table by setting @addr
618
+ * to be 0 and @npages to be U64_MAX.
619
+ *
620
+ * The device TLB will be invalidated automatically if ATS is enabled.
621
+ */
622
+struct iommu_hwpt_vtd_s1_invalidate {
623
+    __aligned_u64 addr;
624
+    __aligned_u64 npages;
625
+    __u32 flags;
626
+    __u32 __reserved;
627
+};
628
+
629
+/**
630
+ * struct iommu_hwpt_invalidate - ioctl(IOMMU_HWPT_INVALIDATE)
631
+ * @size: sizeof(struct iommu_hwpt_invalidate)
632
+ * @hwpt_id: ID of a nested HWPT for cache invalidation
633
+ * @data_uptr: User pointer to an array of driver-specific cache invalidation
634
+ * data.
635
+ * @data_type: One of enum iommu_hwpt_invalidate_data_type, defining the data
636
+ * type of all the entries in the invalidation request array. It
637
+ * should be a type supported by the hwpt pointed by @hwpt_id.
638
+ * @entry_len: Length (in bytes) of a request entry in the request array
639
+ * @entry_num: Input the number of cache invalidation requests in the array.
640
+ * Output the number of requests successfully handled by kernel.
641
+ * @__reserved: Must be 0.
642
+ *
643
+ * Invalidate the iommu cache for user-managed page table. Modifications on a
644
+ * user-managed page table should be followed by this operation to sync cache.
645
+ * Each ioctl can support one or more cache invalidation requests in the array
646
+ * that has a total size of @entry_len * @entry_num.
647
+ *
648
+ * An empty invalidation request array by setting @entry_num==0 is allowed, and
649
+ * @entry_len and @data_uptr would be ignored in this case. This can be used to
650
+ * check if the given @data_type is supported or not by kernel.
651
+ */
652
+struct iommu_hwpt_invalidate {
653
+    __u32 size;
654
+    __u32 hwpt_id;
655
+    __aligned_u64 data_uptr;
656
+    __u32 data_type;
657
+    __u32 entry_len;
658
+    __u32 entry_num;
659
+    __u32 __reserved;
660
+};
661
+#define IOMMU_HWPT_INVALIDATE _IO(IOMMUFD_TYPE, IOMMUFD_CMD_HWPT_INVALIDATE)
662
#endif
663
diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h
664
index XXXXXXX..XXXXXXX 100644
665
--- a/linux-headers/linux/kvm.h
666
+++ b/linux-headers/linux/kvm.h
667
@@ -XXX,XX +XXX,XX @@
668
669
#define KVM_API_VERSION 12
670
671
-/* *** Deprecated interfaces *** */
672
-
673
-#define KVM_TRC_SHIFT 16
674
-
675
-#define KVM_TRC_ENTRYEXIT (1 << KVM_TRC_SHIFT)
676
-#define KVM_TRC_HANDLER (1 << (KVM_TRC_SHIFT + 1))
677
-
678
-#define KVM_TRC_VMENTRY (KVM_TRC_ENTRYEXIT + 0x01)
679
-#define KVM_TRC_VMEXIT (KVM_TRC_ENTRYEXIT + 0x02)
680
-#define KVM_TRC_PAGE_FAULT (KVM_TRC_HANDLER + 0x01)
681
-
682
-#define KVM_TRC_HEAD_SIZE 12
683
-#define KVM_TRC_CYCLE_SIZE 8
684
-#define KVM_TRC_EXTRA_MAX 7
685
-
686
-#define KVM_TRC_INJ_VIRQ (KVM_TRC_HANDLER + 0x02)
687
-#define KVM_TRC_REDELIVER_EVT (KVM_TRC_HANDLER + 0x03)
688
-#define KVM_TRC_PEND_INTR (KVM_TRC_HANDLER + 0x04)
689
-#define KVM_TRC_IO_READ (KVM_TRC_HANDLER + 0x05)
690
-#define KVM_TRC_IO_WRITE (KVM_TRC_HANDLER + 0x06)
691
-#define KVM_TRC_CR_READ (KVM_TRC_HANDLER + 0x07)
692
-#define KVM_TRC_CR_WRITE (KVM_TRC_HANDLER + 0x08)
693
-#define KVM_TRC_DR_READ (KVM_TRC_HANDLER + 0x09)
694
-#define KVM_TRC_DR_WRITE (KVM_TRC_HANDLER + 0x0A)
695
-#define KVM_TRC_MSR_READ (KVM_TRC_HANDLER + 0x0B)
696
-#define KVM_TRC_MSR_WRITE (KVM_TRC_HANDLER + 0x0C)
697
-#define KVM_TRC_CPUID (KVM_TRC_HANDLER + 0x0D)
698
-#define KVM_TRC_INTR (KVM_TRC_HANDLER + 0x0E)
699
-#define KVM_TRC_NMI (KVM_TRC_HANDLER + 0x0F)
700
-#define KVM_TRC_VMMCALL (KVM_TRC_HANDLER + 0x10)
701
-#define KVM_TRC_HLT (KVM_TRC_HANDLER + 0x11)
702
-#define KVM_TRC_CLTS (KVM_TRC_HANDLER + 0x12)
703
-#define KVM_TRC_LMSW (KVM_TRC_HANDLER + 0x13)
704
-#define KVM_TRC_APIC_ACCESS (KVM_TRC_HANDLER + 0x14)
705
-#define KVM_TRC_TDP_FAULT (KVM_TRC_HANDLER + 0x15)
706
-#define KVM_TRC_GTLB_WRITE (KVM_TRC_HANDLER + 0x16)
707
-#define KVM_TRC_STLB_WRITE (KVM_TRC_HANDLER + 0x17)
708
-#define KVM_TRC_STLB_INVAL (KVM_TRC_HANDLER + 0x18)
709
-#define KVM_TRC_PPC_INSTR (KVM_TRC_HANDLER + 0x19)
710
-
711
-struct kvm_user_trace_setup {
712
-    __u32 buf_size;
713
-    __u32 buf_nr;
714
-};
715
-
716
-#define __KVM_DEPRECATED_MAIN_W_0x06 \
717
-    _IOW(KVMIO, 0x06, struct kvm_user_trace_setup)
718
-#define __KVM_DEPRECATED_MAIN_0x07 _IO(KVMIO, 0x07)
719
-#define __KVM_DEPRECATED_MAIN_0x08 _IO(KVMIO, 0x08)
720
-
721
-#define __KVM_DEPRECATED_VM_R_0x70 _IOR(KVMIO, 0x70, struct kvm_assigned_irq)
722
-
723
-struct kvm_breakpoint {
724
-    __u32 enabled;
725
-    __u32 padding;
726
-    __u64 address;
727
-};
728
-
729
-struct kvm_debug_guest {
730
-    __u32 enabled;
731
-    __u32 pad;
732
-    struct kvm_breakpoint breakpoints[4];
733
-    __u32 singlestep;
734
-};
735
-
736
-#define __KVM_DEPRECATED_VCPU_W_0x87 _IOW(KVMIO, 0x87, struct kvm_debug_guest)
737
-
738
-/* *** End of deprecated interfaces *** */
739
-
740
-
741
/* for KVM_SET_USER_MEMORY_REGION */
742
struct kvm_userspace_memory_region {
743
    __u32 slot;
744
@@ -XXX,XX +XXX,XX @@ struct kvm_userspace_memory_region {
745
    __u64 userspace_addr; /* start of the userspace allocated memory */
746
};
747
748
+/* for KVM_SET_USER_MEMORY_REGION2 */
749
+struct kvm_userspace_memory_region2 {
750
+    __u32 slot;
751
+    __u32 flags;
752
+    __u64 guest_phys_addr;
753
+    __u64 memory_size;
754
+    __u64 userspace_addr;
755
+    __u64 guest_memfd_offset;
756
+    __u32 guest_memfd;
757
+    __u32 pad1;
758
+    __u64 pad2[14];
759
+};
760
+
761
/*
762
* The bit 0 ~ bit 15 of kvm_userspace_memory_region::flags are visible for
763
* userspace, other bits are reserved for kvm internal use which are defined
764
@@ -XXX,XX +XXX,XX @@ struct kvm_userspace_memory_region {
765
*/
766
#define KVM_MEM_LOG_DIRTY_PAGES    (1UL << 0)
767
#define KVM_MEM_READONLY    (1UL << 1)
768
+#define KVM_MEM_GUEST_MEMFD    (1UL << 2)
769
770
/* for KVM_IRQ_LINE */
771
struct kvm_irq_level {
772
@@ -XXX,XX +XXX,XX @@ struct kvm_xen_exit {
773
#define KVM_EXIT_RISCV_CSR 36
774
#define KVM_EXIT_NOTIFY 37
775
#define KVM_EXIT_LOONGARCH_IOCSR 38
776
+#define KVM_EXIT_MEMORY_FAULT 39
777
778
/* For KVM_EXIT_INTERNAL_ERROR */
779
/* Emulate instruction failed. */
780
@@ -XXX,XX +XXX,XX @@ struct kvm_run {
781
#define KVM_NOTIFY_CONTEXT_INVALID    (1 << 0)
782
            __u32 flags;
783
        } notify;
784
+        /* KVM_EXIT_MEMORY_FAULT */
785
+        struct {
786
+#define KVM_MEMORY_EXIT_FLAG_PRIVATE    (1ULL << 3)
787
+            __u64 flags;
788
+            __u64 gpa;
789
+            __u64 size;
790
+        } memory_fault;
791
        /* Fix the size of the union. */
792
        char padding[256];
793
    };
794
@@ -XXX,XX +XXX,XX @@ struct kvm_ppc_resize_hpt {
795
*/
796
#define KVM_GET_VCPU_MMAP_SIZE _IO(KVMIO, 0x04) /* in bytes */
797
#define KVM_GET_SUPPORTED_CPUID _IOWR(KVMIO, 0x05, struct kvm_cpuid2)
798
-#define KVM_TRACE_ENABLE __KVM_DEPRECATED_MAIN_W_0x06
799
-#define KVM_TRACE_PAUSE __KVM_DEPRECATED_MAIN_0x07
800
-#define KVM_TRACE_DISABLE __KVM_DEPRECATED_MAIN_0x08
801
#define KVM_GET_EMULATED_CPUID     _IOWR(KVMIO, 0x09, struct kvm_cpuid2)
802
#define KVM_GET_MSR_FEATURE_INDEX_LIST _IOWR(KVMIO, 0x0a, struct kvm_msr_list)
803
804
@@ -XXX,XX +XXX,XX @@ struct kvm_ppc_resize_hpt {
805
#define KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE 228
806
#define KVM_CAP_ARM_SUPPORTED_BLOCK_SIZES 229
807
#define KVM_CAP_ARM_SUPPORTED_REG_MASK_RANGES 230
808
+#define KVM_CAP_USER_MEMORY2 231
809
+#define KVM_CAP_MEMORY_FAULT_INFO 232
810
+#define KVM_CAP_MEMORY_ATTRIBUTES 233
811
+#define KVM_CAP_GUEST_MEMFD 234
812
+#define KVM_CAP_VM_TYPES 235
813
814
#ifdef KVM_CAP_IRQ_ROUTING
815
816
@@ -XXX,XX +XXX,XX @@ struct kvm_x86_mce {
817
#define KVM_XEN_HVM_CONFIG_EVTCHN_2LEVEL    (1 << 4)
818
#define KVM_XEN_HVM_CONFIG_EVTCHN_SEND        (1 << 5)
819
#define KVM_XEN_HVM_CONFIG_RUNSTATE_UPDATE_FLAG    (1 << 6)
820
+#define KVM_XEN_HVM_CONFIG_PVCLOCK_TSC_UNSTABLE    (1 << 7)
821
822
struct kvm_xen_hvm_config {
823
    __u32 flags;
824
@@ -XXX,XX +XXX,XX @@ struct kvm_vfio_spapr_tce {
825
                    struct kvm_userspace_memory_region)
826
#define KVM_SET_TSS_ADDR _IO(KVMIO, 0x47)
827
#define KVM_SET_IDENTITY_MAP_ADDR _IOW(KVMIO, 0x48, __u64)
828
+#define KVM_SET_USER_MEMORY_REGION2 _IOW(KVMIO, 0x49, \
829
+                     struct kvm_userspace_memory_region2)
830
831
/* enable ucontrol for s390 */
832
struct kvm_s390_ucas_mapping {
833
@@ -XXX,XX +XXX,XX @@ struct kvm_s390_ucas_mapping {
834
            _IOW(KVMIO, 0x67, struct kvm_coalesced_mmio_zone)
835
#define KVM_UNREGISTER_COALESCED_MMIO \
836
            _IOW(KVMIO, 0x68, struct kvm_coalesced_mmio_zone)
837
-#define KVM_ASSIGN_PCI_DEVICE _IOR(KVMIO, 0x69, \
838
-                 struct kvm_assigned_pci_dev)
839
#define KVM_SET_GSI_ROUTING _IOW(KVMIO, 0x6a, struct kvm_irq_routing)
840
-/* deprecated, replaced by KVM_ASSIGN_DEV_IRQ */
841
-#define KVM_ASSIGN_IRQ __KVM_DEPRECATED_VM_R_0x70
842
-#define KVM_ASSIGN_DEV_IRQ _IOW(KVMIO, 0x70, struct kvm_assigned_irq)
843
#define KVM_REINJECT_CONTROL _IO(KVMIO, 0x71)
844
-#define KVM_DEASSIGN_PCI_DEVICE _IOW(KVMIO, 0x72, \
845
-                 struct kvm_assigned_pci_dev)
846
-#define KVM_ASSIGN_SET_MSIX_NR _IOW(KVMIO, 0x73, \
847
-                 struct kvm_assigned_msix_nr)
848
-#define KVM_ASSIGN_SET_MSIX_ENTRY _IOW(KVMIO, 0x74, \
849
-                 struct kvm_assigned_msix_entry)
850
-#define KVM_DEASSIGN_DEV_IRQ _IOW(KVMIO, 0x75, struct kvm_assigned_irq)
851
#define KVM_IRQFD _IOW(KVMIO, 0x76, struct kvm_irqfd)
852
#define KVM_CREATE_PIT2         _IOW(KVMIO, 0x77, struct kvm_pit_config)
853
#define KVM_SET_BOOT_CPU_ID _IO(KVMIO, 0x78)
854
@@ -XXX,XX +XXX,XX @@ struct kvm_s390_ucas_mapping {
855
* KVM_CAP_VM_TSC_CONTROL to set defaults for a VM */
856
#define KVM_SET_TSC_KHZ _IO(KVMIO, 0xa2)
857
#define KVM_GET_TSC_KHZ _IO(KVMIO, 0xa3)
858
-/* Available with KVM_CAP_PCI_2_3 */
859
-#define KVM_ASSIGN_SET_INTX_MASK _IOW(KVMIO, 0xa4, \
860
-                 struct kvm_assigned_pci_dev)
861
/* Available with KVM_CAP_SIGNAL_MSI */
862
#define KVM_SIGNAL_MSI _IOW(KVMIO, 0xa5, struct kvm_msi)
863
/* Available with KVM_CAP_PPC_GET_SMMU_INFO */
864
@@ -XXX,XX +XXX,XX @@ struct kvm_s390_ucas_mapping {
865
#define KVM_SET_SREGS _IOW(KVMIO, 0x84, struct kvm_sregs)
866
#define KVM_TRANSLATE _IOWR(KVMIO, 0x85, struct kvm_translation)
867
#define KVM_INTERRUPT _IOW(KVMIO, 0x86, struct kvm_interrupt)
868
-/* KVM_DEBUG_GUEST is no longer supported, use KVM_SET_GUEST_DEBUG instead */
869
-#define KVM_DEBUG_GUEST __KVM_DEPRECATED_VCPU_W_0x87
870
#define KVM_GET_MSRS _IOWR(KVMIO, 0x88, struct kvm_msrs)
871
#define KVM_SET_MSRS _IOW(KVMIO, 0x89, struct kvm_msrs)
872
#define KVM_SET_CPUID _IOW(KVMIO, 0x8a, struct kvm_cpuid)
873
@@ -XXX,XX +XXX,XX @@ struct kvm_s390_zpci_op {
874
/* flags for kvm_s390_zpci_op->u.reg_aen.flags */
875
#define KVM_S390_ZPCIOP_REGAEN_HOST (1 << 0)
876
877
+/* Available with KVM_CAP_MEMORY_ATTRIBUTES */
878
+#define KVM_SET_MEMORY_ATTRIBUTES _IOW(KVMIO, 0xd2, struct kvm_memory_attributes)
879
+
880
+struct kvm_memory_attributes {
881
+    __u64 address;
882
+    __u64 size;
883
+    __u64 attributes;
884
+    __u64 flags;
885
+};
886
+
887
+#define KVM_MEMORY_ATTRIBUTE_PRIVATE (1ULL << 3)
888
+
889
+#define KVM_CREATE_GUEST_MEMFD    _IOWR(KVMIO, 0xd4, struct kvm_create_guest_memfd)
890
+
891
+struct kvm_create_guest_memfd {
892
+    __u64 size;
893
+    __u64 flags;
894
+    __u64 reserved[6];
895
+};
896
+
897
#endif /* __LINUX_KVM_H */
898
diff --git a/linux-headers/linux/userfaultfd.h b/linux-headers/linux/userfaultfd.h
899
index XXXXXXX..XXXXXXX 100644
900
--- a/linux-headers/linux/userfaultfd.h
901
+++ b/linux-headers/linux/userfaultfd.h
902
@@ -XXX,XX +XXX,XX @@
903
             UFFD_FEATURE_WP_HUGETLBFS_SHMEM |    \
904
             UFFD_FEATURE_WP_UNPOPULATED |    \
905
             UFFD_FEATURE_POISON |        \
906
-             UFFD_FEATURE_WP_ASYNC)
907
+             UFFD_FEATURE_WP_ASYNC |        \
908
+             UFFD_FEATURE_MOVE)
909
#define UFFD_API_IOCTLS                \
910
    ((__u64)1 << _UFFDIO_REGISTER |        \
911
     (__u64)1 << _UFFDIO_UNREGISTER |    \
912
@@ -XXX,XX +XXX,XX @@
913
    ((__u64)1 << _UFFDIO_WAKE |        \
914
     (__u64)1 << _UFFDIO_COPY |        \
915
     (__u64)1 << _UFFDIO_ZEROPAGE |        \
916
+     (__u64)1 << _UFFDIO_MOVE |        \
917
     (__u64)1 << _UFFDIO_WRITEPROTECT |    \
918
     (__u64)1 << _UFFDIO_CONTINUE |        \
919
     (__u64)1 << _UFFDIO_POISON)
920
@@ -XXX,XX +XXX,XX @@
921
#define _UFFDIO_WAKE            (0x02)
922
#define _UFFDIO_COPY            (0x03)
923
#define _UFFDIO_ZEROPAGE        (0x04)
924
+#define _UFFDIO_MOVE            (0x05)
925
#define _UFFDIO_WRITEPROTECT        (0x06)
926
#define _UFFDIO_CONTINUE        (0x07)
927
#define _UFFDIO_POISON            (0x08)
928
@@ -XXX,XX +XXX,XX @@
929
                 struct uffdio_copy)
930
#define UFFDIO_ZEROPAGE        _IOWR(UFFDIO, _UFFDIO_ZEROPAGE,    \
931
                 struct uffdio_zeropage)
932
+#define UFFDIO_MOVE        _IOWR(UFFDIO, _UFFDIO_MOVE,    \
933
+                 struct uffdio_move)
934
#define UFFDIO_WRITEPROTECT    _IOWR(UFFDIO, _UFFDIO_WRITEPROTECT, \
935
                 struct uffdio_writeprotect)
936
#define UFFDIO_CONTINUE        _IOWR(UFFDIO, _UFFDIO_CONTINUE,    \
937
@@ -XXX,XX +XXX,XX @@ struct uffdio_api {
938
     * asynchronous mode is supported in which the write fault is
939
     * automatically resolved and write-protection is un-set.
940
     * It implies UFFD_FEATURE_WP_UNPOPULATED.
941
+     *
942
+     * UFFD_FEATURE_MOVE indicates that the kernel supports moving an
943
+     * existing page contents from userspace.
944
     */
945
#define UFFD_FEATURE_PAGEFAULT_FLAG_WP        (1<<0)
946
#define UFFD_FEATURE_EVENT_FORK            (1<<1)
947
@@ -XXX,XX +XXX,XX @@ struct uffdio_api {
948
#define UFFD_FEATURE_WP_UNPOPULATED        (1<<13)
949
#define UFFD_FEATURE_POISON            (1<<14)
950
#define UFFD_FEATURE_WP_ASYNC            (1<<15)
951
+#define UFFD_FEATURE_MOVE            (1<<16)
952
    __u64 features;
953
954
    __u64 ioctls;
955
@@ -XXX,XX +XXX,XX @@ struct uffdio_poison {
956
    __s64 updated;
957
};
958
959
+struct uffdio_move {
960
+    __u64 dst;
961
+    __u64 src;
962
+    __u64 len;
963
+    /*
964
+     * Especially if used to atomically remove memory from the
965
+     * address space the wake on the dst range is not needed.
966
+     */
967
+#define UFFDIO_MOVE_MODE_DONTWAKE        ((__u64)1<<0)
968
+#define UFFDIO_MOVE_MODE_ALLOW_SRC_HOLES    ((__u64)1<<1)
969
+    __u64 mode;
970
+    /*
971
+     * "move" is written by the ioctl and must be at the end: the
972
+     * copy_from_user will not read the last 8 bytes.
973
+     */
974
+    __s64 move;
975
+};
976
+
977
/*
978
* Flags for the userfaultfd(2) system call itself.
979
*/
980
diff --git a/linux-headers/linux/vfio.h b/linux-headers/linux/vfio.h
981
index XXXXXXX..XXXXXXX 100644
982
--- a/linux-headers/linux/vfio.h
983
+++ b/linux-headers/linux/vfio.h
984
@@ -XXX,XX +XXX,XX @@ enum vfio_device_mig_state {
985
    VFIO_DEVICE_STATE_RUNNING_P2P = 5,
986
    VFIO_DEVICE_STATE_PRE_COPY = 6,
987
    VFIO_DEVICE_STATE_PRE_COPY_P2P = 7,
988
+    VFIO_DEVICE_STATE_NR,
989
};
990
991
/**
992
--
993
2.44.0
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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