[v1] target/riscv: Support Zve32x and Zve64x extensions

[PATCH 0/5] target/riscv: Support Zve32x and Zve64x extensions

Jason Chien posted 5 patches 8 months, 3 weeks ago

Diff against v2 v3
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target/riscv/cpu.c                      |  4 +++
target/riscv/cpu_cfg.h                  |  2 ++
target/riscv/cpu_helper.c               |  2 +-
target/riscv/csr.c                      |  2 +-
target/riscv/gdbstub.c                  |  2 +-
target/riscv/insn_trans/trans_rvv.c.inc |  4 +--
target/riscv/tcg/tcg-cpu.c              | 33 ++++++++++++++-----------
7 files changed, 30 insertions(+), 19 deletions(-)

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[PATCH 0/5] target/riscv: Support Zve32x and Zve64x extensions

Posted by Jason Chien 8 months, 3 weeks ago

This patch series adds the support for Zve32x and Zvx64x and makes vector
registers visible in GDB if any of the V/Zve*/Zvk* extensions is enabled.

Jason Chien (5):
  target/riscv: Add support for Zve32x extension
  target/riscv: Expose Zve32x extension to users
  target/riscv: Add support for Zve64x extension
  target/riscv: Expose Zve64x extension to users
  target/riscv: Relax vector register check in RISCV gdbstub

 target/riscv/cpu.c                      |  4 +++
 target/riscv/cpu_cfg.h                  |  2 ++
 target/riscv/cpu_helper.c               |  2 +-
 target/riscv/csr.c                      |  2 +-
 target/riscv/gdbstub.c                  |  2 +-
 target/riscv/insn_trans/trans_rvv.c.inc |  4 +--
 target/riscv/tcg/tcg-cpu.c              | 33 ++++++++++++++-----------
 7 files changed, 30 insertions(+), 19 deletions(-)

-- 
2.43.2

Re: [PATCH 0/5] target/riscv: Support Zve32x and Zve64x extensions

Posted by Jason Chien 8 months, 1 week ago

Ping. Can anyone review the patches please?

Jason Chien <jason.chien@sifive.com> 於 2024年3月7日 週四 上午1:09寫道：

> This patch series adds the support for Zve32x and Zvx64x and makes vector
> registers visible in GDB if any of the V/Zve*/Zvk* extensions is enabled.
>
> Jason Chien (5):
>   target/riscv: Add support for Zve32x extension
>   target/riscv: Expose Zve32x extension to users
>   target/riscv: Add support for Zve64x extension
>   target/riscv: Expose Zve64x extension to users
>   target/riscv: Relax vector register check in RISCV gdbstub
>
>  target/riscv/cpu.c                      |  4 +++
>  target/riscv/cpu_cfg.h                  |  2 ++
>  target/riscv/cpu_helper.c               |  2 +-
>  target/riscv/csr.c                      |  2 +-
>  target/riscv/gdbstub.c                  |  2 +-
>  target/riscv/insn_trans/trans_rvv.c.inc |  4 +--
>  target/riscv/tcg/tcg-cpu.c              | 33 ++++++++++++++-----------
>  7 files changed, 30 insertions(+), 19 deletions(-)
>
> --
> 2.43.2
>
>