[v1] target/hppa: Fix some wide mode displacements

[PATCH 3/3] target/hppa: Fix assemble_12a insns for wide mode

Posted by Richard Henderson 8 months, 4 weeks ago

Reported-by: Sven Schnelle <svens@stackframe.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/hppa/insns.decode | 27 ++++++++++++++++-----------
 target/hppa/translate.c  | 17 +++++++++++++++++
 2 files changed, 33 insertions(+), 11 deletions(-)

diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode
index 9c6f92444c..5412ff9836 100644
--- a/target/hppa/insns.decode
+++ b/target/hppa/insns.decode
@@ -26,7 +26,7 @@
 
 %assemble_11a   4:12 0:1             !function=expand_11a
 %assemble_12    0:s1 2:1 3:10        !function=expand_shl2
-%assemble_12a   0:s1 3:11            !function=expand_shl2
+%assemble_12a   3:13 0:1             !function=expand_12a
 %assemble_16    0:16                 !function=expand_16
 %assemble_17    0:s1 16:5 2:1 3:10   !function=expand_shl2
 %assemble_22    0:s1 16:10 2:1 3:10  !function=expand_shl2
@@ -314,8 +314,9 @@ fstd            001011 ..... ..... .. . 1 -- 100 0 . .....      @fldstdi
 @ldstim14m      ...... b:5 t:5 ................          \
                 &ldst sp=%assemble_sp disp=%assemble_16  \
                 x=0 scale=0 m=%neg_to_m
-@ldstim12m      ...... b:5 t:5 sp:2 ..............      \
-                &ldst disp=%assemble_12a x=0 scale=0 m=%pos_to_m
+@ldstim12m      ...... b:5 t:5 ................          \
+                &ldst sp=%assemble_sp disp=%assemble_12a \
+                x=0 scale=0 m=%pos_to_m
 
 # LDB, LDH, LDW, LDWM
 ld              010000 ..... ..... .. ..............    @ldstim14  size=0
@@ -331,15 +332,19 @@ st              011010 ..... ..... .. ..............    @ldstim14  size=2
 st              011011 ..... ..... .. ..............    @ldstim14m size=2
 st              011111 ..... ..... .. ...........10.    @ldstim12m size=2
 
-fldw            010110 b:5 ..... sp:2 ..............    \
-                &ldst disp=%assemble_12a t=%rm64 m=%a_to_m x=0 scale=0 size=2
-fldw            010111 b:5 ..... sp:2 ...........0..    \
-                &ldst disp=%assemble_12a t=%rm64 m=0 x=0 scale=0 size=2
+fldw            010110 b:5 ..... ................        \
+                &ldst disp=%assemble_12a sp=%assemble_sp \
+                t=%rm64 m=%a_to_m x=0 scale=0 size=2
+fldw            010111 b:5 ..... .............0..        \
+                &ldst disp=%assemble_12a sp=%assemble_sp \
+                t=%rm64 m=0 x=0 scale=0 size=2
 
-fstw            011110 b:5 ..... sp:2 ..............    \
-                &ldst disp=%assemble_12a t=%rm64 m=%a_to_m x=0 scale=0 size=2
-fstw            011111 b:5 ..... sp:2 ...........0..    \
-                &ldst disp=%assemble_12a t=%rm64 m=0 x=0 scale=0 size=2
+fstw            011110 b:5 ..... ................        \
+                &ldst disp=%assemble_12a sp=%assemble_sp \
+                t=%rm64 m=%a_to_m x=0 scale=0 size=2
+fstw            011111 b:5 ..... .............0..        \
+                &ldst disp=%assemble_12a sp=%assemble_sp \
+                t=%rm64 m=0 x=0 scale=0 size=2
 
 ld              010100 ..... ..... .. ............0.    @ldstim11
 fldd            010100 ..... ..... .. ............1.    @ldstim11
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 6dcc74e681..1ef266c403 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -155,6 +155,23 @@ static int expand_11a(DisasContext *ctx, int val)
     return i;
 }
 
+/* Expander for assemble_16a(s,im11a,i). */
+static int expand_12a(DisasContext *ctx, int val)
+{
+    /*
+     * @val is bit 0 and bits [3:15].
+     * Swizzle thing around depending on PSW.W.
+     */
+    int im11a = extract32(val, 1, 11);
+    int sp = extract32(val, 12, 2);
+    int i = (-(val & 1) << 13) | (im11a << 2);
+
+    if (ctx->tb_flags & PSW_W) {
+        i ^= sp << 13;
+    }
+    return i;
+}
+
 /* Expander for assemble_16(s,im14). */
 static int expand_16(DisasContext *ctx, int val)
 {
-- 
2.34.1

Re: [PATCH 3/3] target/hppa: Fix assemble_12a insns for wide mode

Posted by Helge Deller 8 months, 3 weeks ago

On 3/3/24 03:19, Richard Henderson wrote:
> Reported-by: Sven Schnelle <svens@stackframe.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Tested-by: Helge Deller <deller@gmx.de>

> ---
>   target/hppa/insns.decode | 27 ++++++++++++++++-----------
>   target/hppa/translate.c  | 17 +++++++++++++++++
>   2 files changed, 33 insertions(+), 11 deletions(-)
>
> diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode
> index 9c6f92444c..5412ff9836 100644
> --- a/target/hppa/insns.decode
> +++ b/target/hppa/insns.decode
> @@ -26,7 +26,7 @@
>
>   %assemble_11a   4:12 0:1             !function=expand_11a
>   %assemble_12    0:s1 2:1 3:10        !function=expand_shl2
> -%assemble_12a   0:s1 3:11            !function=expand_shl2
> +%assemble_12a   3:13 0:1             !function=expand_12a
>   %assemble_16    0:16                 !function=expand_16
>   %assemble_17    0:s1 16:5 2:1 3:10   !function=expand_shl2
>   %assemble_22    0:s1 16:10 2:1 3:10  !function=expand_shl2
> @@ -314,8 +314,9 @@ fstd            001011 ..... ..... .. . 1 -- 100 0 . .....      @fldstdi
>   @ldstim14m      ...... b:5 t:5 ................          \
>                   &ldst sp=%assemble_sp disp=%assemble_16  \
>                   x=0 scale=0 m=%neg_to_m
> -@ldstim12m      ...... b:5 t:5 sp:2 ..............      \
> -                &ldst disp=%assemble_12a x=0 scale=0 m=%pos_to_m
> +@ldstim12m      ...... b:5 t:5 ................          \
> +                &ldst sp=%assemble_sp disp=%assemble_12a \
> +                x=0 scale=0 m=%pos_to_m
>
>   # LDB, LDH, LDW, LDWM
>   ld              010000 ..... ..... .. ..............    @ldstim14  size=0
> @@ -331,15 +332,19 @@ st              011010 ..... ..... .. ..............    @ldstim14  size=2
>   st              011011 ..... ..... .. ..............    @ldstim14m size=2
>   st              011111 ..... ..... .. ...........10.    @ldstim12m size=2
>
> -fldw            010110 b:5 ..... sp:2 ..............    \
> -                &ldst disp=%assemble_12a t=%rm64 m=%a_to_m x=0 scale=0 size=2
> -fldw            010111 b:5 ..... sp:2 ...........0..    \
> -                &ldst disp=%assemble_12a t=%rm64 m=0 x=0 scale=0 size=2
> +fldw            010110 b:5 ..... ................        \
> +                &ldst disp=%assemble_12a sp=%assemble_sp \
> +                t=%rm64 m=%a_to_m x=0 scale=0 size=2
> +fldw            010111 b:5 ..... .............0..        \
> +                &ldst disp=%assemble_12a sp=%assemble_sp \
> +                t=%rm64 m=0 x=0 scale=0 size=2
>
> -fstw            011110 b:5 ..... sp:2 ..............    \
> -                &ldst disp=%assemble_12a t=%rm64 m=%a_to_m x=0 scale=0 size=2
> -fstw            011111 b:5 ..... sp:2 ...........0..    \
> -                &ldst disp=%assemble_12a t=%rm64 m=0 x=0 scale=0 size=2
> +fstw            011110 b:5 ..... ................        \
> +                &ldst disp=%assemble_12a sp=%assemble_sp \
> +                t=%rm64 m=%a_to_m x=0 scale=0 size=2
> +fstw            011111 b:5 ..... .............0..        \
> +                &ldst disp=%assemble_12a sp=%assemble_sp \
> +                t=%rm64 m=0 x=0 scale=0 size=2
>
>   ld              010100 ..... ..... .. ............0.    @ldstim11
>   fldd            010100 ..... ..... .. ............1.    @ldstim11
> diff --git a/target/hppa/translate.c b/target/hppa/translate.c
> index 6dcc74e681..1ef266c403 100644
> --- a/target/hppa/translate.c
> +++ b/target/hppa/translate.c
> @@ -155,6 +155,23 @@ static int expand_11a(DisasContext *ctx, int val)
>       return i;
>   }
>
> +/* Expander for assemble_16a(s,im11a,i). */
> +static int expand_12a(DisasContext *ctx, int val)
> +{
> +    /*
> +     * @val is bit 0 and bits [3:15].
> +     * Swizzle thing around depending on PSW.W.
> +     */
> +    int im11a = extract32(val, 1, 11);
> +    int sp = extract32(val, 12, 2);
> +    int i = (-(val & 1) << 13) | (im11a << 2);
> +
> +    if (ctx->tb_flags & PSW_W) {
> +        i ^= sp << 13;
> +    }
> +    return i;
> +}
> +
>   /* Expander for assemble_16(s,im14). */
>   static int expand_16(DisasContext *ctx, int val)
>   {

[PATCH 1/3] target/hppa: Fix assemble_16 insns for wide mode
[PATCH 2/3] target/hppa: Fix assemble_11a insns for wide mode
[PATCH 3/3] target/hppa: Fix assemble_12a insns for wide mode