During transactions, these get added to memory attributes at the same
time other attributes are added.

Similar to the requester ID, these are added on PTWs, GPCs, and
descriptor grabbing as well.

Signed-off-by: Joe Komlodi <komlodi@google.com>
---
 target/arm/cpu.c | 2 ++
 target/arm/cpu.h | 2 ++
 target/arm/ptw.c | 4 ++++
 3 files changed, 8 insertions(+)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 9cfbba10c2..dcd2c16c2e 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2404,6 +2404,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
 
     /* For MemTxAttrs. */
     env->requester_id = cpu->requester_id;
+    env->memattr_user_defined = cpu->memattr_user_defined;
 
     qemu_init_vcpu(cs);
     cpu_reset(cs);
@@ -2443,6 +2444,7 @@ static Property arm_cpu_properties[] = {
     DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID),
     DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1),
     DEFINE_PROP_UINT16("requester-id", ARMCPU, requester_id, 0),
+    DEFINE_PROP_UINT8("memattr-user-defined", ARMCPU, memattr_user_defined, 0),
     DEFINE_PROP_END_OF_LIST()
 };
 
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 5fc572e077..499a5b25c7 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -777,6 +777,7 @@ typedef struct CPUArchState {
 
     /* For MemTxAttrs. */
     uint16_t requester_id;
+    uint8_t memattr_user_defined;
 } CPUARMState;
 
 static inline void set_feature(CPUARMState *env, int feature)
@@ -1097,6 +1098,7 @@ struct ArchCPU {
 
     /* Requester ID, used in MemTxAttrs. */
     uint16_t requester_id;
+    uint8_t memattr_user_defined;
 };
 
 typedef struct ARMCPUInfo {
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 148af3a000..b2af3d9052 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -288,6 +288,7 @@ static bool granule_protection_check(CPUARMState *env, uint64_t paddress,
         .secure = true,
         .space = ARMSS_Root,
         .requester_id = env->requester_id,
+        .user_defined = env->memattr_user_defined,
     };
     ARMCPU *cpu = env_archcpu(env);
     uint64_t gpccr = env->cp15.gpccr_el3;
@@ -640,6 +641,7 @@ static uint32_t arm_ldl_ptw(CPUARMState *env, S1Translate *ptw,
             .space = ptw->out_space,
             .secure = arm_space_is_secure(ptw->out_space),
             .requester_id = env->requester_id,
+            .user_defined = env->memattr_user_defined,
         };
         AddressSpace *as = arm_addressspace(cs, attrs);
         MemTxResult result = MEMTX_OK;
@@ -687,6 +689,7 @@ static uint64_t arm_ldq_ptw(CPUARMState *env, S1Translate *ptw,
             .space = ptw->out_space,
             .secure = arm_space_is_secure(ptw->out_space),
             .requester_id = env->requester_id,
+            .user_defined = env->memattr_user_defined,
         };
         AddressSpace *as = arm_addressspace(cs, attrs);
         MemTxResult result = MEMTX_OK;
@@ -3310,6 +3313,7 @@ static bool get_phys_addr_nogpc(CPUARMState *env, S1Translate *ptw,
     result->f.attrs.secure = arm_space_is_secure(ptw->in_space);
 
     result->f.attrs.requester_id = env->requester_id;
+    result->f.attrs.user_defined = env->memattr_user_defined;
 
     switch (mmu_idx) {
     case ARMMMUIdx_Phys_S:
-- 
2.44.0.rc0.258.g7320e95886-goog