The following changes since commit dccbaf0cc0f1744ffd7562a3dc60e4fc99fd9d44:

Merge tag 'hw-misc-20240227' of https://github.com/philmd/qemu into staging (2024-02-27 10:11:07 +0000)

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20240227

for you to fetch changes up to 48f471ab5450ef8981298e39583118729f6b2aa2:

docs/system/arm: Add RPi4B to raspi.rst (2024-02-27 13:01:43 +0000)

* Handle atomic updates of page tables entries in MMIO during PTW

* Advertise Cortex-A53 erratum #843419 fix via REVIDR

* MAINTAINERS: Cover hw/ide/ahci-allwinner.c with AllWinner A10 machine

* misc: m48t59: replace qemu_system_reset_request() call with watchdog_perform_action()

* misc: pxa2xx_timer: replace qemu_system_reset_request() call with watchdog_perform_action()

* xlnx-versal-ospi: disable reentrancy detection for iomem_dac

* sbsa-ref: Simplify init since PCIe is always enabled

* stm32l4x5: Use TYPE_OR_IRQ when connecting STM32L4x5 EXTI fan-in IRQs

* pl031: Update last RTCLR value on write in case it's read back

* block: m25p80: Add support of mt35xu02gbba

* xlnx-versal-virt: Add machine property ospi-flash

* reset: refactor system reset to be three-phase aware

* new board model raspi4b

Abhiram Tilak (2):

misc: m48t59: replace qemu_system_reset_request() call with watchdog_perform_action()

misc: pxa2xx_timer: replace qemu_system_reset_request() call with watchdog_perform_action()

Ard Biesheuvel (1):

target/arm: Advertise Cortex-A53 erratum #843419 fix via REVIDR

Inès Varhol (2):

hw/arm: Use TYPE_OR_IRQ when connecting STM32L4x5 EXTI fan-in IRQs

tests/qtest: Check that EXTI fan-in irqs are correctly connected

Jessica Clarke (1):

pl031: Update last RTCLR value on write in case it's read back

Jonathan Cameron (1):

arm/ptw: Handle atomic updates of page tables entries in MMIO during PTW.

Add the usual boilerplate license/copyright comment to reset.h (using

the text from reset.c), and document the existing functions.

Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>

Message-id: 20240220160622.114437-6-peter.maydell@linaro.org

include/sysemu/reset.h | 79 ++++++++++++++++++++++++++++++++++++++++++

1 file changed, 79 insertions(+)

diff --git a/include/sysemu/reset.h b/include/sysemu/reset.h

--- a/include/sysemu/reset.h

+++ b/include/sysemu/reset.h

@@ -XXX,XX +XXX,XX @@

+/*

+ * Reset handlers.

+ *

+ * Copyright (c) 2003-2008 Fabrice Bellard

+ * Copyright (c) 2016 Red Hat, Inc.

+ * Copyright (c) 2024 Linaro, Ltd.

+ *

+ * Permission is hereby granted, free of charge, to any person obtaining a copy

+ * of this software and associated documentation files (the "Software"), to deal

+ * in the Software without restriction, including without limitation the rights

+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

+ * copies of the Software, and to permit persons to whom the Software is

+ * furnished to do so, subject to the following conditions:

+ *

+ * The above copyright notice and this permission notice shall be included in

+ * all copies or substantial portions of the Software.

+ *

+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

+ * THE SOFTWARE.

+ */

#ifndef QEMU_SYSEMU_RESET_H

#define QEMU_SYSEMU_RESET_H

@@ -XXX,XX +XXX,XX @@

typedef void QEMUResetHandler(void *opaque);

+/**

+ * qemu_register_reset: Register a callback for system reset

+ * @func: function to call

+ * @opaque: opaque data to pass to @func

+ *

+ * Register @func on the list of functions which are called when the

+ * entire system is reset. The functions are called in the order in

+ * which they are registered.

+ *

+ * In general this function should not be used in new code where possible;

+ * for instance, device model reset is better accomplished using the

+ * methods on DeviceState.

+ *

+ * It is not permitted to register or unregister reset functions from

+ * within the @func callback.

+ *

+ * We assume that the caller holds the BQL.

+ */

void qemu_register_reset(QEMUResetHandler *func, void *opaque);

+/**

+ * qemu_register_reset_nosnapshotload: Register a callback for system reset

+ * @func: function to call

+ * @opaque: opaque data to pass to @func

+ *

+ * This is the same as qemu_register_reset(), except that @func is

+ * not called if the reason that the system is being reset is to

+ * put it into a clean state prior to loading a snapshot (i.e. for

+ * SHUTDOWN_CAUSE_SNAPSHOT_LOAD).

+ */

void qemu_register_reset_nosnapshotload(QEMUResetHandler *func, void *opaque);

+/**

+ * qemu_unregister_reset: Unregister a system reset callback

+ * @func: function registered with qemu_register_reset()

+ * @opaque: the same opaque data that was passed to qemu_register_reset()

+ *

+ * Undo the effects of a qemu_register_reset(). The @func and @opaque

+ * must both match the arguments originally used with qemu_register_reset().

+ *

+ * We assume that the caller holds the BQL.

+ */

void qemu_unregister_reset(QEMUResetHandler *func, void *opaque);

+/**

+ * qemu_devices_reset: Perform a complete system reset

+ * @reason: reason for the reset

+ *

+ * This function performs the low-level work needed to do a complete reset

+ * of the system (calling all the callbacks registered with

+ * qemu_register_reset()). It should only be called by the code in a

+ * MachineClass reset method.

+ *

+ * If you want to trigger a system reset from, for instance, a device

+ * model, don't use this function. Use qemu_system_reset_request().

+ */

void qemu_devices_reset(ShutdownCause reason);

Implement a ResetContainer. This is a subclass of Object, and it

implements the Resettable interface. The container holds a list of

arbitrary other objects which implement Resettable, and when the

container is reset, all the objects it contains are also reset.

This will allow us to have a 3-phase-reset equivalent of the old

qemu_register_reset() API: we will have a single "simulation reset"

top level ResetContainer, and objects in it are the equivalent of the

old QEMUResetHandler functions.

The qemu_register_reset() API manages its list of callbacks using a

QTAILQ, but here we use a GPtrArray for our list of Resettable

children: we expect the "remove" operation (which will need to do an

iteration through the list) to be fairly uncommon, and we get simpler

code with fewer memory allocations.

Since there is currently no listed owner in MAINTAINERS for the

existing reset-related source files, create a new section for

them, and add these new files there also.

Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>

Message-id: 20240220160622.114437-7-peter.maydell@linaro.org

Reviewed-by: Zhao Liu <zhao1.liu@intel.com>

MAINTAINERS | 10 +++++

include/hw/core/resetcontainer.h | 48 ++++++++++++++++++++

hw/core/resetcontainer.c | 77 ++++++++++++++++++++++++++++++++

hw/core/meson.build | 1 +

4 files changed, 136 insertions(+)

create mode 100644 include/hw/core/resetcontainer.h

create mode 100644 hw/core/resetcontainer.c

diff --git a/MAINTAINERS b/MAINTAINERS

--- a/MAINTAINERS

+++ b/MAINTAINERS

@@ -XXX,XX +XXX,XX @@ F: hw/core/clock-vmstate.c

F: hw/core/qdev-clock.c

F: docs/devel/clocks.rst

+Reset framework

+M: Peter Maydell <peter.maydell@linaro.org>

+S: Maintained

+F: include/hw/resettable.h

+F: include/hw/core/resetcontainer.h

+F: include/sysemu/reset.h

+F: hw/core/reset.c

+F: hw/core/resettable.c

+F: hw/core/resetcontainer.c

+

Usermode Emulation

------------------

Overall usermode emulation

diff --git a/include/hw/core/resetcontainer.h b/include/hw/core/resetcontainer.h

new file mode 100644

--- /dev/null

+++ b/include/hw/core/resetcontainer.h

+/*

+ * Reset container

+ *

+ * Copyright (c) 2024 Linaro, Ltd

+ *

+ * This work is licensed under the terms of the GNU GPL, version 2 or later.

+ * See the COPYING file in the top-level directory.

+ */

+

+#ifndef HW_RESETCONTAINER_H

+#define HW_RESETCONTAINER_H

+

+/*

+ * The "reset container" is an object which implements the Resettable

+ * interface. It contains a list of arbitrary other objects which also

+ * implement Resettable. Resetting the reset container resets all the

+ * objects in it.

+ */

+

+#include "qom/object.h"

+

+#define TYPE_RESETTABLE_CONTAINER "resettable-container"

+OBJECT_DECLARE_TYPE(ResettableContainer, ResettableContainerClass, RESETTABLE_CONTAINER)

+

+/**

+ * resettable_container_add: Add a resettable object to the container

+ * @rc: container

+ * @obj: object to add to the container

+ *

+ * Add @obj to the ResettableContainer @rc. @obj must implement the

+ * Resettable interface.

+ *

+ * When @rc is reset, it will reset every object that has been added

+ * to it, in the order they were added.

+ */

+void resettable_container_add(ResettableContainer *rc, Object *obj);

+

+/**

+ * resettable_container_remove: Remove an object from the container

+ * @rc: container

+ * @obj: object to remove from the container

+ *

+ * Remove @obj from the ResettableContainer @rc. @obj must have been

+ * previously added to this container.

+ */

+void resettable_container_remove(ResettableContainer *rc, Object *obj);

+

+#endif

diff --git a/hw/core/resetcontainer.c b/hw/core/resetcontainer.c

new file mode 100644

index XXXXXXX..XXXXXXX

--- /dev/null

+++ b/hw/core/resetcontainer.c

@@ -XXX,XX +XXX,XX @@

+/*

+ * Reset container

+ *

+ * Copyright (c) 2024 Linaro, Ltd

+ *

+ * This work is licensed under the terms of the GNU GPL, version 2 or later.

+ * See the COPYING file in the top-level directory.

+ */

+

+/*

+ * The "reset container" is an object which implements the Resettable

+ * interface. It contains a list of arbitrary other objects which also

+ * implement Resettable. Resetting the reset container resets all the

+ * objects in it.

+ */

+

+#include "qemu/osdep.h"

+#include "hw/resettable.h"

+#include "hw/core/resetcontainer.h"

+

+struct ResettableContainer {

+ Object parent;

+ ResettableState reset_state;

+ GPtrArray *children;

+};

+

+OBJECT_DEFINE_SIMPLE_TYPE_WITH_INTERFACES(ResettableContainer, resettable_container, RESETTABLE_CONTAINER, OBJECT, { TYPE_RESETTABLE_INTERFACE }, { })

+

+void resettable_container_add(ResettableContainer *rc, Object *obj)

+{

+ INTERFACE_CHECK(void, obj, TYPE_RESETTABLE_INTERFACE);

+ g_ptr_array_add(rc->children, obj);

+}

+

+void resettable_container_remove(ResettableContainer *rc, Object *obj)

+{

+ g_ptr_array_remove(rc->children, obj);

+}

+

+static ResettableState *resettable_container_get_state(Object *obj)

+{

+ ResettableContainer *rc = RESETTABLE_CONTAINER(obj);

+ return &rc->reset_state;

+}

+

+static void resettable_container_child_foreach(Object *obj,

+ ResettableChildCallback cb,

+ void *opaque, ResetType type)

+{

+ ResettableContainer *rc = RESETTABLE_CONTAINER(obj);

+ unsigned int len = rc->children->len;

+

+ for (unsigned int i = 0; i < len; i++) {

+ cb(g_ptr_array_index(rc->children, i), opaque, type);

+ /* Detect callbacks trying to unregister themselves */

+ assert(len == rc->children->len);

+ }

+}

+

+static void resettable_container_init(Object *obj)

+{

+ ResettableContainer *rc = RESETTABLE_CONTAINER(obj);

+

+ rc->children = g_ptr_array_new();

+}

+

+static void resettable_container_finalize(Object *obj)

+{

+}

+

+static void resettable_container_class_init(ObjectClass *klass, void *data)

+{

+ ResettableClass *rc = RESETTABLE_CLASS(klass);

+

+ rc->get_state = resettable_container_get_state;

+ rc->child_foreach = resettable_container_child_foreach;

+}

diff --git a/hw/core/meson.build b/hw/core/meson.build

index XXXXXXX..XXXXXXX 100644

--- a/hw/core/meson.build

+++ b/hw/core/meson.build

@@ -XXX,XX +XXX,XX @@ hwcore_ss.add(files(

'qdev-properties.c',

'qdev.c',

'reset.c',

+ 'resetcontainer.c',

'resettable.c',

'vmstate-if.c',

# irq.c needed for qdev GPIO handling:

From: Sergey Kambalin <serg.oker@gmail.com>

docs/system/arm/raspi.rst | 12 +++++++-----

1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/docs/system/arm/raspi.rst b/docs/system/arm/raspi.rst

--- a/docs/system/arm/raspi.rst

+++ b/docs/system/arm/raspi.rst

@@ -XXX,XX +XXX,XX @@

-Raspberry Pi boards (``raspi0``, ``raspi1ap``, ``raspi2b``, ``raspi3ap``, ``raspi3b``)

-======================================================================================

+Raspberry Pi boards (``raspi0``, ``raspi1ap``, ``raspi2b``, ``raspi3ap``, ``raspi3b``, ``raspi4b``)

+===================================================================================================

QEMU provides models of the following Raspberry Pi boards:

@@ -XXX,XX +XXX,XX @@ QEMU provides models of the following Raspberry Pi boards:

Cortex-A53 (4 cores), 512 MiB of RAM

``raspi3b``

Cortex-A53 (4 cores), 1 GiB of RAM

+``raspi4b``

+ Cortex-A72 (4 cores), 2 GiB of RAM

Implemented devices

-------------------

- * ARM1176JZF-S, Cortex-A7 or Cortex-A53 CPU

+ * ARM1176JZF-S, Cortex-A7, Cortex-A53 or Cortex-A72 CPU

* Interrupt controller

* DMA controller

* Clock and reset controller (CPRMAN)

@@ -XXX,XX +XXX,XX @@ Implemented devices

* VideoCore firmware (property)

* Peripheral SPI controller (SPI)

Missing devices

---------------

* Analog to Digital Converter (ADC)

* Pulse Width Modulation (PWM)

+ * PCIE Root Port (raspi4b)

+ * GENET Ethernet Controller (raspi4b)

From: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

There is no point in checking do we have PCIe if first thing after check

is adding PCIe card without checking.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Message-id: 20240215153311.186772-1-marcin.juszkiewicz@linaro.org

hw/arm/sbsa-ref.c | 5 ++---

1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c

--- a/hw/arm/sbsa-ref.c

+++ b/hw/arm/sbsa-ref.c

@@ -XXX,XX +XXX,XX @@ static void create_pcie(SBSAMachineState *sms)

pci = PCI_HOST_BRIDGE(dev);

- if (pci->bus) {

- pci_init_nic_devices(pci->bus, mc->default_nic);

- }

+

+ pci_init_nic_devices(pci->bus, mc->default_nic);

pci_create_simple(pci->bus, -1, "bochs-display");

From: Inès Varhol <ines.varhol@telecom-paris.fr>

Fixes: 52671f69f7a4 ("[PATCH v8 0/3] Add device STM32L4x5 EXTI")

Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>

Message-id: 20240220184145.106107-2-ines.varhol@telecom-paris.fr

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

include/hw/arm/stm32l4x5_soc.h | 4 ++

hw/arm/stm32l4x5_soc.c | 80 +++++++++++++++++++++++++++++-----

2 files changed, 74 insertions(+), 10 deletions(-)

diff --git a/include/hw/arm/stm32l4x5_soc.h b/include/hw/arm/stm32l4x5_soc.h

--- a/include/hw/arm/stm32l4x5_soc.h

+++ b/include/hw/arm/stm32l4x5_soc.h

@@ -XXX,XX +XXX,XX @@

#include "exec/memory.h"

#include "hw/arm/armv7m.h"

+#include "hw/or-irq.h"

#include "hw/misc/stm32l4x5_syscfg.h"

#include "hw/misc/stm32l4x5_exti.h"

#include "qom/object.h"

@@ -XXX,XX +XXX,XX @@

#define TYPE_STM32L4X5XG_SOC "stm32l4x5xg-soc"

OBJECT_DECLARE_TYPE(Stm32l4x5SocState, Stm32l4x5SocClass, STM32L4X5_SOC)

+#define NUM_EXTI_OR_GATES 4

+

struct Stm32l4x5SocState {

SysBusDevice parent_obj;

ARMv7MState armv7m;

Stm32l4x5ExtiState exti;

+ OrIRQState exti_or_gates[NUM_EXTI_OR_GATES];

Stm32l4x5SyscfgState syscfg;

MemoryRegion sram1;

diff --git a/hw/arm/stm32l4x5_soc.c b/hw/arm/stm32l4x5_soc.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/stm32l4x5_soc.c

+++ b/hw/arm/stm32l4x5_soc.c

@@ -XXX,XX +XXX,XX @@

#include "qapi/error.h"

#include "exec/address-spaces.h"

#include "sysemu/sysemu.h"

+#include "hw/or-irq.h"

#include "hw/arm/stm32l4x5_soc.h"

#include "hw/qdev-clock.h"

#include "hw/misc/unimp.h"

@@ -XXX,XX +XXX,XX @@

#define NUM_EXTI_IRQ 40

/* Match exti line connections with their CPU IRQ number */

/* See Vector Table (Reference Manual p.396) */

+/*

+ * Some IRQs are connected to the same CPU IRQ (denoted by -1)

+ * and require an intermediary OR gate to function correctly.

+ */

static const int exti_irq[NUM_EXTI_IRQ] = {

6, /* GPIO[0] */

7, /* GPIO[1] */

8, /* GPIO[2] */

9, /* GPIO[3] */

10, /* GPIO[4] */

- 23, 23, 23, 23, 23, /* GPIO[5..9] */

- 40, 40, 40, 40, 40, 40, /* GPIO[10..15] */

- 1, /* PVD */

+ -1, -1, -1, -1, -1, /* GPIO[5..9] OR gate 23 */

+ -1, -1, -1, -1, -1, -1, /* GPIO[10..15] OR gate 40 */

+ -1, /* PVD OR gate 1 */

67, /* OTG_FS_WKUP, Direct */

41, /* RTC_ALARM */

2, /* RTC_TAMP_STAMP2/CSS_LSE */

3, /* RTC wakeup timer */

- 63, /* COMP1 */

- 63, /* COMP2 */

+ -1, -1, /* COMP[1..2] OR gate 63 */

31, /* I2C1 wakeup, Direct */

33, /* I2C2 wakeup, Direct */

72, /* I2C3 wakeup, Direct */

@@ -XXX,XX +XXX,XX @@ static const int exti_irq[NUM_EXTI_IRQ] = {

65, /* LPTIM1, Direct */

66, /* LPTIM2, Direct */

76, /* SWPMI1 wakeup, Direct */

- 1, /* PVM1 wakeup */

- 1, /* PVM2 wakeup */

- 1, /* PVM3 wakeup */

- 1, /* PVM4 wakeup */

+ -1, -1, -1, -1, /* PVM[1..4] OR gate 1 */

78 /* LCD wakeup, Direct */

};

+static const int exti_or_gates_out[NUM_EXTI_OR_GATES] = {

+ 23, 40, 63, 1,

+};

+

+static const int exti_or_gates_num_lines_in[NUM_EXTI_OR_GATES] = {

+ 5, 6, 2, 5,

+};

+

+/* 3 OR gates with consecutive inputs */

+#define NUM_EXTI_SIMPLE_OR_GATES 3

+static const int exti_or_gates_first_line_in[NUM_EXTI_SIMPLE_OR_GATES] = {

+ 5, 10, 21,

+};

+

+/* 1 OR gate with non-consecutive inputs */

+#define EXTI_OR_GATE1_NUM_LINES_IN 5

+static const int exti_or_gate1_lines_in[EXTI_OR_GATE1_NUM_LINES_IN] = {

+ 16, 35, 36, 37, 38,

+};

+

static void stm32l4x5_soc_initfn(Object *obj)

{

Stm32l4x5SocState *s = STM32L4X5_SOC(obj);

object_initialize_child(obj, "exti", &s->exti, TYPE_STM32L4X5_EXTI);

+ for (unsigned i = 0; i < NUM_EXTI_OR_GATES; i++) {

+ object_initialize_child(obj, "exti_or_gates[*]", &s->exti_or_gates[i],

+ TYPE_OR_IRQ);

+ }

object_initialize_child(obj, "syscfg", &s->syscfg, TYPE_STM32L4X5_SYSCFG);

s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);

@@ -XXX,XX +XXX,XX @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)

sysbus_mmio_map(busdev, 0, EXTI_ADDR);

+

+ /* IRQs with fan-in that require an OR gate */

+ for (unsigned i = 0; i < NUM_EXTI_OR_GATES; i++) {

+ if (!object_property_set_int(OBJECT(&s->exti_or_gates[i]), "num-lines",

+ exti_or_gates_num_lines_in[i], errp)) {

+ return;

+ }

+ if (!qdev_realize(DEVICE(&s->exti_or_gates[i]), NULL, errp)) {

+ return;

+ }

+

+ qdev_connect_gpio_out(DEVICE(&s->exti_or_gates[i]), 0,

+ qdev_get_gpio_in(armv7m, exti_or_gates_out[i]));

+

+ if (i < NUM_EXTI_SIMPLE_OR_GATES) {

+ /* consecutive inputs for OR gates 23, 40, 63 */

+ for (unsigned j = 0; j < exti_or_gates_num_lines_in[i]; j++) {

+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->exti),

+ exti_or_gates_first_line_in[i] + j,

+ qdev_get_gpio_in(DEVICE(&s->exti_or_gates[i]), j));

+ }

+ } else {

+ /* non-consecutive inputs for OR gate 1 */

+ for (unsigned j = 0; j < EXTI_OR_GATE1_NUM_LINES_IN; j++) {

+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->exti),

+ exti_or_gate1_lines_in[j],

+ qdev_get_gpio_in(DEVICE(&s->exti_or_gates[i]), j));

+ }

+ }

+ }

+

+ /* IRQs that don't require fan-in */

for (unsigned i = 0; i < NUM_EXTI_IRQ; i++) {

- sysbus_connect_irq(busdev, i, qdev_get_gpio_in(armv7m, exti_irq[i]));

+ if (exti_irq[i] != -1) {

+ sysbus_connect_irq(busdev, i,

+ qdev_get_gpio_in(armv7m, exti_irq[i]));

+ }

for (unsigned i = 0; i < 16; i++) {

From: Sergey Kambalin <serg.oker@gmail.com>

Pre setup for BCM2838 introduction

Signed-off-by: Sergey Kambalin <sergey.kambalin@auriga.com>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Message-id: 20240226000259.2752893-2-sergey.kambalin@auriga.com

include/hw/arm/bcm2836.h | 26 +++++++++-

hw/arm/bcm2836.c | 103 ++++++++++++++++++++++-----------------

hw/arm/raspi.c | 2 +-

3 files changed, 84 insertions(+), 47 deletions(-)

diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h

--- a/include/hw/arm/bcm2836.h

+++ b/include/hw/arm/bcm2836.h

@@ -XXX,XX +XXX,XX @@

#include "target/arm/cpu.h"

#include "qom/object.h"

+#define TYPE_BCM283X_BASE "bcm283x-base"

+OBJECT_DECLARE_TYPE(BCM283XBaseState, BCM283XBaseClass, BCM283X_BASE)

#define TYPE_BCM283X "bcm283x"

-OBJECT_DECLARE_TYPE(BCM283XState, BCM283XClass, BCM283X)

+OBJECT_DECLARE_SIMPLE_TYPE(BCM283XState, BCM283X)

#define BCM283X_NCPUS 4

@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_TYPE(BCM283XState, BCM283XClass, BCM283X)

#define TYPE_BCM2836 "bcm2836"

#define TYPE_BCM2837 "bcm2837"

-struct BCM283XState {

+struct BCM283XBaseState {

/*< private >*/

DeviceState parent_obj;

/*< public >*/

@@ -XXX,XX +XXX,XX @@ struct BCM283XState {

ARMCPU core;

} cpu[BCM283X_NCPUS];

BCM2836ControlState control;

+};

+

+struct BCM283XBaseClass {

+ /*< private >*/

+ DeviceClass parent_class;

+ /*< public >*/

+ const char *name;

+ const char *cpu_type;

+ unsigned core_count;

+ hwaddr peri_base; /* Peripheral base address seen by the CPU */

+ hwaddr ctrl_base; /* Interrupt controller and mailboxes etc. */

+ int clusterid;

+};

+

+struct BCM283XState {

+ /*< private >*/

+ BCM283XBaseState parent_obj;

+ /*< public >*/

BCM2835PeripheralState peripherals;

};

+bool bcm283x_common_realize(DeviceState *dev, Error **errp);

+

#endif /* BCM2836_H */

diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/bcm2836.c

+++ b/hw/arm/bcm2836.c

@@ -XXX,XX +XXX,XX @@ struct BCM283XClass {

};

static Property bcm2836_enabled_cores_property =

- DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus, 0);

+ DEFINE_PROP_UINT32("enabled-cpus", BCM283XBaseState, enabled_cpus, 0);

-static void bcm2836_init(Object *obj)

+static void bcm283x_base_init(Object *obj)

- BCM283XState *s = BCM283X(obj);

- BCM283XClass *bc = BCM283X_GET_CLASS(obj);

+ BCM283XBaseState *s = BCM283X_BASE(obj);

+ BCM283XBaseClass *bc = BCM283X_BASE_GET_CLASS(obj);

int n;

for (n = 0; n < bc->core_count; n++) {

@@ -XXX,XX +XXX,XX @@ static void bcm2836_init(Object *obj)

object_initialize_child(obj, "control", &s->control,

TYPE_BCM2836_CONTROL);

+}

+

+static void bcm283x_init(Object *obj)

+{

+ BCM283XState *s = BCM283X(obj);

object_initialize_child(obj, "peripherals", &s->peripherals,

TYPE_BCM2835_PERIPHERALS);

@@ -XXX,XX +XXX,XX @@ static void bcm2836_init(Object *obj)

"vcram-size");

}

-static bool bcm283x_common_realize(DeviceState *dev, Error **errp)

+bool bcm283x_common_realize(DeviceState *dev, Error **errp)

{

BCM283XState *s = BCM283X(dev);

- BCM283XClass *bc = BCM283X_GET_CLASS(dev);

+ BCM283XBaseState *s_base = BCM283X_BASE(dev);

+ BCM283XBaseClass *bc = BCM283X_BASE_GET_CLASS(dev);

Object *obj;

/* common peripherals from bcm2835 */