From: Jamin Lin <jamin_lin@aspeedtech.com>
In the previous design of ASPEED SOCs QEMU model, it set the boot
address at "0" which was the hardcode setting for ast10x0, ast2600,
ast2500 and ast2400.
According to the design of ast2700, it has a bootmcu(riscv-32) which
is used for executing SPL and initialize DRAM and copy u-boot image
from SPI/Flash to DRAM at address 0x400000000 at SPL boot stage.
Then, CPUs(cortex-a35) execute u-boot, kernel and rofs.
Currently, qemu not support emulate two CPU architectures
at the same machine. Therefore, qemu will only support
to emulate CPU(cortex-a35) side for ast2700 and the boot
address is "0x4 00000000".
Fixed hardcode boot address "0" for future models using
a different mapping address.
Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/arm/aspeed_soc.h | 2 --
hw/arm/aspeed.c | 4 +++-
hw/arm/aspeed_ast2400.c | 4 ++--
hw/arm/aspeed_ast2600.c | 2 +-
4 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index e1a023be538b..c60fac900acb 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -224,8 +224,6 @@ enum {
ASPEED_DEV_FSI2,
};
-#define ASPEED_SOC_SPI_BOOT_ADDR 0x0
-
qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev);
bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp);
void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr);
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 0af96afa16a6..8854581ca8de 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -289,12 +289,14 @@ static void aspeed_install_boot_rom(AspeedMachineState *bmc, BlockBackend *blk,
uint64_t rom_size)
{
AspeedSoCState *soc = bmc->soc;
+ AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(soc);
memory_region_init_rom(&bmc->boot_rom, NULL, "aspeed.boot_rom", rom_size,
&error_abort);
memory_region_add_subregion_overlap(&soc->spi_boot_container, 0,
&bmc->boot_rom, 1);
- write_boot_rom(blk, ASPEED_SOC_SPI_BOOT_ADDR, rom_size, &error_abort);
+ write_boot_rom(blk, sc->memmap[ASPEED_DEV_SPI_BOOT],
+ rom_size, &error_abort);
}
void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype,
diff --git a/hw/arm/aspeed_ast2400.c b/hw/arm/aspeed_ast2400.c
index 95da85fee029..d12588620751 100644
--- a/hw/arm/aspeed_ast2400.c
+++ b/hw/arm/aspeed_ast2400.c
@@ -26,7 +26,7 @@
#define ASPEED_SOC_IOMEM_SIZE 0x00200000
static const hwaddr aspeed_soc_ast2400_memmap[] = {
- [ASPEED_DEV_SPI_BOOT] = ASPEED_SOC_SPI_BOOT_ADDR,
+ [ASPEED_DEV_SPI_BOOT] = 0x00000000,
[ASPEED_DEV_IOMEM] = 0x1E600000,
[ASPEED_DEV_FMC] = 0x1E620000,
[ASPEED_DEV_SPI1] = 0x1E630000,
@@ -61,7 +61,7 @@ static const hwaddr aspeed_soc_ast2400_memmap[] = {
};
static const hwaddr aspeed_soc_ast2500_memmap[] = {
- [ASPEED_DEV_SPI_BOOT] = ASPEED_SOC_SPI_BOOT_ADDR,
+ [ASPEED_DEV_SPI_BOOT] = 0x00000000,
[ASPEED_DEV_IOMEM] = 0x1E600000,
[ASPEED_DEV_FMC] = 0x1E620000,
[ASPEED_DEV_SPI1] = 0x1E630000,
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index f74561ecdcd5..174be537709b 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -22,7 +22,7 @@
#define ASPEED_SOC_DPMCU_SIZE 0x00040000
static const hwaddr aspeed_soc_ast2600_memmap[] = {
- [ASPEED_DEV_SPI_BOOT] = ASPEED_SOC_SPI_BOOT_ADDR,
+ [ASPEED_DEV_SPI_BOOT] = 0x00000000,
[ASPEED_DEV_SRAM] = 0x10000000,
[ASPEED_DEV_DPMCU] = 0x18000000,
/* 0x16000000 0x17FFFFFF : AHB BUS do LPC Bus bridge */
--
2.43.2
Hi Jamin, On 27/2/24 13:52, Cédric Le Goater wrote: > From: Jamin Lin <jamin_lin@aspeedtech.com> > > In the previous design of ASPEED SOCs QEMU model, it set the boot > address at "0" which was the hardcode setting for ast10x0, ast2600, > ast2500 and ast2400. > > According to the design of ast2700, it has a bootmcu(riscv-32) which > is used for executing SPL and initialize DRAM and copy u-boot image > from SPI/Flash to DRAM at address 0x400000000 at SPL boot stage. > Then, CPUs(cortex-a35) execute u-boot, kernel and rofs. > > Currently, qemu not support emulate two CPU architectures > at the same machine. Therefore, qemu will only support > to emulate CPU(cortex-a35) side for ast2700 and the boot > address is "0x4 00000000". > > Fixed hardcode boot address "0" for future models using > a different mapping address. > > Signed-off-by: Troy Lee <troy_lee@aspeedtech.com> > Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> > Reviewed-by: Cédric Le Goater <clg@kaod.org> Tip for the email workflow: when someone provide a R-b tag for a patch, please carry it on in your next iterations. https://lore.kernel.org/qemu-devel/09f9ca34-4e0c-4ada-b808-643a8c578511@linaro.org/ See https://www.qemu.org/docs/master/devel/submitting-a-patch.html#proper-use-of-reviewed-by-tags-can-aid-review > Signed-off-by: Cédric Le Goater <clg@kaod.org> > --- > include/hw/arm/aspeed_soc.h | 2 -- > hw/arm/aspeed.c | 4 +++- > hw/arm/aspeed_ast2400.c | 4 ++-- > hw/arm/aspeed_ast2600.c | 2 +- > 4 files changed, 6 insertions(+), 6 deletions(-)
> -----Original Message----- > From: Philippe Mathieu-Daudé <philmd@linaro.org> > Sent: Friday, March 1, 2024 11:49 PM > To: Cédric Le Goater <clg@kaod.org>; qemu-arm@nongnu.org; > qemu-devel@nongnu.org > Cc: Jamin Lin <jamin_lin@aspeedtech.com>; Troy Lee > <troy_lee@aspeedtech.com> > Subject: Re: [PULL 2/2] aspeed: fix hardcode boot address 0 > > Hi Jamin, > > On 27/2/24 13:52, Cédric Le Goater wrote: > > From: Jamin Lin <jamin_lin@aspeedtech.com> > > > > In the previous design of ASPEED SOCs QEMU model, it set the boot > > address at "0" which was the hardcode setting for ast10x0, ast2600, > > ast2500 and ast2400. > > > > According to the design of ast2700, it has a bootmcu(riscv-32) which > > is used for executing SPL and initialize DRAM and copy u-boot image > > from SPI/Flash to DRAM at address 0x400000000 at SPL boot stage. > > Then, CPUs(cortex-a35) execute u-boot, kernel and rofs. > > > > Currently, qemu not support emulate two CPU architectures at the same > > machine. Therefore, qemu will only support to emulate CPU(cortex-a35) > > side for ast2700 and the boot address is "0x4 00000000". > > > > Fixed hardcode boot address "0" for future models using a different > > mapping address. > > > > Signed-off-by: Troy Lee <troy_lee@aspeedtech.com> > > Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> > > Reviewed-by: Cédric Le Goater <clg@kaod.org> > > Tip for the email workflow: when someone provide a R-b tag for a patch, > please carry it on in your next iterations. > > https://lore.kernel.org/qemu-devel/09f9ca34-4e0c-4ada-b808-643a8c578511 > @linaro.org/ > > See > https://www.qemu.org/docs/master/devel/submitting-a-patch.html#proper-us > e-of-reviewed-by-tags-can-aid-review > Got it and thanks for notification. > > Signed-off-by: Cédric Le Goater <clg@kaod.org> > > --- > > include/hw/arm/aspeed_soc.h | 2 -- > > hw/arm/aspeed.c | 4 +++- > > hw/arm/aspeed_ast2400.c | 4 ++-- > > hw/arm/aspeed_ast2600.c | 2 +- > > 4 files changed, 6 insertions(+), 6 deletions(-)
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