RISC-V: Implement CSR tcontrol in debug spec

[PATCH 4/4] target/riscv: Set the value of CSR tcontrol when mret is executed

Posted by Alvin Chang via 8 months, 2 weeks ago

The RISC-V debug specification defines the following operation for CSR
tcontrol when "mret" is executed:
- tcontrol.MTE is set to the value of tcontrol.MPTE

This commit implements the above operation into helper_mret().

Note that from tech-debug mailing list:
https://lists.riscv.org/g/tech-debug/topic/102702615#1461
The debug specification does not mention the operation to tcontrol.MPTE
when "mret" is executed. Therefore, we just keep its current value.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
---
 target/riscv/op_helper.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index f414aaebdb..12822b3afa 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -347,6 +347,12 @@ target_ulong helper_mret(CPURISCVState *env)
         mstatus = set_field(mstatus, MSTATUS_MPRV, 0);
     }
     env->mstatus = mstatus;
+
+    uint64_t tcontrol = env->tcontrol;
+    tcontrol = set_field(tcontrol, TCONTROL_MTE,
+                         get_field(tcontrol, TCONTROL_MPTE));
+    env->tcontrol = tcontrol;
+
     riscv_cpu_set_mode(env, prev_priv);
 
     if (riscv_has_ext(env, RVH)) {
-- 
2.34.1

Re: [PATCH 4/4] target/riscv: Set the value of CSR tcontrol when mret is executed

Posted by Daniel Henrique Barboza 8 months, 2 weeks ago


On 2/16/24 03:13, Alvin Chang wrote:
> The RISC-V debug specification defines the following operation for CSR
> tcontrol when "mret" is executed:
> - tcontrol.MTE is set to the value of tcontrol.MPTE
> 
> This commit implements the above operation into helper_mret().
> 
> Note that from tech-debug mailing list:
> https://lists.riscv.org/g/tech-debug/topic/102702615#1461
> The debug specification does not mention the operation to tcontrol.MPTE
> when "mret" is executed. Therefore, we just keep its current value.
> 
> Signed-off-by: Alvin Chang <alvinga@andestech.com>
> ---

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   target/riscv/op_helper.c | 6 ++++++
>   1 file changed, 6 insertions(+)
> 
> diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
> index f414aaebdb..12822b3afa 100644
> --- a/target/riscv/op_helper.c
> +++ b/target/riscv/op_helper.c
> @@ -347,6 +347,12 @@ target_ulong helper_mret(CPURISCVState *env)
>           mstatus = set_field(mstatus, MSTATUS_MPRV, 0);
>       }
>       env->mstatus = mstatus;
> +
> +    uint64_t tcontrol = env->tcontrol;
> +    tcontrol = set_field(tcontrol, TCONTROL_MTE,
> +                         get_field(tcontrol, TCONTROL_MPTE));
> +    env->tcontrol = tcontrol;
> +
>       riscv_cpu_set_mode(env, prev_priv);
>   
>       if (riscv_has_ext(env, RVH)) {

[PATCH 1/4] target/riscv: Add CSR tcontrol of debug trigger module
[PATCH 2/4] target/riscv: Reset CSR tcontrol when the trigger module resets
[PATCH 3/4] target/riscv: Set the value of CSR tcontrol when trapping to M-mode
[PATCH 4/4] target/riscv: Set the value of CSR tcontrol when mret is executed