[PATCH 2/4] target/riscv: Reset CSR tcontrol when the trigger module resets

Alvin Chang via posted 4 patches 8 months, 2 weeks ago
Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Bin Meng <bin.meng@windriver.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
[PATCH 2/4] target/riscv: Reset CSR tcontrol when the trigger module resets
Posted by Alvin Chang via 8 months, 2 weeks ago
When the trigger module resets, reset the value of CSR tcontrol as zero.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
---
 target/riscv/debug.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index e30d99cc2f..e3832a643e 100644
--- a/target/riscv/debug.c
+++ b/target/riscv/debug.c
@@ -941,5 +941,6 @@ void riscv_trigger_reset_hold(CPURISCVState *env)
         timer_del(env->itrigger_timer[i]);
     }
 
+    env->tcontrol = 0;
     env->mcontext = 0;
 }
-- 
2.34.1
Re: [PATCH 2/4] target/riscv: Reset CSR tcontrol when the trigger module resets
Posted by Daniel Henrique Barboza 8 months, 2 weeks ago

On 2/16/24 03:13, Alvin Chang wrote:
> When the trigger module resets, reset the value of CSR tcontrol as zero.
> 
> Signed-off-by: Alvin Chang <alvinga@andestech.com>
> ---

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   target/riscv/debug.c | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/target/riscv/debug.c b/target/riscv/debug.c
> index e30d99cc2f..e3832a643e 100644
> --- a/target/riscv/debug.c
> +++ b/target/riscv/debug.c
> @@ -941,5 +941,6 @@ void riscv_trigger_reset_hold(CPURISCVState *env)
>           timer_del(env->itrigger_timer[i]);
>       }
>   
> +    env->tcontrol = 0;
>       env->mcontext = 0;
>   }