RISC-V: Implement CSR tcontrol in debug spec

[PATCH 0/4] RISC-V: Implement CSR tcontrol in debug spec

Alvin Chang via posted 4 patches 8 months, 2 weeks ago

Download series mbox

Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20240216061332.50229-1-alvinga@andestech.com

Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Bin Meng <bin.meng@windriver.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>

target/riscv/cpu.h        |  1 +
target/riscv/cpu_bits.h   |  3 +++
target/riscv/cpu_helper.c |  6 ++++++
target/riscv/csr.c        | 15 +++++++++++++++
target/riscv/debug.c      |  1 +
target/riscv/op_helper.c  |  6 ++++++
6 files changed, 32 insertions(+)

Expand all Fold all

[PATCH 0/4] RISC-V: Implement CSR tcontrol in debug spec

Posted by Alvin Chang via 8 months, 2 weeks ago

The RISC-V Debug specification defines CSR "tcontrol" in the trigger
module:
  https://github.com/riscv/riscv-debug-spec

This series implements it and the related operations.

Alvin Chang (4):
  target/riscv: Add CSR tcontrol of debug trigger module
  target/riscv: Reset CSR tcontrol when the trigger module resets
  target/riscv: Set the value of CSR tcontrol when trapping to M-mode
  target/riscv: Set the value of CSR tcontrol when mret is executed

 target/riscv/cpu.h        |  1 +
 target/riscv/cpu_bits.h   |  3 +++
 target/riscv/cpu_helper.c |  6 ++++++
 target/riscv/csr.c        | 15 +++++++++++++++
 target/riscv/debug.c      |  1 +
 target/riscv/op_helper.c  |  6 ++++++
 6 files changed, 32 insertions(+)

-- 
2.34.1