https://lore.kernel.org/qemu-devel/20240215150133.2088-1-Jonathan.Cameron@huawei.com/
gives more details of the reason the CXL emulation uses MMIO space
(short answer is it has very fine grained address routing).

Obviously this one is lower priority for me to upstream as the ARM support in
general is only in my CXL staging tree (I'll get back to that soonish).

The equivalent tests with CXL memory and forcing applications to run from it
on ARM64 TCG ran into an additional issue.  We need to be able to do
atomic compare and swap to update the access and dirty flags as part of
a page walk if we have the ARM 8.1 FEAT_HADFS (note you can disable this in
the kernel then this problem isn't hit but that's not a viable long term
solution though it did help me diagnose the problem)

As the patch says I'm far from confident on this fix. Whilst it 'works'
for little endian at least I'm hoping someone more familiar with the locking
requirements etc can let me know if the BQL is the right option here and
people can give a general opinion on whether such a hack is the right
solution.

Jonathan Cameron (1):
  arm/ptw: Handle atomic updates of page tables entries in MMIO during
    PTW.

 target/arm/ptw.c | 34 ++++++++++++++++++++++++++++++++--
 1 file changed, 32 insertions(+), 2 deletions(-)

-- 
2.39.2