[v3] UART0 device name and fix hardcode boot address 0

[PATCH v3 0/2] UART0 device name and fix hardcode boot address 0

Jamin Lin via posted 2 patches 9 months, 2 weeks ago

Diff against v3 v3 v3
Download series mbox

Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20240215075331.2512428-1-jamin._5Flin@aspeedtech.com

Maintainers: "Cédric Le Goater" <clg@kaod.org>, Peter Maydell <peter.maydell@linaro.org>, Andrew Jeffery <andrew@codeconstruct.com.au>, Joel Stanley <joel@jms.id.au>

There is a newer version of this series

hw/arm/aspeed.c             | 17 +++++++++++------
hw/arm/aspeed_ast10x0.c     |  1 +
hw/arm/aspeed_ast2400.c     |  6 ++++--
hw/arm/aspeed_ast2600.c     |  3 ++-
hw/arm/aspeed_soc_common.c  | 10 ++++++----
include/hw/arm/aspeed_soc.h | 19 +++++++++++++++++--
6 files changed, 41 insertions(+), 15 deletions(-)

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[PATCH v3 0/2] UART0 device name and fix hardcode boot address 0

Posted by Jamin Lin via 9 months, 2 weeks ago

v1:
1. support uart controller both 0 and 1 base
2. fix hardcode boot address 0

v2:
1. introduce a new UART0 device name
2. remove ASPEED_SOC_SPI_BOOT_ADDR marco

v3:
1. add uart helper functions to get the index, start and last.
2. add more description in commit log

Jamin Lin (2):
  aspeed: introduce a new UART0 device name
  aspeed: fix hardcode boot address 0

 hw/arm/aspeed.c             | 17 +++++++++++------
 hw/arm/aspeed_ast10x0.c     |  1 +
 hw/arm/aspeed_ast2400.c     |  6 ++++--
 hw/arm/aspeed_ast2600.c     |  3 ++-
 hw/arm/aspeed_soc_common.c  | 10 ++++++----
 include/hw/arm/aspeed_soc.h | 19 +++++++++++++++++--
 6 files changed, 41 insertions(+), 15 deletions(-)

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2.25.1