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[PATCH v3 2/3] Hexagon (target/hexagon) Pass SP explicitly to helpers that need it

Taylor Simpson posted 3 patches 9 months, 2 weeks ago
Maintainers: Brian Cain <bcain@quicinc.com>
[PATCH v3 2/3] Hexagon (target/hexagon) Pass SP explicitly to helpers that need it
Posted by Taylor Simpson 9 months, 2 weeks ago 
Rather than reading SP from the env, pass it explicitly

Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Tested-by: Anton Johansson <anjo@rev.ng>
---
 target/hexagon/macros.h          |  2 +-
 target/hexagon/attribs_def.h.inc |  3 ++-
 target/hexagon/hex_common.py     | 11 +++++++++++
 3 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h
index aedc863fab..feb798c6c0 100644
--- a/target/hexagon/macros.h
+++ b/target/hexagon/macros.h
@@ -343,7 +343,7 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv val, int shift)
 
 #define fREAD_LR() (env->gpr[HEX_REG_LR])
 
-#define fREAD_SP() (env->gpr[HEX_REG_SP])
+#define fREAD_SP() (SP)
 #define fREAD_LC0 (env->gpr[HEX_REG_LC0])
 #define fREAD_LC1 (env->gpr[HEX_REG_LC1])
 #define fREAD_SA0 (env->gpr[HEX_REG_SA0])
diff --git a/target/hexagon/attribs_def.h.inc b/target/hexagon/attribs_def.h.inc
index 87942d46f4..9e3a05f882 100644
--- a/target/hexagon/attribs_def.h.inc
+++ b/target/hexagon/attribs_def.h.inc
@@ -1,5 +1,5 @@
 /*
- *  Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
+ *  Copyright(c) 2019-2024 Qualcomm Innovation Center, Inc. All Rights Reserved.
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -117,6 +117,7 @@ DEF_ATTRIB(IMPLICIT_READS_P1, "Reads the P1 register", "", "")
 DEF_ATTRIB(IMPLICIT_READS_P2, "Reads the P2 register", "", "")
 DEF_ATTRIB(IMPLICIT_READS_P3, "Reads the P3 register", "", "")
 DEF_ATTRIB(IMPLICIT_WRITES_USR, "May write USR", "", "")
+DEF_ATTRIB(IMPLICIT_READS_SP, "Reads the SP register", "", "")
 DEF_ATTRIB(COMMUTES, "The operation is communitive", "", "")
 DEF_ATTRIB(DEALLOCRET, "dealloc_return", "", "")
 DEF_ATTRIB(DEALLOCFRAME, "deallocframe", "", "")
diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py
index 14dcf261b4..b96f67972d 100755
--- a/target/hexagon/hex_common.py
+++ b/target/hexagon/hex_common.py
@@ -101,6 +101,7 @@ def calculate_attribs():
     add_qemu_macro_attrib('fLSBNEW1', 'A_IMPLICIT_READS_P1')
     add_qemu_macro_attrib('fLSBNEW1NOT', 'A_IMPLICIT_READS_P1')
     add_qemu_macro_attrib('fREAD_P3', 'A_IMPLICIT_READS_P3')
+    add_qemu_macro_attrib('fREAD_SP', 'A_IMPLICIT_READS_SP')
 
     # Recurse down macros, find attributes from sub-macros
     macroValues = list(macros.values())
@@ -201,6 +202,10 @@ def need_p0(tag):
     return "A_IMPLICIT_READS_P0" in attribdict[tag]
 
 
+def need_sp(tag):
+    return "A_IMPLICIT_READS_SP" in attribdict[tag]
+
+
 def need_slot(tag):
     if (
         "A_CVI_SCATTER" not in attribdict[tag]
@@ -1128,6 +1133,12 @@ def helper_args(tag, regs, imms):
             "hex_pred[0]",
             "uint32_t P0"
         ))
+    if need_sp(tag):
+        args.append(HelperArg(
+            "i32",
+            "hex_gpr[HEX_REG_SP]",
+            "uint32_t SP"
+        ))
     if need_slot(tag):
         args.append(HelperArg(
             "i32",
-- 
2.34.1
RE: [PATCH v3 2/3] Hexagon (target/hexagon) Pass SP explicitly to helpers that need it
Posted by Brian Cain 9 months, 1 week ago 

> -----Original Message-----
> From: Taylor Simpson <ltaylorsimpson@gmail.com>
> Sent: Tuesday, February 13, 2024 10:27 PM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain <bcain@quicinc.com>; Matheus Bernardino (QUIC)
> <quic_mathbern@quicinc.com>; Sid Manning <sidneym@quicinc.com>; Marco
> Liebel (QUIC) <quic_mliebel@quicinc.com>; richard.henderson@linaro.org;
> philmd@linaro.org; ale@rev.ng; anjo@rev.ng; ltaylorsimpson@gmail.com
> Subject: [PATCH v3 2/3] Hexagon (target/hexagon) Pass SP explicitly to helpers
> that need it
> 
> WARNING: This email originated from outside of Qualcomm. Please be wary of
> any links or attachments, and do not enable macros.
> 
> Rather than reading SP from the env, pass it explicitly
> 
> Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com>
> Reviewed-by: Anton Johansson <anjo@rev.ng>
> Tested-by: Anton Johansson <anjo@rev.ng>
> ---


Reviewed-by: Brian Cain <bcain@quicinc.com>

>  target/hexagon/macros.h          |  2 +-
>  target/hexagon/attribs_def.h.inc |  3 ++-
>  target/hexagon/hex_common.py     | 11 +++++++++++
>  3 files changed, 14 insertions(+), 2 deletions(-)
> 
> diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h
> index aedc863fab..feb798c6c0 100644
> --- a/target/hexagon/macros.h
> +++ b/target/hexagon/macros.h
> @@ -343,7 +343,7 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv val,
> int shift)
> 
>  #define fREAD_LR() (env->gpr[HEX_REG_LR])
> 
> -#define fREAD_SP() (env->gpr[HEX_REG_SP])
> +#define fREAD_SP() (SP)
>  #define fREAD_LC0 (env->gpr[HEX_REG_LC0])
>  #define fREAD_LC1 (env->gpr[HEX_REG_LC1])
>  #define fREAD_SA0 (env->gpr[HEX_REG_SA0])
> diff --git a/target/hexagon/attribs_def.h.inc b/target/hexagon/attribs_def.h.inc
> index 87942d46f4..9e3a05f882 100644
> --- a/target/hexagon/attribs_def.h.inc
> +++ b/target/hexagon/attribs_def.h.inc
> @@ -1,5 +1,5 @@
>  /*
> - *  Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights
> Reserved.
> + *  Copyright(c) 2019-2024 Qualcomm Innovation Center, Inc. All Rights
> Reserved.
>   *
>   *  This program is free software; you can redistribute it and/or modify
>   *  it under the terms of the GNU General Public License as published by
> @@ -117,6 +117,7 @@ DEF_ATTRIB(IMPLICIT_READS_P1, "Reads the P1
> register", "", "")
>  DEF_ATTRIB(IMPLICIT_READS_P2, "Reads the P2 register", "", "")
>  DEF_ATTRIB(IMPLICIT_READS_P3, "Reads the P3 register", "", "")
>  DEF_ATTRIB(IMPLICIT_WRITES_USR, "May write USR", "", "")
> +DEF_ATTRIB(IMPLICIT_READS_SP, "Reads the SP register", "", "")
>  DEF_ATTRIB(COMMUTES, "The operation is communitive", "", "")
>  DEF_ATTRIB(DEALLOCRET, "dealloc_return", "", "")
>  DEF_ATTRIB(DEALLOCFRAME, "deallocframe", "", "")
> diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py
> index 14dcf261b4..b96f67972d 100755
> --- a/target/hexagon/hex_common.py
> +++ b/target/hexagon/hex_common.py
> @@ -101,6 +101,7 @@ def calculate_attribs():
>      add_qemu_macro_attrib('fLSBNEW1', 'A_IMPLICIT_READS_P1')
>      add_qemu_macro_attrib('fLSBNEW1NOT', 'A_IMPLICIT_READS_P1')
>      add_qemu_macro_attrib('fREAD_P3', 'A_IMPLICIT_READS_P3')
> +    add_qemu_macro_attrib('fREAD_SP', 'A_IMPLICIT_READS_SP')
> 
>      # Recurse down macros, find attributes from sub-macros
>      macroValues = list(macros.values())
> @@ -201,6 +202,10 @@ def need_p0(tag):
>      return "A_IMPLICIT_READS_P0" in attribdict[tag]
> 
> 
> +def need_sp(tag):
> +    return "A_IMPLICIT_READS_SP" in attribdict[tag]
> +
> +
>  def need_slot(tag):
>      if (
>          "A_CVI_SCATTER" not in attribdict[tag]
> @@ -1128,6 +1133,12 @@ def helper_args(tag, regs, imms):
>              "hex_pred[0]",
>              "uint32_t P0"
>          ))
> +    if need_sp(tag):
> +        args.append(HelperArg(
> +            "i32",
> +            "hex_gpr[HEX_REG_SP]",
> +            "uint32_t SP"
> +        ))
>      if need_slot(tag):
>          args.append(HelperArg(
>              "i32",
> --
> 2.34.1
RE: [PATCH v3 2/3] Hexagon (target/hexagon) Pass SP explicitly to helpers that need it
Posted by Brian Cain 9 months, 1 week ago 

> -----Original Message-----
> From: Taylor Simpson <ltaylorsimpson@gmail.com>
> Sent: Tuesday, February 13, 2024 10:27 PM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain <bcain@quicinc.com>; Matheus Bernardino (QUIC)
> <quic_mathbern@quicinc.com>; Sid Manning <sidneym@quicinc.com>; Marco
> Liebel (QUIC) <quic_mliebel@quicinc.com>; richard.henderson@linaro.org;
> philmd@linaro.org; ale@rev.ng; anjo@rev.ng; ltaylorsimpson@gmail.com
> Subject: [PATCH v3 2/3] Hexagon (target/hexagon) Pass SP explicitly to helpers
> that need it
> 
> WARNING: This email originated from outside of Qualcomm. Please be wary of
> any links or attachments, and do not enable macros.
> 
> Rather than reading SP from the env, pass it explicitly
> 
> Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com>
> Reviewed-by: Anton Johansson <anjo@rev.ng>
> Tested-by: Anton Johansson <anjo@rev.ng>
> ---

Reviewed-by: Brian Cain <bcain@quicinc.com>

>  target/hexagon/macros.h          |  2 +-
>  target/hexagon/attribs_def.h.inc |  3 ++-
>  target/hexagon/hex_common.py     | 11 +++++++++++
>  3 files changed, 14 insertions(+), 2 deletions(-)
> 
> diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h
> index aedc863fab..feb798c6c0 100644
> --- a/target/hexagon/macros.h
> +++ b/target/hexagon/macros.h
> @@ -343,7 +343,7 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv val,
> int shift)
> 
>  #define fREAD_LR() (env->gpr[HEX_REG_LR])
> 
> -#define fREAD_SP() (env->gpr[HEX_REG_SP])
> +#define fREAD_SP() (SP)
>  #define fREAD_LC0 (env->gpr[HEX_REG_LC0])
>  #define fREAD_LC1 (env->gpr[HEX_REG_LC1])
>  #define fREAD_SA0 (env->gpr[HEX_REG_SA0])
> diff --git a/target/hexagon/attribs_def.h.inc b/target/hexagon/attribs_def.h.inc
> index 87942d46f4..9e3a05f882 100644
> --- a/target/hexagon/attribs_def.h.inc
> +++ b/target/hexagon/attribs_def.h.inc
> @@ -1,5 +1,5 @@
>  /*
> - *  Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights
> Reserved.
> + *  Copyright(c) 2019-2024 Qualcomm Innovation Center, Inc. All Rights
> Reserved.
>   *
>   *  This program is free software; you can redistribute it and/or modify
>   *  it under the terms of the GNU General Public License as published by
> @@ -117,6 +117,7 @@ DEF_ATTRIB(IMPLICIT_READS_P1, "Reads the P1
> register", "", "")
>  DEF_ATTRIB(IMPLICIT_READS_P2, "Reads the P2 register", "", "")
>  DEF_ATTRIB(IMPLICIT_READS_P3, "Reads the P3 register", "", "")
>  DEF_ATTRIB(IMPLICIT_WRITES_USR, "May write USR", "", "")
> +DEF_ATTRIB(IMPLICIT_READS_SP, "Reads the SP register", "", "")
>  DEF_ATTRIB(COMMUTES, "The operation is communitive", "", "")
>  DEF_ATTRIB(DEALLOCRET, "dealloc_return", "", "")
>  DEF_ATTRIB(DEALLOCFRAME, "deallocframe", "", "")
> diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py
> index 14dcf261b4..b96f67972d 100755
> --- a/target/hexagon/hex_common.py
> +++ b/target/hexagon/hex_common.py
> @@ -101,6 +101,7 @@ def calculate_attribs():
>      add_qemu_macro_attrib('fLSBNEW1', 'A_IMPLICIT_READS_P1')
>      add_qemu_macro_attrib('fLSBNEW1NOT', 'A_IMPLICIT_READS_P1')
>      add_qemu_macro_attrib('fREAD_P3', 'A_IMPLICIT_READS_P3')
> +    add_qemu_macro_attrib('fREAD_SP', 'A_IMPLICIT_READS_SP')
> 
>      # Recurse down macros, find attributes from sub-macros
>      macroValues = list(macros.values())
> @@ -201,6 +202,10 @@ def need_p0(tag):
>      return "A_IMPLICIT_READS_P0" in attribdict[tag]
> 
> 
> +def need_sp(tag):
> +    return "A_IMPLICIT_READS_SP" in attribdict[tag]
> +
> +
>  def need_slot(tag):
>      if (
>          "A_CVI_SCATTER" not in attribdict[tag]
> @@ -1128,6 +1133,12 @@ def helper_args(tag, regs, imms):
>              "hex_pred[0]",
>              "uint32_t P0"
>          ))
> +    if need_sp(tag):
> +        args.append(HelperArg(
> +            "i32",
> +            "hex_gpr[HEX_REG_SP]",
> +            "uint32_t SP"
> +        ))
>      if need_slot(tag):
>          args.append(HelperArg(
>              "i32",
> --
> 2.34.1

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