From: Helge Deller <deller@gmx.de>
Add the do_transaction_failed() handler to tigger a HPMC to the CPU
in case of I/O transaction errors.
This is a preparation commit.
We still lack implementation for some registers, so do not yet enable sending
HPMCs. Having this hunk here now nevertheless helps for the further
development, so that it can easily be enabled later on.
Signed-off-by: Helge Deller <deller@gmx.de>
---
target/hppa/cpu.c | 1 +
target/hppa/cpu.h | 5 +++++
target/hppa/mem_helper.c | 19 +++++++++++++++++++
3 files changed, 25 insertions(+)
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index 5f87c1b12a..afe73d4474 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -191,6 +191,7 @@ static const TCGCPUOps hppa_tcg_ops = {
.cpu_exec_interrupt = hppa_cpu_exec_interrupt,
.do_interrupt = hppa_cpu_do_interrupt,
.do_unaligned_access = hppa_cpu_do_unaligned_access,
+ .do_transaction_failed = hppa_cpu_do_transaction_failed,
#endif /* !CONFIG_USER_ONLY */
};
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index 06b65f2258..5a4b56c975 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -383,6 +383,11 @@ bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req);
int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx,
int type, hwaddr *pphys, int *pprot,
HPPATLBEntry **tlb_entry);
+void hppa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
+ vaddr addr, unsigned size,
+ MMUAccessType access_type,
+ int mmu_idx, MemTxAttrs attrs,
+ MemTxResult response, uintptr_t retaddr);
extern const MemoryRegionOps hppa_io_eir_ops;
extern const VMStateDescription vmstate_hppa_cpu;
void hppa_cpu_alarm_timer(void *);
diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c
index 629a9d90ef..676c0b3003 100644
--- a/target/hppa/mem_helper.c
+++ b/target/hppa/mem_helper.c
@@ -353,6 +353,25 @@ raise_exception_with_ior(CPUHPPAState *env, int excp, uintptr_t retaddr,
cpu_loop_exit_restore(cs, retaddr);
}
+void hppa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
+ vaddr addr, unsigned size,
+ MMUAccessType access_type,
+ int mmu_idx, MemTxAttrs attrs,
+ MemTxResult response, uintptr_t retaddr)
+{
+ CPUHPPAState *env = cpu_env(cs);
+
+ qemu_log_mask(LOG_GUEST_ERROR, "HPMC at " TARGET_FMT_lx ":" TARGET_FMT_lx
+ " while accessing I/O at %#08" HWADDR_PRIx "\n",
+ env->iasq_f, env->iaoq_f, physaddr);
+
+ /* FIXME: Enable HPMC exceptions when firmware has clean device probing */
+ if (0) {
+ raise_exception_with_ior(env, EXCP_HPMC, retaddr, addr,
+ MMU_IDX_MMU_DISABLED(mmu_idx));
+ }
+}
+
bool hppa_cpu_tlb_fill(CPUState *cs, vaddr addr, int size,
MMUAccessType type, int mmu_idx,
bool probe, uintptr_t retaddr)
--
2.43.0