Now that we can generate reliable clock frequencies from the RCC, remove
the hacky definition of the sysclk in the b_l475e_iot01a initialisation
code and use the correct RCC clock.
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
---
hw/arm/b-l475e-iot01a.c | 10 +---------
hw/arm/stm32l4x5_soc.c | 33 ++++-----------------------------
include/hw/arm/stm32l4x5_soc.h | 3 ---
3 files changed, 5 insertions(+), 41 deletions(-)
diff --git a/hw/arm/b-l475e-iot01a.c b/hw/arm/b-l475e-iot01a.c
index 6ecde2db15..d862aa43fc 100644
--- a/hw/arm/b-l475e-iot01a.c
+++ b/hw/arm/b-l475e-iot01a.c
@@ -26,27 +26,19 @@
#include "qapi/error.h"
#include "hw/boards.h"
#include "hw/qdev-properties.h"
-#include "hw/qdev-clock.h"
#include "qemu/error-report.h"
#include "hw/arm/stm32l4x5_soc.h"
#include "hw/arm/boot.h"
-/* Main SYSCLK frequency in Hz (80MHz) */
-#define MAIN_SYSCLK_FREQ_HZ 80000000ULL
+/* B-L475E-IOT01A implementation is derived from netduinoplus2 */
static void b_l475e_iot01a_init(MachineState *machine)
{
const Stm32l4x5SocClass *sc;
DeviceState *dev;
- Clock *sysclk;
-
- /* This clock doesn't need migration because it is fixed-frequency */
- sysclk = clock_new(OBJECT(machine), "SYSCLK");
- clock_set_hz(sysclk, MAIN_SYSCLK_FREQ_HZ);
dev = qdev_new(TYPE_STM32L4X5XG_SOC);
object_property_add_child(OBJECT(machine), "soc", OBJECT(dev));
- qdev_connect_clock_in(dev, "sysclk", sysclk);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sc = STM32L4X5_SOC_GET_CLASS(dev);
diff --git a/hw/arm/stm32l4x5_soc.c b/hw/arm/stm32l4x5_soc.c
index d5c04b446d..347a5377e5 100644
--- a/hw/arm/stm32l4x5_soc.c
+++ b/hw/arm/stm32l4x5_soc.c
@@ -85,9 +85,6 @@ static void stm32l4x5_soc_initfn(Object *obj)
object_initialize_child(obj, "exti", &s->exti, TYPE_STM32L4X5_EXTI);
object_initialize_child(obj, "syscfg", &s->syscfg, TYPE_STM32L4X5_SYSCFG);
object_initialize_child(obj, "rcc", &s->rcc, TYPE_STM32L4X5_RCC);
-
- s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
- s->refclk = qdev_init_clock_in(DEVICE(s), "refclk", NULL, NULL, 0);
}
static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
@@ -99,30 +96,6 @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
DeviceState *armv7m;
SysBusDevice *busdev;
- /*
- * We use s->refclk internally and only define it with qdev_init_clock_in()
- * so it is correctly parented and not leaked on an init/deinit; it is not
- * intended as an externally exposed clock.
- */
- if (clock_has_source(s->refclk)) {
- error_setg(errp, "refclk clock must not be wired up by the board code");
- return;
- }
-
- if (!clock_has_source(s->sysclk)) {
- error_setg(errp, "sysclk clock must be wired up by the board code");
- return;
- }
-
- /*
- * TODO: ideally we should model the SoC RCC and its ability to
- * change the sysclk frequency and define different sysclk sources.
- */
-
- /* The refclk always runs at frequency HCLK / 8 */
- clock_set_mul_div(s->refclk, 8, 1);
- clock_set_source(s->refclk, s->sysclk);
-
if (!memory_region_init_rom(&s->flash, OBJECT(dev_soc), "flash",
sc->flash_size, errp)) {
return;
@@ -152,8 +125,10 @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
qdev_prop_set_uint32(armv7m, "num-prio-bits", 4);
qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4"));
qdev_prop_set_bit(armv7m, "enable-bitband", true);
- qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
- qdev_connect_clock_in(armv7m, "refclk", s->refclk);
+ qdev_connect_clock_in(armv7m, "cpuclk",
+ qdev_get_clock_out(DEVICE(&(s->rcc)), "cortex-fclk-out"));
+ qdev_connect_clock_in(armv7m, "refclk",
+ qdev_get_clock_out(DEVICE(&(s->rcc)), "cortex-refclk-out"));
object_property_set_link(OBJECT(&s->armv7m), "memory",
OBJECT(system_memory), &error_abort);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) {
diff --git a/include/hw/arm/stm32l4x5_soc.h b/include/hw/arm/stm32l4x5_soc.h
index e480fcc976..1f71298b45 100644
--- a/include/hw/arm/stm32l4x5_soc.h
+++ b/include/hw/arm/stm32l4x5_soc.h
@@ -50,9 +50,6 @@ struct Stm32l4x5SocState {
MemoryRegion sram2;
MemoryRegion flash;
MemoryRegion flash_alias;
-
- Clock *sysclk;
- Clock *refclk;
};
struct Stm32l4x5SocClass {
--
2.34.1On Wed, Jan 31, 2024 at 3:21 AM Arnaud Minier
<arnaud.minier@telecom-paris.fr> wrote:
>
> Now that we can generate reliable clock frequencies from the RCC, remove
> the hacky definition of the sysclk in the b_l475e_iot01a initialisation
> code and use the correct RCC clock.
>
> Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
> Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> hw/arm/b-l475e-iot01a.c | 10 +---------
> hw/arm/stm32l4x5_soc.c | 33 ++++-----------------------------
> include/hw/arm/stm32l4x5_soc.h | 3 ---
> 3 files changed, 5 insertions(+), 41 deletions(-)
>
> diff --git a/hw/arm/b-l475e-iot01a.c b/hw/arm/b-l475e-iot01a.c
> index 6ecde2db15..d862aa43fc 100644
> --- a/hw/arm/b-l475e-iot01a.c
> +++ b/hw/arm/b-l475e-iot01a.c
> @@ -26,27 +26,19 @@
> #include "qapi/error.h"
> #include "hw/boards.h"
> #include "hw/qdev-properties.h"
> -#include "hw/qdev-clock.h"
> #include "qemu/error-report.h"
> #include "hw/arm/stm32l4x5_soc.h"
> #include "hw/arm/boot.h"
>
> -/* Main SYSCLK frequency in Hz (80MHz) */
> -#define MAIN_SYSCLK_FREQ_HZ 80000000ULL
> +/* B-L475E-IOT01A implementation is derived from netduinoplus2 */
>
> static void b_l475e_iot01a_init(MachineState *machine)
> {
> const Stm32l4x5SocClass *sc;
> DeviceState *dev;
> - Clock *sysclk;
> -
> - /* This clock doesn't need migration because it is fixed-frequency */
> - sysclk = clock_new(OBJECT(machine), "SYSCLK");
> - clock_set_hz(sysclk, MAIN_SYSCLK_FREQ_HZ);
>
> dev = qdev_new(TYPE_STM32L4X5XG_SOC);
> object_property_add_child(OBJECT(machine), "soc", OBJECT(dev));
> - qdev_connect_clock_in(dev, "sysclk", sysclk);
> sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
>
> sc = STM32L4X5_SOC_GET_CLASS(dev);
> diff --git a/hw/arm/stm32l4x5_soc.c b/hw/arm/stm32l4x5_soc.c
> index d5c04b446d..347a5377e5 100644
> --- a/hw/arm/stm32l4x5_soc.c
> +++ b/hw/arm/stm32l4x5_soc.c
> @@ -85,9 +85,6 @@ static void stm32l4x5_soc_initfn(Object *obj)
> object_initialize_child(obj, "exti", &s->exti, TYPE_STM32L4X5_EXTI);
> object_initialize_child(obj, "syscfg", &s->syscfg, TYPE_STM32L4X5_SYSCFG);
> object_initialize_child(obj, "rcc", &s->rcc, TYPE_STM32L4X5_RCC);
> -
> - s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
> - s->refclk = qdev_init_clock_in(DEVICE(s), "refclk", NULL, NULL, 0);
> }
>
> static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
> @@ -99,30 +96,6 @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
> DeviceState *armv7m;
> SysBusDevice *busdev;
>
> - /*
> - * We use s->refclk internally and only define it with qdev_init_clock_in()
> - * so it is correctly parented and not leaked on an init/deinit; it is not
> - * intended as an externally exposed clock.
> - */
> - if (clock_has_source(s->refclk)) {
> - error_setg(errp, "refclk clock must not be wired up by the board code");
> - return;
> - }
> -
> - if (!clock_has_source(s->sysclk)) {
> - error_setg(errp, "sysclk clock must be wired up by the board code");
> - return;
> - }
> -
> - /*
> - * TODO: ideally we should model the SoC RCC and its ability to
> - * change the sysclk frequency and define different sysclk sources.
> - */
> -
> - /* The refclk always runs at frequency HCLK / 8 */
> - clock_set_mul_div(s->refclk, 8, 1);
> - clock_set_source(s->refclk, s->sysclk);
> -
> if (!memory_region_init_rom(&s->flash, OBJECT(dev_soc), "flash",
> sc->flash_size, errp)) {
> return;
> @@ -152,8 +125,10 @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
> qdev_prop_set_uint32(armv7m, "num-prio-bits", 4);
> qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4"));
> qdev_prop_set_bit(armv7m, "enable-bitband", true);
> - qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
> - qdev_connect_clock_in(armv7m, "refclk", s->refclk);
> + qdev_connect_clock_in(armv7m, "cpuclk",
> + qdev_get_clock_out(DEVICE(&(s->rcc)), "cortex-fclk-out"));
> + qdev_connect_clock_in(armv7m, "refclk",
> + qdev_get_clock_out(DEVICE(&(s->rcc)), "cortex-refclk-out"));
> object_property_set_link(OBJECT(&s->armv7m), "memory",
> OBJECT(system_memory), &error_abort);
> if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) {
> diff --git a/include/hw/arm/stm32l4x5_soc.h b/include/hw/arm/stm32l4x5_soc.h
> index e480fcc976..1f71298b45 100644
> --- a/include/hw/arm/stm32l4x5_soc.h
> +++ b/include/hw/arm/stm32l4x5_soc.h
> @@ -50,9 +50,6 @@ struct Stm32l4x5SocState {
> MemoryRegion sram2;
> MemoryRegion flash;
> MemoryRegion flash_alias;
> -
> - Clock *sysclk;
> - Clock *refclk;
> };
>
> struct Stm32l4x5SocClass {
> --
> 2.34.1
>
>
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