Mechanical patch produced running the command documented
in scripts/coccinelle/cpu_env.cocci_template header.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/riscv/arch_dump.c | 6 ++----
target/riscv/cpu.c | 17 +++++------------
target/riscv/cpu_helper.c | 17 +++++------------
target/riscv/debug.c | 9 +++------
target/riscv/gdbstub.c | 6 ++----
target/riscv/kvm/kvm-cpu.c | 11 +++--------
target/riscv/tcg/tcg-cpu.c | 10 +++-------
target/riscv/translate.c | 6 ++----
8 files changed, 25 insertions(+), 57 deletions(-)
diff --git a/target/riscv/arch_dump.c b/target/riscv/arch_dump.c
index 434c8a3dbb..994709647f 100644
--- a/target/riscv/arch_dump.c
+++ b/target/riscv/arch_dump.c
@@ -68,8 +68,7 @@ int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
int cpuid, DumpState *s)
{
struct riscv64_note note;
- RISCVCPU *cpu = RISCV_CPU(cs);
- CPURISCVState *env = &cpu->env;
+ CPURISCVState *env = cpu_env(cs);
int ret, i = 0;
const char name[] = "CORE";
@@ -137,8 +136,7 @@ int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
int cpuid, DumpState *s)
{
struct riscv32_note note;
- RISCVCPU *cpu = RISCV_CPU(cs);
- CPURISCVState *env = &cpu->env;
+ CPURISCVState *env = cpu_env(cs);
int ret, i;
const char name[] = "CORE";
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1bd99bc5c6..8af4f7a088 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -419,8 +419,7 @@ static void riscv_any_cpu_init(Object *obj)
static void riscv_max_cpu_init(Object *obj)
{
- RISCVCPU *cpu = RISCV_CPU(obj);
- CPURISCVState *env = &cpu->env;
+ CPURISCVState *env = cpu_env(CPU(obj));
RISCVMXL mlx = MXL_RV64;
#ifdef TARGET_RISCV32
@@ -828,8 +827,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
static void riscv_cpu_set_pc(CPUState *cs, vaddr value)
{
- RISCVCPU *cpu = RISCV_CPU(cs);
- CPURISCVState *env = &cpu->env;
+ CPURISCVState *env = cpu_env(cs);
if (env->xl == MXL_RV32) {
env->pc = (int32_t)value;
@@ -840,8 +838,7 @@ static void riscv_cpu_set_pc(CPUState *cs, vaddr value)
static vaddr riscv_cpu_get_pc(CPUState *cs)
{
- RISCVCPU *cpu = RISCV_CPU(cs);
- CPURISCVState *env = &cpu->env;
+ CPURISCVState *env = cpu_env(cs);
/* Match cpu_get_tb_cpu_state. */
if (env->xl == MXL_RV32) {
@@ -853,8 +850,7 @@ static vaddr riscv_cpu_get_pc(CPUState *cs)
static bool riscv_cpu_has_work(CPUState *cs)
{
#ifndef CONFIG_USER_ONLY
- RISCVCPU *cpu = RISCV_CPU(cs);
- CPURISCVState *env = &cpu->env;
+ CPURISCVState *env = cpu_env(cs);
/*
* Definition of the WFI instruction requires it to ignore the privilege
* mode and delegation registers, but respect individual enables
@@ -1642,10 +1638,7 @@ static void rva22s64_profile_cpu_init(Object *obj)
static const gchar *riscv_gdb_arch_name(CPUState *cs)
{
- RISCVCPU *cpu = RISCV_CPU(cs);
- CPURISCVState *env = &cpu->env;
-
- switch (riscv_cpu_mxl(env)) {
+ switch (riscv_cpu_mxl(cpu_env(cs))) {
case MXL_RV32:
return "riscv:rv32";
case MXL_RV64:
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 791435d628..01b32a3f83 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -493,9 +493,7 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *env)
bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
if (interrupt_request & CPU_INTERRUPT_HARD) {
- RISCVCPU *cpu = RISCV_CPU(cs);
- CPURISCVState *env = &cpu->env;
- int interruptno = riscv_cpu_local_irq_pending(env);
+ int interruptno = riscv_cpu_local_irq_pending(cpu_env(cs));
if (interruptno >= 0) {
cs->exception_index = RISCV_EXCP_INT_FLAG | interruptno;
riscv_cpu_do_interrupt(cs);
@@ -1196,8 +1194,7 @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
{
- RISCVCPU *cpu = RISCV_CPU(cs);
- CPURISCVState *env = &cpu->env;
+ CPURISCVState *env = cpu_env(cs);
hwaddr phys_addr;
int prot;
int mmu_idx = cpu_mmu_index(env, false);
@@ -1223,8 +1220,7 @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
int mmu_idx, MemTxAttrs attrs,
MemTxResult response, uintptr_t retaddr)
{
- RISCVCPU *cpu = RISCV_CPU(cs);
- CPURISCVState *env = &cpu->env;
+ CPURISCVState *env = cpu_env(cs);
if (access_type == MMU_DATA_STORE) {
cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
@@ -1244,8 +1240,7 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
MMUAccessType access_type, int mmu_idx,
uintptr_t retaddr)
{
- RISCVCPU *cpu = RISCV_CPU(cs);
- CPURISCVState *env = &cpu->env;
+ CPURISCVState *env = cpu_env(cs);
switch (access_type) {
case MMU_INST_FETCH:
cs->exception_index = RISCV_EXCP_INST_ADDR_MIS;
@@ -1631,9 +1626,7 @@ static target_ulong riscv_transformed_insn(CPURISCVState *env,
void riscv_cpu_do_interrupt(CPUState *cs)
{
#if !defined(CONFIG_USER_ONLY)
-
- RISCVCPU *cpu = RISCV_CPU(cs);
- CPURISCVState *env = &cpu->env;
+ CPURISCVState *env = cpu_env(cs);
bool write_gva = false;
uint64_t s;
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index 4945d1a1f2..c8df9812be 100644
--- a/target/riscv/debug.c
+++ b/target/riscv/debug.c
@@ -757,8 +757,7 @@ target_ulong tinfo_csr_read(CPURISCVState *env)
void riscv_cpu_debug_excp_handler(CPUState *cs)
{
- RISCVCPU *cpu = RISCV_CPU(cs);
- CPURISCVState *env = &cpu->env;
+ CPURISCVState *env = cpu_env(cs);
if (cs->watchpoint_hit) {
if (cs->watchpoint_hit->flags & BP_CPU) {
@@ -773,8 +772,7 @@ void riscv_cpu_debug_excp_handler(CPUState *cs)
bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
{
- RISCVCPU *cpu = RISCV_CPU(cs);
- CPURISCVState *env = &cpu->env;
+ CPURISCVState *env = cpu_env(cs);
CPUBreakpoint *bp;
target_ulong ctrl;
target_ulong pc;
@@ -832,8 +830,7 @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
{
- RISCVCPU *cpu = RISCV_CPU(cs);
- CPURISCVState *env = &cpu->env;
+ CPURISCVState *env = cpu_env(cs);
target_ulong ctrl;
target_ulong addr;
int trigger_type;
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index 58b3ace0fe..999d815b34 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -49,8 +49,7 @@ static const struct TypeSize vec_lanes[] = {
int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{
- RISCVCPU *cpu = RISCV_CPU(cs);
- CPURISCVState *env = &cpu->env;
+ CPURISCVState *env = cpu_env(cs);
target_ulong tmp;
if (n < 32) {
@@ -75,8 +74,7 @@ int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
{
- RISCVCPU *cpu = RISCV_CPU(cs);
- CPURISCVState *env = &cpu->env;
+ CPURISCVState *env = cpu_env(cs);
int length = 0;
target_ulong tmp;
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index 680a729cd8..563b371ec9 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -171,9 +171,7 @@ static void kvm_cpu_get_misa_ext_cfg(Object *obj, Visitor *v,
{
KVMCPUConfig *misa_ext_cfg = opaque;
target_ulong misa_bit = misa_ext_cfg->offset;
- RISCVCPU *cpu = RISCV_CPU(obj);
- CPURISCVState *env = &cpu->env;
- bool value = env->misa_ext_mask & misa_bit;
+ bool value = cpu_env(CPU(obj))->misa_ext_mask & misa_bit;
visit_type_bool(v, name, &value, errp);
}
@@ -184,15 +182,13 @@ static void kvm_cpu_set_misa_ext_cfg(Object *obj, Visitor *v,
{
KVMCPUConfig *misa_ext_cfg = opaque;
target_ulong misa_bit = misa_ext_cfg->offset;
- RISCVCPU *cpu = RISCV_CPU(obj);
- CPURISCVState *env = &cpu->env;
bool value, host_bit;
if (!visit_type_bool(v, name, &value, errp)) {
return;
}
- host_bit = env->misa_ext_mask & misa_bit;
+ host_bit = cpu_env(CPU(obj))->misa_ext_mask & misa_bit;
if (value == host_bit) {
return;
@@ -1583,10 +1579,9 @@ static void kvm_cpu_instance_init(CPUState *cs)
*/
static bool kvm_cpu_realize(CPUState *cs, Error **errp)
{
- RISCVCPU *cpu = RISCV_CPU(cs);
int ret;
- if (riscv_has_ext(&cpu->env, RVV)) {
+ if (riscv_has_ext(cpu_env(cs), RVV)) {
ret = prctl(PR_RISCV_V_SET_CONTROL, PR_RISCV_V_VSTATE_CTRL_ON);
if (ret) {
error_setg(errp, "Error in prctl PR_RISCV_V_SET_CONTROL, code: %s",
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index 994ca1cdf9..e0f05d898c 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -92,8 +92,7 @@ static void riscv_cpu_synchronize_from_tb(CPUState *cs,
const TranslationBlock *tb)
{
if (!(tb_cflags(tb) & CF_PCREL)) {
- RISCVCPU *cpu = RISCV_CPU(cs);
- CPURISCVState *env = &cpu->env;
+ CPURISCVState *env = cpu_env(cs);
RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
@@ -110,8 +109,7 @@ static void riscv_restore_state_to_opc(CPUState *cs,
const TranslationBlock *tb,
const uint64_t *data)
{
- RISCVCPU *cpu = RISCV_CPU(cs);
- CPURISCVState *env = &cpu->env;
+ CPURISCVState *env = cpu_env(cs);
RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
target_ulong pc;
@@ -1030,11 +1028,9 @@ static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
{
const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque;
target_ulong misa_bit = misa_ext_cfg->misa_bit;
- RISCVCPU *cpu = RISCV_CPU(obj);
- CPURISCVState *env = &cpu->env;
bool value;
- value = env->misa_ext & misa_bit;
+ value = cpu_env(CPU(obj))->misa_ext & misa_bit;
visit_type_bool(v, name, &value, errp);
}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 071fbad7ef..24db9f3882 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1074,9 +1074,8 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
CPUState *cpu = ctx->cs;
- CPURISCVState *env = cpu_env(cpu);
- return cpu_ldl_code(env, pc);
+ return cpu_ldl_code(cpu_env(cpu), pc);
}
/* Include insn module translation function */
@@ -1265,8 +1264,7 @@ static void riscv_tr_disas_log(const DisasContextBase *dcbase,
CPUState *cpu, FILE *logfile)
{
#ifndef CONFIG_USER_ONLY
- RISCVCPU *rvcpu = RISCV_CPU(cpu);
- CPURISCVState *env = &rvcpu->env;
+ CPURISCVState *env = cpu_env(cpu);
#endif
fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first));
--
2.41.0
On Tue, Jan 30, 2024 at 2:52 AM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> Mechanical patch produced running the command documented
> in scripts/coccinelle/cpu_env.cocci_template header.
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/arch_dump.c | 6 ++----
> target/riscv/cpu.c | 17 +++++------------
> target/riscv/cpu_helper.c | 17 +++++------------
> target/riscv/debug.c | 9 +++------
> target/riscv/gdbstub.c | 6 ++----
> target/riscv/kvm/kvm-cpu.c | 11 +++--------
> target/riscv/tcg/tcg-cpu.c | 10 +++-------
> target/riscv/translate.c | 6 ++----
> 8 files changed, 25 insertions(+), 57 deletions(-)
>
> diff --git a/target/riscv/arch_dump.c b/target/riscv/arch_dump.c
> index 434c8a3dbb..994709647f 100644
> --- a/target/riscv/arch_dump.c
> +++ b/target/riscv/arch_dump.c
> @@ -68,8 +68,7 @@ int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
> int cpuid, DumpState *s)
> {
> struct riscv64_note note;
> - RISCVCPU *cpu = RISCV_CPU(cs);
> - CPURISCVState *env = &cpu->env;
> + CPURISCVState *env = cpu_env(cs);
> int ret, i = 0;
> const char name[] = "CORE";
>
> @@ -137,8 +136,7 @@ int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
> int cpuid, DumpState *s)
> {
> struct riscv32_note note;
> - RISCVCPU *cpu = RISCV_CPU(cs);
> - CPURISCVState *env = &cpu->env;
> + CPURISCVState *env = cpu_env(cs);
> int ret, i;
> const char name[] = "CORE";
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 1bd99bc5c6..8af4f7a088 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -419,8 +419,7 @@ static void riscv_any_cpu_init(Object *obj)
>
> static void riscv_max_cpu_init(Object *obj)
> {
> - RISCVCPU *cpu = RISCV_CPU(obj);
> - CPURISCVState *env = &cpu->env;
> + CPURISCVState *env = cpu_env(CPU(obj));
> RISCVMXL mlx = MXL_RV64;
>
> #ifdef TARGET_RISCV32
> @@ -828,8 +827,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
>
> static void riscv_cpu_set_pc(CPUState *cs, vaddr value)
> {
> - RISCVCPU *cpu = RISCV_CPU(cs);
> - CPURISCVState *env = &cpu->env;
> + CPURISCVState *env = cpu_env(cs);
>
> if (env->xl == MXL_RV32) {
> env->pc = (int32_t)value;
> @@ -840,8 +838,7 @@ static void riscv_cpu_set_pc(CPUState *cs, vaddr value)
>
> static vaddr riscv_cpu_get_pc(CPUState *cs)
> {
> - RISCVCPU *cpu = RISCV_CPU(cs);
> - CPURISCVState *env = &cpu->env;
> + CPURISCVState *env = cpu_env(cs);
>
> /* Match cpu_get_tb_cpu_state. */
> if (env->xl == MXL_RV32) {
> @@ -853,8 +850,7 @@ static vaddr riscv_cpu_get_pc(CPUState *cs)
> static bool riscv_cpu_has_work(CPUState *cs)
> {
> #ifndef CONFIG_USER_ONLY
> - RISCVCPU *cpu = RISCV_CPU(cs);
> - CPURISCVState *env = &cpu->env;
> + CPURISCVState *env = cpu_env(cs);
> /*
> * Definition of the WFI instruction requires it to ignore the privilege
> * mode and delegation registers, but respect individual enables
> @@ -1642,10 +1638,7 @@ static void rva22s64_profile_cpu_init(Object *obj)
>
> static const gchar *riscv_gdb_arch_name(CPUState *cs)
> {
> - RISCVCPU *cpu = RISCV_CPU(cs);
> - CPURISCVState *env = &cpu->env;
> -
> - switch (riscv_cpu_mxl(env)) {
> + switch (riscv_cpu_mxl(cpu_env(cs))) {
> case MXL_RV32:
> return "riscv:rv32";
> case MXL_RV64:
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 791435d628..01b32a3f83 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -493,9 +493,7 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *env)
> bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
> {
> if (interrupt_request & CPU_INTERRUPT_HARD) {
> - RISCVCPU *cpu = RISCV_CPU(cs);
> - CPURISCVState *env = &cpu->env;
> - int interruptno = riscv_cpu_local_irq_pending(env);
> + int interruptno = riscv_cpu_local_irq_pending(cpu_env(cs));
> if (interruptno >= 0) {
> cs->exception_index = RISCV_EXCP_INT_FLAG | interruptno;
> riscv_cpu_do_interrupt(cs);
> @@ -1196,8 +1194,7 @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
>
> hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
> {
> - RISCVCPU *cpu = RISCV_CPU(cs);
> - CPURISCVState *env = &cpu->env;
> + CPURISCVState *env = cpu_env(cs);
> hwaddr phys_addr;
> int prot;
> int mmu_idx = cpu_mmu_index(env, false);
> @@ -1223,8 +1220,7 @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
> int mmu_idx, MemTxAttrs attrs,
> MemTxResult response, uintptr_t retaddr)
> {
> - RISCVCPU *cpu = RISCV_CPU(cs);
> - CPURISCVState *env = &cpu->env;
> + CPURISCVState *env = cpu_env(cs);
>
> if (access_type == MMU_DATA_STORE) {
> cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
> @@ -1244,8 +1240,7 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
> MMUAccessType access_type, int mmu_idx,
> uintptr_t retaddr)
> {
> - RISCVCPU *cpu = RISCV_CPU(cs);
> - CPURISCVState *env = &cpu->env;
> + CPURISCVState *env = cpu_env(cs);
> switch (access_type) {
> case MMU_INST_FETCH:
> cs->exception_index = RISCV_EXCP_INST_ADDR_MIS;
> @@ -1631,9 +1626,7 @@ static target_ulong riscv_transformed_insn(CPURISCVState *env,
> void riscv_cpu_do_interrupt(CPUState *cs)
> {
> #if !defined(CONFIG_USER_ONLY)
> -
> - RISCVCPU *cpu = RISCV_CPU(cs);
> - CPURISCVState *env = &cpu->env;
> + CPURISCVState *env = cpu_env(cs);
> bool write_gva = false;
> uint64_t s;
>
> diff --git a/target/riscv/debug.c b/target/riscv/debug.c
> index 4945d1a1f2..c8df9812be 100644
> --- a/target/riscv/debug.c
> +++ b/target/riscv/debug.c
> @@ -757,8 +757,7 @@ target_ulong tinfo_csr_read(CPURISCVState *env)
>
> void riscv_cpu_debug_excp_handler(CPUState *cs)
> {
> - RISCVCPU *cpu = RISCV_CPU(cs);
> - CPURISCVState *env = &cpu->env;
> + CPURISCVState *env = cpu_env(cs);
>
> if (cs->watchpoint_hit) {
> if (cs->watchpoint_hit->flags & BP_CPU) {
> @@ -773,8 +772,7 @@ void riscv_cpu_debug_excp_handler(CPUState *cs)
>
> bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
> {
> - RISCVCPU *cpu = RISCV_CPU(cs);
> - CPURISCVState *env = &cpu->env;
> + CPURISCVState *env = cpu_env(cs);
> CPUBreakpoint *bp;
> target_ulong ctrl;
> target_ulong pc;
> @@ -832,8 +830,7 @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
>
> bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
> {
> - RISCVCPU *cpu = RISCV_CPU(cs);
> - CPURISCVState *env = &cpu->env;
> + CPURISCVState *env = cpu_env(cs);
> target_ulong ctrl;
> target_ulong addr;
> int trigger_type;
> diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
> index 58b3ace0fe..999d815b34 100644
> --- a/target/riscv/gdbstub.c
> +++ b/target/riscv/gdbstub.c
> @@ -49,8 +49,7 @@ static const struct TypeSize vec_lanes[] = {
>
> int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
> {
> - RISCVCPU *cpu = RISCV_CPU(cs);
> - CPURISCVState *env = &cpu->env;
> + CPURISCVState *env = cpu_env(cs);
> target_ulong tmp;
>
> if (n < 32) {
> @@ -75,8 +74,7 @@ int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
>
> int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
> {
> - RISCVCPU *cpu = RISCV_CPU(cs);
> - CPURISCVState *env = &cpu->env;
> + CPURISCVState *env = cpu_env(cs);
> int length = 0;
> target_ulong tmp;
>
> diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
> index 680a729cd8..563b371ec9 100644
> --- a/target/riscv/kvm/kvm-cpu.c
> +++ b/target/riscv/kvm/kvm-cpu.c
> @@ -171,9 +171,7 @@ static void kvm_cpu_get_misa_ext_cfg(Object *obj, Visitor *v,
> {
> KVMCPUConfig *misa_ext_cfg = opaque;
> target_ulong misa_bit = misa_ext_cfg->offset;
> - RISCVCPU *cpu = RISCV_CPU(obj);
> - CPURISCVState *env = &cpu->env;
> - bool value = env->misa_ext_mask & misa_bit;
> + bool value = cpu_env(CPU(obj))->misa_ext_mask & misa_bit;
>
> visit_type_bool(v, name, &value, errp);
> }
> @@ -184,15 +182,13 @@ static void kvm_cpu_set_misa_ext_cfg(Object *obj, Visitor *v,
> {
> KVMCPUConfig *misa_ext_cfg = opaque;
> target_ulong misa_bit = misa_ext_cfg->offset;
> - RISCVCPU *cpu = RISCV_CPU(obj);
> - CPURISCVState *env = &cpu->env;
> bool value, host_bit;
>
> if (!visit_type_bool(v, name, &value, errp)) {
> return;
> }
>
> - host_bit = env->misa_ext_mask & misa_bit;
> + host_bit = cpu_env(CPU(obj))->misa_ext_mask & misa_bit;
>
> if (value == host_bit) {
> return;
> @@ -1583,10 +1579,9 @@ static void kvm_cpu_instance_init(CPUState *cs)
> */
> static bool kvm_cpu_realize(CPUState *cs, Error **errp)
> {
> - RISCVCPU *cpu = RISCV_CPU(cs);
> int ret;
>
> - if (riscv_has_ext(&cpu->env, RVV)) {
> + if (riscv_has_ext(cpu_env(cs), RVV)) {
> ret = prctl(PR_RISCV_V_SET_CONTROL, PR_RISCV_V_VSTATE_CTRL_ON);
> if (ret) {
> error_setg(errp, "Error in prctl PR_RISCV_V_SET_CONTROL, code: %s",
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index 994ca1cdf9..e0f05d898c 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -92,8 +92,7 @@ static void riscv_cpu_synchronize_from_tb(CPUState *cs,
> const TranslationBlock *tb)
> {
> if (!(tb_cflags(tb) & CF_PCREL)) {
> - RISCVCPU *cpu = RISCV_CPU(cs);
> - CPURISCVState *env = &cpu->env;
> + CPURISCVState *env = cpu_env(cs);
> RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
>
> tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
> @@ -110,8 +109,7 @@ static void riscv_restore_state_to_opc(CPUState *cs,
> const TranslationBlock *tb,
> const uint64_t *data)
> {
> - RISCVCPU *cpu = RISCV_CPU(cs);
> - CPURISCVState *env = &cpu->env;
> + CPURISCVState *env = cpu_env(cs);
> RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
> target_ulong pc;
>
> @@ -1030,11 +1028,9 @@ static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
> {
> const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque;
> target_ulong misa_bit = misa_ext_cfg->misa_bit;
> - RISCVCPU *cpu = RISCV_CPU(obj);
> - CPURISCVState *env = &cpu->env;
> bool value;
>
> - value = env->misa_ext & misa_bit;
> + value = cpu_env(CPU(obj))->misa_ext & misa_bit;
>
> visit_type_bool(v, name, &value, errp);
> }
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 071fbad7ef..24db9f3882 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -1074,9 +1074,8 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
> {
> DisasContext *ctx = container_of(dcbase, DisasContext, base);
> CPUState *cpu = ctx->cs;
> - CPURISCVState *env = cpu_env(cpu);
>
> - return cpu_ldl_code(env, pc);
> + return cpu_ldl_code(cpu_env(cpu), pc);
> }
>
> /* Include insn module translation function */
> @@ -1265,8 +1264,7 @@ static void riscv_tr_disas_log(const DisasContextBase *dcbase,
> CPUState *cpu, FILE *logfile)
> {
> #ifndef CONFIG_USER_ONLY
> - RISCVCPU *rvcpu = RISCV_CPU(cpu);
> - CPURISCVState *env = &rvcpu->env;
> + CPURISCVState *env = cpu_env(cpu);
> #endif
>
> fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first));
> --
> 2.41.0
>
>
Hey Phil,
This patch is giving me a conflict in target/riscv/cpu_helper.c when applying
on top of master. Not sure if I'm missing any dependency.
It's a trivial conflict though, just a FYI. As for the patch:
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
On 1/29/24 13:45, Philippe Mathieu-Daudé wrote:
> Mechanical patch produced running the command documented
> in scripts/coccinelle/cpu_env.cocci_template header.
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> target/riscv/arch_dump.c | 6 ++----
> target/riscv/cpu.c | 17 +++++------------
> target/riscv/cpu_helper.c | 17 +++++------------
> target/riscv/debug.c | 9 +++------
> target/riscv/gdbstub.c | 6 ++----
> target/riscv/kvm/kvm-cpu.c | 11 +++--------
> target/riscv/tcg/tcg-cpu.c | 10 +++-------
> target/riscv/translate.c | 6 ++----
> 8 files changed, 25 insertions(+), 57 deletions(-)
>
> diff --git a/target/riscv/arch_dump.c b/target/riscv/arch_dump.c
> index 434c8a3dbb..994709647f 100644
> --- a/target/riscv/arch_dump.c
> +++ b/target/riscv/arch_dump.c
> @@ -68,8 +68,7 @@ int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
> int cpuid, DumpState *s)
> {
> struct riscv64_note note;
> - RISCVCPU *cpu = RISCV_CPU(cs);
> - CPURISCVState *env = &cpu->env;
> + CPURISCVState *env = cpu_env(cs);
> int ret, i = 0;
> const char name[] = "CORE";
>
> @@ -137,8 +136,7 @@ int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
> int cpuid, DumpState *s)
> {
> struct riscv32_note note;
> - RISCVCPU *cpu = RISCV_CPU(cs);
> - CPURISCVState *env = &cpu->env;
> + CPURISCVState *env = cpu_env(cs);
> int ret, i;
> const char name[] = "CORE";
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 1bd99bc5c6..8af4f7a088 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -419,8 +419,7 @@ static void riscv_any_cpu_init(Object *obj)
>
> static void riscv_max_cpu_init(Object *obj)
> {
> - RISCVCPU *cpu = RISCV_CPU(obj);
> - CPURISCVState *env = &cpu->env;
> + CPURISCVState *env = cpu_env(CPU(obj));
> RISCVMXL mlx = MXL_RV64;
>
> #ifdef TARGET_RISCV32
> @@ -828,8 +827,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
>
> static void riscv_cpu_set_pc(CPUState *cs, vaddr value)
> {
> - RISCVCPU *cpu = RISCV_CPU(cs);
> - CPURISCVState *env = &cpu->env;
> + CPURISCVState *env = cpu_env(cs);
>
> if (env->xl == MXL_RV32) {
> env->pc = (int32_t)value;
> @@ -840,8 +838,7 @@ static void riscv_cpu_set_pc(CPUState *cs, vaddr value)
>
> static vaddr riscv_cpu_get_pc(CPUState *cs)
> {
> - RISCVCPU *cpu = RISCV_CPU(cs);
> - CPURISCVState *env = &cpu->env;
> + CPURISCVState *env = cpu_env(cs);
>
> /* Match cpu_get_tb_cpu_state. */
> if (env->xl == MXL_RV32) {
> @@ -853,8 +850,7 @@ static vaddr riscv_cpu_get_pc(CPUState *cs)
> static bool riscv_cpu_has_work(CPUState *cs)
> {
> #ifndef CONFIG_USER_ONLY
> - RISCVCPU *cpu = RISCV_CPU(cs);
> - CPURISCVState *env = &cpu->env;
> + CPURISCVState *env = cpu_env(cs);
> /*
> * Definition of the WFI instruction requires it to ignore the privilege
> * mode and delegation registers, but respect individual enables
> @@ -1642,10 +1638,7 @@ static void rva22s64_profile_cpu_init(Object *obj)
>
> static const gchar *riscv_gdb_arch_name(CPUState *cs)
> {
> - RISCVCPU *cpu = RISCV_CPU(cs);
> - CPURISCVState *env = &cpu->env;
> -
> - switch (riscv_cpu_mxl(env)) {
> + switch (riscv_cpu_mxl(cpu_env(cs))) {
> case MXL_RV32:
> return "riscv:rv32";
> case MXL_RV64:
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 791435d628..01b32a3f83 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -493,9 +493,7 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *env)
> bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
> {
> if (interrupt_request & CPU_INTERRUPT_HARD) {
> - RISCVCPU *cpu = RISCV_CPU(cs);
> - CPURISCVState *env = &cpu->env;
> - int interruptno = riscv_cpu_local_irq_pending(env);
> + int interruptno = riscv_cpu_local_irq_pending(cpu_env(cs));
> if (interruptno >= 0) {
> cs->exception_index = RISCV_EXCP_INT_FLAG | interruptno;
> riscv_cpu_do_interrupt(cs);
> @@ -1196,8 +1194,7 @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
>
> hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
> {
> - RISCVCPU *cpu = RISCV_CPU(cs);
> - CPURISCVState *env = &cpu->env;
> + CPURISCVState *env = cpu_env(cs);
> hwaddr phys_addr;
> int prot;
> int mmu_idx = cpu_mmu_index(env, false);
> @@ -1223,8 +1220,7 @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
> int mmu_idx, MemTxAttrs attrs,
> MemTxResult response, uintptr_t retaddr)
> {
> - RISCVCPU *cpu = RISCV_CPU(cs);
> - CPURISCVState *env = &cpu->env;
> + CPURISCVState *env = cpu_env(cs);
>
> if (access_type == MMU_DATA_STORE) {
> cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
> @@ -1244,8 +1240,7 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
> MMUAccessType access_type, int mmu_idx,
> uintptr_t retaddr)
> {
> - RISCVCPU *cpu = RISCV_CPU(cs);
> - CPURISCVState *env = &cpu->env;
> + CPURISCVState *env = cpu_env(cs);
> switch (access_type) {
> case MMU_INST_FETCH:
> cs->exception_index = RISCV_EXCP_INST_ADDR_MIS;
> @@ -1631,9 +1626,7 @@ static target_ulong riscv_transformed_insn(CPURISCVState *env,
> void riscv_cpu_do_interrupt(CPUState *cs)
> {
> #if !defined(CONFIG_USER_ONLY)
> -
> - RISCVCPU *cpu = RISCV_CPU(cs);
> - CPURISCVState *env = &cpu->env;
> + CPURISCVState *env = cpu_env(cs);
> bool write_gva = false;
> uint64_t s;
>
> diff --git a/target/riscv/debug.c b/target/riscv/debug.c
> index 4945d1a1f2..c8df9812be 100644
> --- a/target/riscv/debug.c
> +++ b/target/riscv/debug.c
> @@ -757,8 +757,7 @@ target_ulong tinfo_csr_read(CPURISCVState *env)
>
> void riscv_cpu_debug_excp_handler(CPUState *cs)
> {
> - RISCVCPU *cpu = RISCV_CPU(cs);
> - CPURISCVState *env = &cpu->env;
> + CPURISCVState *env = cpu_env(cs);
>
> if (cs->watchpoint_hit) {
> if (cs->watchpoint_hit->flags & BP_CPU) {
> @@ -773,8 +772,7 @@ void riscv_cpu_debug_excp_handler(CPUState *cs)
>
> bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
> {
> - RISCVCPU *cpu = RISCV_CPU(cs);
> - CPURISCVState *env = &cpu->env;
> + CPURISCVState *env = cpu_env(cs);
> CPUBreakpoint *bp;
> target_ulong ctrl;
> target_ulong pc;
> @@ -832,8 +830,7 @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
>
> bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
> {
> - RISCVCPU *cpu = RISCV_CPU(cs);
> - CPURISCVState *env = &cpu->env;
> + CPURISCVState *env = cpu_env(cs);
> target_ulong ctrl;
> target_ulong addr;
> int trigger_type;
> diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
> index 58b3ace0fe..999d815b34 100644
> --- a/target/riscv/gdbstub.c
> +++ b/target/riscv/gdbstub.c
> @@ -49,8 +49,7 @@ static const struct TypeSize vec_lanes[] = {
>
> int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
> {
> - RISCVCPU *cpu = RISCV_CPU(cs);
> - CPURISCVState *env = &cpu->env;
> + CPURISCVState *env = cpu_env(cs);
> target_ulong tmp;
>
> if (n < 32) {
> @@ -75,8 +74,7 @@ int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
>
> int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
> {
> - RISCVCPU *cpu = RISCV_CPU(cs);
> - CPURISCVState *env = &cpu->env;
> + CPURISCVState *env = cpu_env(cs);
> int length = 0;
> target_ulong tmp;
>
> diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
> index 680a729cd8..563b371ec9 100644
> --- a/target/riscv/kvm/kvm-cpu.c
> +++ b/target/riscv/kvm/kvm-cpu.c
> @@ -171,9 +171,7 @@ static void kvm_cpu_get_misa_ext_cfg(Object *obj, Visitor *v,
> {
> KVMCPUConfig *misa_ext_cfg = opaque;
> target_ulong misa_bit = misa_ext_cfg->offset;
> - RISCVCPU *cpu = RISCV_CPU(obj);
> - CPURISCVState *env = &cpu->env;
> - bool value = env->misa_ext_mask & misa_bit;
> + bool value = cpu_env(CPU(obj))->misa_ext_mask & misa_bit;
>
> visit_type_bool(v, name, &value, errp);
> }
> @@ -184,15 +182,13 @@ static void kvm_cpu_set_misa_ext_cfg(Object *obj, Visitor *v,
> {
> KVMCPUConfig *misa_ext_cfg = opaque;
> target_ulong misa_bit = misa_ext_cfg->offset;
> - RISCVCPU *cpu = RISCV_CPU(obj);
> - CPURISCVState *env = &cpu->env;
> bool value, host_bit;
>
> if (!visit_type_bool(v, name, &value, errp)) {
> return;
> }
>
> - host_bit = env->misa_ext_mask & misa_bit;
> + host_bit = cpu_env(CPU(obj))->misa_ext_mask & misa_bit;
>
> if (value == host_bit) {
> return;
> @@ -1583,10 +1579,9 @@ static void kvm_cpu_instance_init(CPUState *cs)
> */
> static bool kvm_cpu_realize(CPUState *cs, Error **errp)
> {
> - RISCVCPU *cpu = RISCV_CPU(cs);
> int ret;
>
> - if (riscv_has_ext(&cpu->env, RVV)) {
> + if (riscv_has_ext(cpu_env(cs), RVV)) {
> ret = prctl(PR_RISCV_V_SET_CONTROL, PR_RISCV_V_VSTATE_CTRL_ON);
> if (ret) {
> error_setg(errp, "Error in prctl PR_RISCV_V_SET_CONTROL, code: %s",
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index 994ca1cdf9..e0f05d898c 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -92,8 +92,7 @@ static void riscv_cpu_synchronize_from_tb(CPUState *cs,
> const TranslationBlock *tb)
> {
> if (!(tb_cflags(tb) & CF_PCREL)) {
> - RISCVCPU *cpu = RISCV_CPU(cs);
> - CPURISCVState *env = &cpu->env;
> + CPURISCVState *env = cpu_env(cs);
> RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
>
> tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
> @@ -110,8 +109,7 @@ static void riscv_restore_state_to_opc(CPUState *cs,
> const TranslationBlock *tb,
> const uint64_t *data)
> {
> - RISCVCPU *cpu = RISCV_CPU(cs);
> - CPURISCVState *env = &cpu->env;
> + CPURISCVState *env = cpu_env(cs);
> RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
> target_ulong pc;
>
> @@ -1030,11 +1028,9 @@ static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
> {
> const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque;
> target_ulong misa_bit = misa_ext_cfg->misa_bit;
> - RISCVCPU *cpu = RISCV_CPU(obj);
> - CPURISCVState *env = &cpu->env;
> bool value;
>
> - value = env->misa_ext & misa_bit;
> + value = cpu_env(CPU(obj))->misa_ext & misa_bit;
>
> visit_type_bool(v, name, &value, errp);
> }
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 071fbad7ef..24db9f3882 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -1074,9 +1074,8 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
> {
> DisasContext *ctx = container_of(dcbase, DisasContext, base);
> CPUState *cpu = ctx->cs;
> - CPURISCVState *env = cpu_env(cpu);
>
> - return cpu_ldl_code(env, pc);
> + return cpu_ldl_code(cpu_env(cpu), pc);
> }
>
> /* Include insn module translation function */
> @@ -1265,8 +1264,7 @@ static void riscv_tr_disas_log(const DisasContextBase *dcbase,
> CPUState *cpu, FILE *logfile)
> {
> #ifndef CONFIG_USER_ONLY
> - RISCVCPU *rvcpu = RISCV_CPU(cpu);
> - CPURISCVState *env = &rvcpu->env;
> + CPURISCVState *env = cpu_env(cpu);
> #endif
>
> fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first));
On 29/1/24 22:53, Daniel Henrique Barboza wrote: > Hey Phil, > > This patch is giving me a conflict in target/riscv/cpu_helper.c when > applying > on top of master. Not sure if I'm missing any dependency. My 'master' was commit 7a1dc45af5. > It's a trivial conflict though, just a FYI. As for the patch: > > > Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Thanks!
© 2016 - 2024 Red Hat, Inc.