This patch series adds cache structure table generation for the Processor
Properties Topology Table (PPTT) to describe cache hierarchy information
for ACPI guests. Both ARM and RISC-V virtual machines benefit from these
enhancement.

A 3-level cache topology is employed here, referring to the type 1 cache
structure according to ACPI spec v6.3. The L1 cache and L2 cache are
private resources for the core, while the L3 cache is the private
resource for the cluster.

In the absence of cluster values in the QEMU command, a 2-layer cache is
expected. The default cache value should be passed in from the
architecture code.

Examples:
3-layer: -smp 4,sockets=1,clusters=2,cores=2,threads=1
2-layer: -smp 4,sockets=1,cores=2,threads=2

Sia Jee Heng (3):
  hw/acpi/aml-build: Add cache structure table creation for PPTT table
  hw/riscv/virt-acpi-build.c: Generate PPTT table
  hw/arm/virt-acpi-build.c: Enable CPU cache topology

 hw/acpi/aml-build.c         | 65 ++++++++++++++++++++++++++++++++++---
 hw/arm/virt-acpi-build.c    | 44 ++++++++++++++++++++++++-
 hw/riscv/virt-acpi-build.c  | 49 +++++++++++++++++++++++++++-
 hw/riscv/virt.c             |  1 +
 include/hw/acpi/aml-build.h | 26 ++++++++++++++-
 5 files changed, 177 insertions(+), 8 deletions(-)


base-commit: 7a1dc45af581d2b643cdbf33c01fd96271616fbd
-- 
2.34.1