From: Yao Zi <ziyao@disroot.org>

Clang on LoongArch only accepts fp register names in the dollar-prefixed

form, while GCC allows omitting the dollar. Change registers in ASM

clobbers to the dollar-prefixed form to make user emulators buildable

with Clang on loongarch64. No functional change invovled.

Cc: qemu-stable@nongnu.org

Fixes: adc8467e697 ("host/include/loongarch64: Add atomic16 load and store")

Signed-off-by: Yao Zi <ziyao@disroot.org>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Bibo Mao <maobibo@loongson.cn>

Signed-off-by: Bibo Mao <maobibo@loongson.cn>

---

host/include/loongarch64/host/atomic128-ldst.h.inc | 4 ++--

host/include/loongarch64/host/bufferiszero.c.inc | 6 ++++--

host/include/loongarch64/host/load-extract-al16-al8.h.inc | 2 +-

3 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/host/include/loongarch64/host/atomic128-ldst.h.inc b/host/include/loongarch64/host/atomic128-ldst.h.inc

index XXXXXXX..XXXXXXX 100644

--- a/host/include/loongarch64/host/atomic128-ldst.h.inc

+++ b/host/include/loongarch64/host/atomic128-ldst.h.inc

@@ -XXX,XX +XXX,XX @@ static inline Int128 atomic16_read_ro(const Int128 *ptr)

asm("vld $vr0, %2, 0\n\t"

"vpickve2gr.d %0, $vr0, 0\n\t"

"vpickve2gr.d %1, $vr0, 1"

-    : "=r"(l), "=r"(h) : "r"(ptr), "m"(*ptr) : "f0");

+ : "=r"(l), "=r"(h) : "r"(ptr), "m"(*ptr) : "$f0");

return int128_make128(l, h);

}

@@ -XXX,XX +XXX,XX @@ static inline void atomic16_set(Int128 *ptr, Int128 val)

asm("vinsgr2vr.d $vr0, %1, 0\n\t"

"vinsgr2vr.d $vr0, %2, 1\n\t"

"vst $vr0, %3, 0"

-    : "=m"(*ptr) : "r"(l), "r"(h), "r"(ptr) : "f0");

+ : "=m"(*ptr) : "r"(l), "r"(h), "r"(ptr) : "$f0");

}

#endif /* LOONGARCH_ATOMIC128_LDST_H */

diff --git a/host/include/loongarch64/host/bufferiszero.c.inc b/host/include/loongarch64/host/bufferiszero.c.inc

index XXXXXXX..XXXXXXX 100644

--- a/host/include/loongarch64/host/bufferiszero.c.inc

+++ b/host/include/loongarch64/host/bufferiszero.c.inc

@@ -XXX,XX +XXX,XX @@ static bool buffer_is_zero_lsx(const void *buf, size_t len)

"2:"

: "=&r"(ret), "+r"(p)

: "r"(buf), "r"(e), "r"(l)

- : "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "fcc0");

+ : "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", "$f8",

+ "$fcc0");

return ret;

}

@@ -XXX,XX +XXX,XX @@ static bool buffer_is_zero_lasx(const void *buf, size_t len)

"3:"

: "=&r"(ret), "+r"(p)

: "r"(buf), "r"(e), "r"(l)

- : "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "fcc0");

+ : "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", "$f8",

+ "$fcc0");

return ret;

}

diff --git a/host/include/loongarch64/host/load-extract-al16-al8.h.inc b/host/include/loongarch64/host/load-extract-al16-al8.h.inc

index XXXXXXX..XXXXXXX 100644

--- a/host/include/loongarch64/host/load-extract-al16-al8.h.inc

+++ b/host/include/loongarch64/host/load-extract-al16-al8.h.inc

@@ -XXX,XX +XXX,XX @@ static inline uint64_t load_atom_extract_al16_or_al8(void *pv, int s)

asm("vld $vr0, %2, 0\n\t"

"vpickve2gr.d %0, $vr0, 0\n\t"

"vpickve2gr.d %1, $vr0, 1"

-    : "=r"(l), "=r"(h) : "r"(ptr_align), "m"(*ptr_align) : "f0");

+ : "=r"(l), "=r"(h) : "r"(ptr_align), "m"(*ptr_align) : "$f0");

return (l >> shr) | (h << (-shr & 63));

}

--

2.43.5

Add index entry for LoongArch system and do some small modification

with LoongArch document with rst syntax.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>

Reviewed-by: Song Gao <gaosong@loongson.cn>

---

docs/system/loongarch/virt.rst | 31 ++++++++++---------------------

docs/system/target-loongarch.rst | 19 +++++++++++++++++++

docs/system/targets.rst | 1 +

3 files changed, 30 insertions(+), 21 deletions(-)

create mode 100644 docs/system/target-loongarch.rst

diff --git a/docs/system/loongarch/virt.rst b/docs/system/loongarch/virt.rst

index XXXXXXX..XXXXXXX 100644

--- a/docs/system/loongarch/virt.rst

+++ b/docs/system/loongarch/virt.rst

@@ -XXX,XX +XXX,XX @@ Supported devices

-----------------

The ``virt`` machine supports:

-- Gpex host bridge

-- Ls7a RTC device

-- Ls7a IOAPIC device

-- ACPI GED device

-- Fw_cfg device

-- PCI/PCIe devices

-- Memory device

-- CPU device. Type: la464.

+

+* Gpex host bridge

+* Ls7a RTC device

+* Ls7a IOAPIC device

+* ACPI GED device

+* Fw_cfg device

+* PCI/PCIe devices

+* Memory device

+* CPU device. Type: la464.

CPU and machine Type

--------------------

@@ -XXX,XX +XXX,XX @@ can be accessed by following steps.

.. code-block:: bash

- ./configure --disable-rdma --prefix=/usr \

- --target-list="loongarch64-softmmu" \

- --disable-libiscsi --disable-libnfs --disable-libpmem \

- --disable-glusterfs --enable-libusb --enable-usb-redir \

- --disable-opengl --disable-xen --enable-spice \

- --enable-debug --disable-capstone --disable-kvm \

- --enable-profiler

+ ./configure --target-list="loongarch64-softmmu"

make -j8

(2) Set cross tools:

@@ -XXX,XX +XXX,XX @@ can be accessed by following steps.

.. code-block:: bash

wget https://github.com/loongson/build-tools/releases/download/2022.09.06/loongarch64-clfs-6.3-cross-tools-gcc-glibc.tar.xz

-

tar -vxf loongarch64-clfs-6.3-cross-tools-gcc-glibc.tar.xz -C /opt

-

export PATH=/opt/cross-tools/bin:$PATH

export LD_LIBRARY_PATH=/opt/cross-tools/lib:$LD_LIBRARY_PATH

export LD_LIBRARY_PATH=/opt/cross-tools/loongarch64-unknown-linux-gnu/lib/:$LD_LIBRARY_PATH

@@ -XXX,XX +XXX,XX @@ Note: To build the release version of the bios, set --buildtarget=RELEASE,

.. code-block:: bash

git clone https://github.com/loongson/linux.git

-

cd linux

-

git checkout loongarch-next

-

make ARCH=loongarch CROSS_COMPILE=loongarch64-unknown-linux-gnu- loongson3_defconfig

-

make ARCH=loongarch CROSS_COMPILE=loongarch64-unknown-linux-gnu- -j32

Note: The branch of linux source code is loongarch-next.

diff --git a/docs/system/target-loongarch.rst b/docs/system/target-loongarch.rst

new file mode 100644

index XXXXXXX..XXXXXXX

--- /dev/null

+++ b/docs/system/target-loongarch.rst

@@ -XXX,XX +XXX,XX @@

+.. _LoongArch-System-emulator:

+

+LoongArch System emulator

+-------------------------

+

+QEMU can emulate loongArch 64 bit systems via the

+``qemu-system-loongarch64`` binary. Only one machine type ``virt`` is

+supported.

+

+When using KVM as accelerator, QEMU can emulate la464 cpu model. And when

+using the default cpu model with TCG as accelerator, QEMU will emulate a

+subset of la464 cpu features that should be enough to run distributions

+built for the la464.

+

+Board-specific documentation

+============================

+

+.. toctree::

+ loongarch/virt

diff --git a/docs/system/targets.rst b/docs/system/targets.rst

index XXXXXXX..XXXXXXX 100644

--- a/docs/system/targets.rst

+++ b/docs/system/targets.rst

@@ -XXX,XX +XXX,XX @@ Contents:

target-arm

target-avr

+ target-loongarch

target-m68k

target-mips

target-ppc

--

2.43.5

From: Song Gao <gaosong@loongson.cn>

In expression 1ULL << tlb_ps, left shifting by more than 63 bits has

undefined behavior. The shift amount, tlb_ps, is as much as 64. check

"tlb_ps >=64" to fix.

Resolves: Coverity CID 1593475

Fixes: d882c284a3 ("target/loongarch: check tlb_ps")

Suggested-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Song Gao <gaosong@loongson.cn>

Reviewed-by: Bibo Mao <maobibo@loongson.cn>

Signed-off-by: Bibo Mao <maobibo@loongson.cn>

---

target/loongarch/internals.h | 2 +-

target/loongarch/tcg/csr_helper.c | 2 +-

target/loongarch/tcg/tlb_helper.c | 10 +++++-----

3 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/target/loongarch/internals.h b/target/loongarch/internals.h

index XXXXXXX..XXXXXXX 100644

--- a/target/loongarch/internals.h

+++ b/target/loongarch/internals.h

@@ -XXX,XX +XXX,XX @@ enum {

TLBRET_PE = 7,

};

-bool check_ps(CPULoongArchState *ent, int ps);

+bool check_ps(CPULoongArchState *ent, uint8_t ps);

extern const VMStateDescription vmstate_loongarch_cpu;

diff --git a/target/loongarch/tcg/csr_helper.c b/target/loongarch/tcg/csr_helper.c

index XXXXXXX..XXXXXXX 100644

--- a/target/loongarch/tcg/csr_helper.c

+++ b/target/loongarch/tcg/csr_helper.c

@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrwr_ticlr(CPULoongArchState *env, target_ulong val)

target_ulong helper_csrwr_pwcl(CPULoongArchState *env, target_ulong val)

{

- int shift, ptbase;

+ uint8_t shift, ptbase;

int64_t old_v = env->CSR_PWCL;

/*

diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c

index XXXXXXX..XXXXXXX 100644

--- a/target/loongarch/tcg/tlb_helper.c

+++ b/target/loongarch/tcg/tlb_helper.c

@@ -XXX,XX +XXX,XX @@

#include "exec/log.h"

#include "cpu-csr.h"

-bool check_ps(CPULoongArchState *env, int tlb_ps)

+bool check_ps(CPULoongArchState *env, uint8_t tlb_ps)

{

- if (tlb_ps > 64) {

- return false;

- }

- return BIT_ULL(tlb_ps) & (env->CSR_PRCFG2);

+ if (tlb_ps >= 64) {

+ return false;

+ }

+ return BIT_ULL(tlb_ps) & (env->CSR_PRCFG2);

}

void get_dir_base_width(CPULoongArchState *env, uint64_t *dir_base,

--

2.43.5