This patch adds a new device STM32L4x5 GPIO device and is part
of a series implementing the STM32L4x5 with a few peripherals.
Changes from v1 :
- replacing test GPIO register `DISCONNECTED_PINS` with an object
property accessed using `qtest_qmp()` in the qtest (through helpers
`get_disconnected_pins()` and `disconnect_all_pins()`)
- removing GPIO subclasses and storing MODER, OSPEEDR and PUPDR reset
values in properties
- adding a `name` property and using it for more lisible traces
- using `g_strdup_printf()` to facilitate setting irqs in the qtest,
and initializing GPIO children in soc_initfn
Changes from RFC v1 :
- `stm32l4x5-gpio-test.c` : correct typos, make the test generic,
add a test for bitwise writing in register ODR
- `stm32l4x5_soc.c` : connect gpios to their clock, use an
array of GpioState
- `stm32l4x5_gpio.c` : correct comments in `update_gpio_idr()`,
correct `get_gpio_pins_to_disconnect()`, correct `stm32l4x5_gpio_init()`
and initialize the clock, add a realize function
- update MAINAINERS
Based-on: 20240118091107.87831-1-arnaud.minier@telecom-paris.fr
([PATCH v2 0/7] Add device STM32L4x5 RCC)
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Inès Varhol (3):
hw/gpio: Implement STM32L4x5 GPIO
hw/arm: Connect STM32L4x5 GPIO to STM32L4x5 SoC
tests/qtest: Add STM32L4x5 GPIO QTest testcase
MAINTAINERS | 1 +
docs/system/arm/b-l475e-iot01a.rst | 2 +-
hw/arm/Kconfig | 3 +-
hw/arm/stm32l4x5_soc.c | 79 ++++-
hw/gpio/Kconfig | 3 +
hw/gpio/meson.build | 1 +
hw/gpio/stm32l4x5_gpio.c | 447 +++++++++++++++++++++++++
hw/gpio/trace-events | 6 +
include/hw/arm/stm32l4x5_soc.h | 2 +
include/hw/gpio/stm32l4x5_gpio.h | 65 ++++
tests/qtest/meson.build | 3 +-
tests/qtest/stm32l4x5_gpio-test.c | 520 +++++++++++++++++++++++++++++
12 files changed, 1115 insertions(+), 17 deletions(-)
create mode 100644 hw/gpio/stm32l4x5_gpio.c
create mode 100644 include/hw/gpio/stm32l4x5_gpio.h
create mode 100644 tests/qtest/stm32l4x5_gpio-test.c
--
2.43.0