This is mostly TCG core emulation improvements and fixes. I
got the chiptod model in there because it's intertwined with
TFMR SPR.

Other non-TCG patches are spapr MSR entry point change which
goes together with the other machine check / MSR[ME] fixes.
And Saif's gdb patches, as well as some SPR renaming.

Will probably a bit more similar patches too, e.g., Dan's SPR
patches, but I'll just get this out for review before
upstreaming it.

Thanks,
Nick

Glenn Miles (4):
  target/ppc: Add new hflags to support BHRB
  target/ppc: Add recording of taken branches to BHRB
  target/ppc: Add clrbhrb and mfbhrbe instructions
  target/ppc: Add migration support for BHRB

Nicholas Piggin (21):
  target/ppc: Fix crash on machine check caused by ifetch
  target/ppc: Prevent supervisor from modifying MSR[ME]
  spapr: set MSR[ME] and MSR[FP] on client entry
  target/ppc: Rename registers to match ISA
  target/ppc: Rename TBL to TB on 64-bit
  target/ppc: Improve timebase register defines naming
  target/ppc: Fix move-to timebase SPR access permissions
  pnv/chiptod: Add POWER9/10 chiptod model
  ppc/pnv: Wire ChipTOD model to powernv9 and powernv10 machines
  pnv/chiptod: Implement the ChipTOD to Core transfer
  target/ppc: Implement core timebase state machine and TFMR
  target/ppc: Add SMT support to time facilities
  target/ppc: BookE DECAR SPR is 32-bit
  target/ppc: Wire up BookE ATB registers for e500 family
  target/ppc: Add PPR32 SPR
  target/ppc: add helper to write per-LPAR SPRs
  target/ppc: Add SMT support to simple SPRs
  target/ppc: Add SMT support to PTCR SPR
  target/ppc: Implement LDBAR, TTR SPRs
  target/ppc: Implement SPRC/SPRD SPRs
  target/ppc: add SMT support to msgsnd broadcast

Saif Abrar (1):
  target/ppc: Update gdbstub to read SPR's CFAR, DEC, HDEC, TB-L/U

 include/hw/ppc/pnv.h                          |   2 +
 include/hw/ppc/pnv_chip.h                     |   3 +
 include/hw/ppc/pnv_chiptod.h                  |  53 ++
 include/hw/ppc/pnv_xscom.h                    |   9 +
 target/ppc/cpu.h                              |  97 ++-
 target/ppc/helper.h                           |  13 +-
 target/ppc/power8-pmu.h                       |  11 +-
 target/ppc/spr_common.h                       |   8 +
 target/ppc/insn32.decode                      |   8 +
 hw/ppc/pnv.c                                  |  45 ++
 hw/ppc/pnv_chiptod.c                          | 586 ++++++++++++++++++
 hw/ppc/spapr_cpu_core.c                       |   2 +
 target/ppc/cpu_init.c                         | 124 +++-
 target/ppc/excp_helper.c                      |  89 ++-
 target/ppc/gdbstub.c                          |  40 +-
 target/ppc/helper_regs.c                      |  83 ++-
 target/ppc/machine.c                          |  23 +-
 target/ppc/misc_helper.c                      | 132 +++-
 target/ppc/power8-pmu.c                       |  48 +-
 target/ppc/ppc-qmp-cmds.c                     |   4 +
 target/ppc/timebase_helper.c                  | 309 ++++++++-
 target/ppc/translate.c                        | 207 ++++++-
 target/ppc/power8-pmu-regs.c.inc              |   5 +
 target/ppc/translate/bhrb-impl.c.inc          |  43 ++
 target/ppc/translate/branch-impl.c.inc        |   2 +-
 .../ppc/translate/processor-ctrl-impl.c.inc   |   2 +-
 hw/ppc/meson.build                            |   1 +
 hw/ppc/trace-events                           |   4 +
 28 files changed, 1855 insertions(+), 98 deletions(-)
 create mode 100644 include/hw/ppc/pnv_chiptod.h
 create mode 100644 hw/ppc/pnv_chiptod.c
 create mode 100644 target/ppc/translate/bhrb-impl.c.inc

-- 
2.42.0

Hello Nick,

On 1/18/24 16:06, Nicholas Piggin wrote:
> This is mostly TCG core emulation improvements and fixes. I
> got the chiptod model in there because it's intertwined with
> TFMR SPR.
> 
> Other non-TCG patches are spapr MSR entry point change which
> goes together with the other machine check / MSR[ME] fixes.
> And Saif's gdb patches, as well as some SPR renaming.
> 
> Will probably a bit more similar patches too, e.g., Dan's SPR
> patches, but I'll just get this out for review before
> upstreaming it.

Before we start a new round of reviews, could we please uptream the ones
reviewed in the previous cycle [1] ? Some are part of this series and we
shoudn't have to go through them again.

Thanks,

C.

[1] https://patchwork.ozlabs.org/project/qemu-ppc/list/

On Fri Jan 19, 2024 at 6:58 PM AEST, Cédric Le Goater wrote:
> Hello Nick,
>
> On 1/18/24 16:06, Nicholas Piggin wrote:
> > This is mostly TCG core emulation improvements and fixes. I
> > got the chiptod model in there because it's intertwined with
> > TFMR SPR.
> > 
> > Other non-TCG patches are spapr MSR entry point change which
> > goes together with the other machine check / MSR[ME] fixes.
> > And Saif's gdb patches, as well as some SPR renaming.
> > 
> > Will probably a bit more similar patches too, e.g., Dan's SPR
> > patches, but I'll just get this out for review before
> > upstreaming it.
>
> Before we start a new round of reviews, could we please uptream the ones
> reviewed in the previous cycle [1] ? Some are part of this series and we
> shoudn't have to go through them again.

Yeah good idea, will do.

Thanks,
Nick