[v2] Export debug triggers as an extension

[PATCH v2 0/2] Export debug triggers as an extension

Himanshu Chauhan posted 2 patches 8 months, 1 week ago

Diff against v1 v3
Download series mbox

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git fetch https://github.com/patchew-project/qemu tags/patchew/20240117142412.1615505-1-hchauhan@ventanamicro.com

Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Bin Meng <bin.meng@windriver.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>

There is a newer version of this series

target/riscv/cpu.c        | 8 ++++----
target/riscv/cpu_cfg.h    | 2 +-
target/riscv/cpu_helper.c | 2 +-
target/riscv/csr.c        | 2 +-
target/riscv/machine.c    | 2 +-
5 files changed, 8 insertions(+), 8 deletions(-)

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[PATCH v2 0/2] Export debug triggers as an extension

Posted by Himanshu Chauhan 8 months, 1 week ago

All the CPUs may or may not implement the debug trigger (sdtrig)
extension. The presence of it should be dynamically detectable.
This patch exports the debug triggers as an extension which
can be turned on or off by x-sdtrig=<true/false> option. It is
turned on by default.

"x-sdtrig" is concatenated to ISA string when it is enabled.
Like so:
rv64imafdch_zicbom_*_x-sdtrig_*_sstc_svadu

Changes from v1:
   - Replaced the debug property with ext_sdtrig
   - Marked it experimenatal by naming it x-sdtrig
   - x-sdtrig is added to ISA string
   - Reversed the patch order

Himanshu Chauhan (2):
  target/riscv: Convert sdtrig functionality from property to an
    extension
  target/riscv: Export sdtrig in ISA string

 target/riscv/cpu.c        | 8 ++++----
 target/riscv/cpu_cfg.h    | 2 +-
 target/riscv/cpu_helper.c | 2 +-
 target/riscv/csr.c        | 2 +-
 target/riscv/machine.c    | 2 +-
 5 files changed, 8 insertions(+), 8 deletions(-)

-- 
2.34.1