[v3] target/riscv: add 'cpu->cfg.vlenb', remove 'cpu->cfg.vlen'

[PATCH v3 08/13] target/riscv/vector_helper.c: use vlenb in HELPER(vsetvl)

Posted by Daniel Henrique Barboza 8 months, 1 week ago

Use the new 'vlenb' CPU config to validate fractional LMUL. The original
comparison is done with 'vlen' and 'sew', both in bits. Adjust the shift
to use vlenb.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/riscv/vector_helper.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index cb944229b0..b13be1541a 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -45,9 +45,16 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
                                             xlen - 1 - R_VTYPE_RESERVED_SHIFT);
 
     if (lmul & 4) {
-        /* Fractional LMUL - check LMUL * VLEN >= SEW */
+        /*
+         * Fractional LMUL, check:
+         *
+         * VLEN * LMUL >= SEW
+         * VLEN >> (8 - lmul) >= sew
+         * (vlenb << 3) >> (8 - lmul) >= sew
+         * vlenb >> (8 - 3 - lmul) >= sew
+         */
         if (lmul == 4 ||
-            cpu->cfg.vlen >> (8 - lmul) < sew) {
+            cpu->cfg.vlenb >> (8 - 3 - lmul) < sew) {
             vill = true;
         }
     }
-- 
2.43.0

Re: [PATCH v3 08/13] target/riscv/vector_helper.c: use vlenb in HELPER(vsetvl)

Posted by Alistair Francis 8 months ago

On Wed, Jan 17, 2024 at 7:02 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> Use the new 'vlenb' CPU config to validate fractional LMUL. The original
> comparison is done with 'vlen' and 'sew', both in bits. Adjust the shift
> to use vlenb.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/vector_helper.c | 11 +++++++++--
>  1 file changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index cb944229b0..b13be1541a 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -45,9 +45,16 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
>                                              xlen - 1 - R_VTYPE_RESERVED_SHIFT);
>
>      if (lmul & 4) {
> -        /* Fractional LMUL - check LMUL * VLEN >= SEW */
> +        /*
> +         * Fractional LMUL, check:
> +         *
> +         * VLEN * LMUL >= SEW
> +         * VLEN >> (8 - lmul) >= sew
> +         * (vlenb << 3) >> (8 - lmul) >= sew
> +         * vlenb >> (8 - 3 - lmul) >= sew
> +         */
>          if (lmul == 4 ||
> -            cpu->cfg.vlen >> (8 - lmul) < sew) {
> +            cpu->cfg.vlenb >> (8 - 3 - lmul) < sew) {
>              vill = true;
>          }
>      }
> --
> 2.43.0
>
>