[PATCH v3 06/13] target/riscv/insn_trans/trans_rvvk.c.inc: use 'vlenb'

Daniel Henrique Barboza posted 13 patches 9 months, 4 weeks ago
[PATCH v3 06/13] target/riscv/insn_trans/trans_rvvk.c.inc: use 'vlenb'
Posted by Daniel Henrique Barboza 9 months, 4 weeks ago
Use s->cfg_ptr->vlenb instead of s->cfg_ptr->vlen / 8.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/riscv/insn_trans/trans_rvvk.c.inc | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_trans/trans_rvvk.c.inc
index 3801c16829..a5cdd1b67f 100644
--- a/target/riscv/insn_trans/trans_rvvk.c.inc
+++ b/target/riscv/insn_trans/trans_rvvk.c.inc
@@ -174,7 +174,7 @@ GEN_OPIVX_GVEC_TRANS_CHECK(vandn_vx, andcs, zvkb_vx_check)
             data = FIELD_DP32(data, VDATA, VMA, s->vma);                   \
             tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),         \
                                vreg_ofs(s, a->rs2), tcg_env,               \
-                               s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, \
+                               s->cfg_ptr->vlenb, s->cfg_ptr->vlenb,       \
                                data, fns[s->sew]);                         \
             mark_vs_dirty(s);                                              \
             gen_set_label(over);                                           \
@@ -267,7 +267,7 @@ GEN_OPIVI_WIDEN_TRANS(vwsll_vi, IMM_ZX, vwsll_vx, vwsll_vx_check)
             rd_v = tcg_temp_new_ptr();                                        \
             rs2_v = tcg_temp_new_ptr();                                       \
             desc = tcg_constant_i32(                                          \
-                simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data)); \
+                simd_desc(s->cfg_ptr->vlenb, s->cfg_ptr->vlenb, data));       \
             tcg_gen_addi_ptr(rd_v, tcg_env, vreg_ofs(s, a->rd));              \
             tcg_gen_addi_ptr(rs2_v, tcg_env, vreg_ofs(s, a->rs2));            \
             gen_helper_##NAME(rd_v, rs2_v, tcg_env, desc);                    \
@@ -345,7 +345,7 @@ GEN_V_UNMASKED_TRANS(vaesem_vs, vaes_check_vs, ZVKNED_EGS)
             rs2_v = tcg_temp_new_ptr();                                       \
             uimm_v = tcg_constant_i32(a->rs1);                                \
             desc = tcg_constant_i32(                                          \
-                simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data)); \
+                simd_desc(s->cfg_ptr->vlenb, s->cfg_ptr->vlenb, data));       \
             tcg_gen_addi_ptr(rd_v, tcg_env, vreg_ofs(s, a->rd));              \
             tcg_gen_addi_ptr(rs2_v, tcg_env, vreg_ofs(s, a->rs2));            \
             gen_helper_##NAME(rd_v, rs2_v, uimm_v, tcg_env, desc);            \
@@ -413,7 +413,7 @@ GEN_VI_UNMASKED_TRANS(vaeskf2_vi, vaeskf2_check, ZVKNED_EGS)
                                                                               \
             tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1),       \
                                vreg_ofs(s, a->rs2), tcg_env,                  \
-                               s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8,    \
+                               s->cfg_ptr->vlenb, s->cfg_ptr->vlenb,          \
                                data, gen_helper_##NAME);                      \
                                                                               \
             mark_vs_dirty(s);                                                 \
@@ -466,8 +466,8 @@ static bool trans_vsha2cl_vv(DisasContext *s, arg_rmrr *a)
         data = FIELD_DP32(data, VDATA, VMA, s->vma);
 
         tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1),
-            vreg_ofs(s, a->rs2), tcg_env, s->cfg_ptr->vlen / 8,
-            s->cfg_ptr->vlen / 8, data,
+            vreg_ofs(s, a->rs2), tcg_env, s->cfg_ptr->vlenb,
+            s->cfg_ptr->vlenb, data,
             s->sew == MO_32 ?
                 gen_helper_vsha2cl32_vv : gen_helper_vsha2cl64_vv);
 
@@ -500,8 +500,8 @@ static bool trans_vsha2ch_vv(DisasContext *s, arg_rmrr *a)
         data = FIELD_DP32(data, VDATA, VMA, s->vma);
 
         tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1),
-            vreg_ofs(s, a->rs2), tcg_env, s->cfg_ptr->vlen / 8,
-            s->cfg_ptr->vlen / 8, data,
+            vreg_ofs(s, a->rs2), tcg_env, s->cfg_ptr->vlenb,
+            s->cfg_ptr->vlenb, data,
             s->sew == MO_32 ?
                 gen_helper_vsha2ch32_vv : gen_helper_vsha2ch64_vv);
 
-- 
2.43.0
Re: [PATCH v3 06/13] target/riscv/insn_trans/trans_rvvk.c.inc: use 'vlenb'
Posted by Alistair Francis 9 months, 3 weeks ago
On Wed, Jan 17, 2024 at 7:01 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> Use s->cfg_ptr->vlenb instead of s->cfg_ptr->vlen / 8.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/insn_trans/trans_rvvk.c.inc | 16 ++++++++--------
>  1 file changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_trans/trans_rvvk.c.inc
> index 3801c16829..a5cdd1b67f 100644
> --- a/target/riscv/insn_trans/trans_rvvk.c.inc
> +++ b/target/riscv/insn_trans/trans_rvvk.c.inc
> @@ -174,7 +174,7 @@ GEN_OPIVX_GVEC_TRANS_CHECK(vandn_vx, andcs, zvkb_vx_check)
>              data = FIELD_DP32(data, VDATA, VMA, s->vma);                   \
>              tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),         \
>                                 vreg_ofs(s, a->rs2), tcg_env,               \
> -                               s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, \
> +                               s->cfg_ptr->vlenb, s->cfg_ptr->vlenb,       \
>                                 data, fns[s->sew]);                         \
>              mark_vs_dirty(s);                                              \
>              gen_set_label(over);                                           \
> @@ -267,7 +267,7 @@ GEN_OPIVI_WIDEN_TRANS(vwsll_vi, IMM_ZX, vwsll_vx, vwsll_vx_check)
>              rd_v = tcg_temp_new_ptr();                                        \
>              rs2_v = tcg_temp_new_ptr();                                       \
>              desc = tcg_constant_i32(                                          \
> -                simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data)); \
> +                simd_desc(s->cfg_ptr->vlenb, s->cfg_ptr->vlenb, data));       \
>              tcg_gen_addi_ptr(rd_v, tcg_env, vreg_ofs(s, a->rd));              \
>              tcg_gen_addi_ptr(rs2_v, tcg_env, vreg_ofs(s, a->rs2));            \
>              gen_helper_##NAME(rd_v, rs2_v, tcg_env, desc);                    \
> @@ -345,7 +345,7 @@ GEN_V_UNMASKED_TRANS(vaesem_vs, vaes_check_vs, ZVKNED_EGS)
>              rs2_v = tcg_temp_new_ptr();                                       \
>              uimm_v = tcg_constant_i32(a->rs1);                                \
>              desc = tcg_constant_i32(                                          \
> -                simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data)); \
> +                simd_desc(s->cfg_ptr->vlenb, s->cfg_ptr->vlenb, data));       \
>              tcg_gen_addi_ptr(rd_v, tcg_env, vreg_ofs(s, a->rd));              \
>              tcg_gen_addi_ptr(rs2_v, tcg_env, vreg_ofs(s, a->rs2));            \
>              gen_helper_##NAME(rd_v, rs2_v, uimm_v, tcg_env, desc);            \
> @@ -413,7 +413,7 @@ GEN_VI_UNMASKED_TRANS(vaeskf2_vi, vaeskf2_check, ZVKNED_EGS)
>                                                                                \
>              tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1),       \
>                                 vreg_ofs(s, a->rs2), tcg_env,                  \
> -                               s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8,    \
> +                               s->cfg_ptr->vlenb, s->cfg_ptr->vlenb,          \
>                                 data, gen_helper_##NAME);                      \
>                                                                                \
>              mark_vs_dirty(s);                                                 \
> @@ -466,8 +466,8 @@ static bool trans_vsha2cl_vv(DisasContext *s, arg_rmrr *a)
>          data = FIELD_DP32(data, VDATA, VMA, s->vma);
>
>          tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1),
> -            vreg_ofs(s, a->rs2), tcg_env, s->cfg_ptr->vlen / 8,
> -            s->cfg_ptr->vlen / 8, data,
> +            vreg_ofs(s, a->rs2), tcg_env, s->cfg_ptr->vlenb,
> +            s->cfg_ptr->vlenb, data,
>              s->sew == MO_32 ?
>                  gen_helper_vsha2cl32_vv : gen_helper_vsha2cl64_vv);
>
> @@ -500,8 +500,8 @@ static bool trans_vsha2ch_vv(DisasContext *s, arg_rmrr *a)
>          data = FIELD_DP32(data, VDATA, VMA, s->vma);
>
>          tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1),
> -            vreg_ofs(s, a->rs2), tcg_env, s->cfg_ptr->vlen / 8,
> -            s->cfg_ptr->vlen / 8, data,
> +            vreg_ofs(s, a->rs2), tcg_env, s->cfg_ptr->vlenb,
> +            s->cfg_ptr->vlenb, data,
>              s->sew == MO_32 ?
>                  gen_helper_vsha2ch32_vv : gen_helper_vsha2ch64_vv);
>
> --
> 2.43.0
>
>