[PULL 0/4] tcg patch queue
[PATCH v3 00/28] tcg patch queue
1
The following changes since commit 34eac35f893664eb8545b98142e23d9954722766:
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v3: One more try to fix macos issues.
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Merge tag 'pull-riscv-to-apply-20240110' of https://github.com/alistair23/qemu into staging (2024-01-10 11:41:56 +0000)
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r~
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6
7
8
The following changes since commit e0209297cddd5e10a07e15fac5cca7aa1a8e0e59:
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10
Merge tag 'pull-ufs-20250217' of https://gitlab.com/jeuk20.kim/qemu into staging (2025-02-18 10:58:48 +0800)
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11
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are available in the Git repository at:
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are available in the Git repository at:
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13
7
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20240111
14
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20250215-3
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15
9
for you to fetch changes up to 1d513e06d96697f44de4a1b85c6ff627c443e306:
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for you to fetch changes up to e726f65867087d86436de05e9f372a86ec1381a6:
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11
util: fix build with musl libc on ppc64le (2024-01-11 08:48:16 +1100)
18
tcg: Remove TCG_TARGET_HAS_{br,set}cond2 from riscv and loongarch64 (2025-02-18 08:29:03 -0800)
12
19
13
----------------------------------------------------------------
20
----------------------------------------------------------------
14
tcg/i386: Use more 8-bit immediate forms for add, sub, or, xor
21
tcg: Remove last traces of TCG_TARGET_NEED_POOL_LABELS
15
tcg/ppc: Use new registers for LQ destination
22
tcg: Cleanups after disallowing 64-on-32
16
util: fix build with musl libc on ppc64le
23
tcg: Introduce constraint for zero register
24
tcg: Remove TCG_TARGET_HAS_{br,set}cond2 from riscv and loongarch64
25
tcg/i386: Use tcg_{high,unsigned}_cond in tcg_out_brcond2
26
linux-user: Move TARGET_SA_RESTORER out of generic/signal.h
27
linux-user: Fix alignment when unmapping excess reservation
28
target/sparc: Fix register selection for all F*TOx and FxTO* instructions
29
target/sparc: Fix gdbstub incorrectly handling registers f32-f62
30
target/sparc: fake UltraSPARC T1 PCR and PIC registers
17
31
18
----------------------------------------------------------------
32
----------------------------------------------------------------
19
Natanael Copa (1):
33
Andreas Schwab (1):
20
util: fix build with musl libc on ppc64le
34
linux-user: Move TARGET_SA_RESTORER out of generic/signal.h
21
35
22
Paolo Bonzini (2):
36
Artyom Tarasenko (1):
23
tcg/i386: convert add/sub of 128 to sub/add of -128
37
target/sparc: fake UltraSPARC T1 PCR and PIC registers
24
tcg/i386: use 8-bit OR or XOR for unsigned 8-bit immediates
25
38
26
Richard Henderson (1):
39
Fabiano Rosas (1):
27
tcg/ppc: Use new registers for LQ destination
40
elfload: Fix alignment when unmapping excess reservation
28
41
29
tcg/ppc/tcg-target-con-set.h | 2 +-
42
Mikael Szreder (2):
30
tcg/tcg.c | 21 ++++++++++++----
43
target/sparc: Fix register selection for all F*TOx and FxTO* instructions
31
util/cpuinfo-ppc.c | 6 ++---
44
target/sparc: Fix gdbstub incorrectly handling registers f32-f62
32
tcg/i386/tcg-target.c.inc | 60 +++++++++++++++++++++++++++++++++-----------
45
33
tcg/ppc/tcg-target.c.inc | 3 ++-
46
Richard Henderson (23):
34
5 files changed, 67 insertions(+), 25 deletions(-)
47
tcg: Remove last traces of TCG_TARGET_NEED_POOL_LABELS
48
tcg: Remove TCG_OVERSIZED_GUEST
49
tcg: Drop support for two address registers in gen_ldst
50
tcg: Merge INDEX_op_qemu_*_{a32,a64}_*
51
tcg/arm: Drop addrhi from prepare_host_addr
52
tcg/i386: Drop addrhi from prepare_host_addr
53
tcg/mips: Drop addrhi from prepare_host_addr
54
tcg/ppc: Drop addrhi from prepare_host_addr
55
tcg: Replace addr{lo,hi}_reg with addr_reg in TCGLabelQemuLdst
56
plugins: Fix qemu_plugin_read_memory_vaddr parameters
57
accel/tcg: Fix tlb_set_page_with_attrs, tlb_set_page
58
target/loongarch: Use VADDR_PRIx for logging pc_next
59
target/mips: Use VADDR_PRIx for logging pc_next
60
include/exec: Change vaddr to uintptr_t
61
include/exec: Use uintptr_t in CPUTLBEntry
62
tcg: Introduce the 'z' constraint for a hardware zero register
63
tcg/aarch64: Use 'z' constraint
64
tcg/loongarch64: Use 'z' constraint
65
tcg/mips: Use 'z' constraint
66
tcg/riscv: Use 'z' constraint
67
tcg/sparc64: Use 'z' constraint
68
tcg/i386: Use tcg_{high,unsigned}_cond in tcg_out_brcond2
69
tcg: Remove TCG_TARGET_HAS_{br,set}cond2 from riscv and loongarch64
70
71
include/exec/tlb-common.h | 10 +-
72
include/exec/vaddr.h | 16 +-
73
include/qemu/atomic.h | 18 +-
74
include/tcg/oversized-guest.h | 23 ---
75
include/tcg/tcg-opc.h | 28 +--
76
include/tcg/tcg.h | 3 +-
77
linux-user/aarch64/target_signal.h | 2 +
78
linux-user/arm/target_signal.h | 2 +
79
linux-user/generic/signal.h | 1 -
80
linux-user/i386/target_signal.h | 2 +
81
linux-user/m68k/target_signal.h | 1 +
82
linux-user/microblaze/target_signal.h | 2 +
83
linux-user/ppc/target_signal.h | 2 +
84
linux-user/s390x/target_signal.h | 2 +
85
linux-user/sh4/target_signal.h | 2 +
86
linux-user/x86_64/target_signal.h | 2 +
87
linux-user/xtensa/target_signal.h | 2 +
88
tcg/aarch64/tcg-target-con-set.h | 12 +-
89
tcg/aarch64/tcg-target.h | 2 +
90
tcg/loongarch64/tcg-target-con-set.h | 15 +-
91
tcg/loongarch64/tcg-target-con-str.h | 1 -
92
tcg/loongarch64/tcg-target-has.h | 2 -
93
tcg/loongarch64/tcg-target.h | 2 +
94
tcg/mips/tcg-target-con-set.h | 26 +--
95
tcg/mips/tcg-target-con-str.h | 1 -
96
tcg/mips/tcg-target.h | 2 +
97
tcg/riscv/tcg-target-con-set.h | 10 +-
98
tcg/riscv/tcg-target-con-str.h | 1 -
99
tcg/riscv/tcg-target-has.h | 2 -
100
tcg/riscv/tcg-target.h | 2 +
101
tcg/sparc64/tcg-target-con-set.h | 12 +-
102
tcg/sparc64/tcg-target-con-str.h | 1 -
103
tcg/sparc64/tcg-target.h | 3 +-
104
tcg/tci/tcg-target.h | 1 -
105
accel/tcg/cputlb.c | 32 +---
106
accel/tcg/tcg-all.c | 9 +-
107
linux-user/elfload.c | 4 +-
108
plugins/api.c | 2 +-
109
target/arm/ptw.c | 34 ----
110
target/loongarch/tcg/translate.c | 2 +-
111
target/mips/tcg/octeon_translate.c | 4 +-
112
target/riscv/cpu_helper.c | 13 +-
113
target/sparc/gdbstub.c | 18 +-
114
target/sparc/translate.c | 19 +++
115
tcg/optimize.c | 21 +--
116
tcg/tcg-op-ldst.c | 103 +++--------
117
tcg/tcg.c | 97 +++++------
118
tcg/tci.c | 119 +++----------
119
docs/devel/multi-thread-tcg.rst | 1 -
120
docs/devel/tcg-ops.rst | 4 +-
121
target/loongarch/tcg/insn_trans/trans_atomic.c.inc | 2 +-
122
target/sparc/insns.decode | 19 ++-
123
tcg/aarch64/tcg-target.c.inc | 86 ++++------
124
tcg/arm/tcg-target.c.inc | 114 ++++---------
125
tcg/i386/tcg-target.c.inc | 190 +++++----------------
126
tcg/loongarch64/tcg-target.c.inc | 72 +++-----
127
tcg/mips/tcg-target.c.inc | 169 ++++++------------
128
tcg/ppc/tcg-target.c.inc | 164 +++++-------------
129
tcg/riscv/tcg-target.c.inc | 56 +++---
130
tcg/s390x/tcg-target.c.inc | 40 ++---
131
tcg/sparc64/tcg-target.c.inc | 45 ++---
132
tcg/tci/tcg-target.c.inc | 60 ++-----
133
62 files changed, 550 insertions(+), 1162 deletions(-)
134
delete mode 100644 include/tcg/oversized-guest.h
diff view generated by jsdifflib
[PULL 1/4] tcg/i386: convert add/sub of 128 to sub/add of -128
Deleted patch
1
From: Paolo Bonzini <pbonzini@redhat.com>
2
1
3
Extend the existing conditional that generates INC/DEC, to also swap an
4
ADD for a SUB and vice versa when the immediate is 128. This facilitates
5
using OPC_ARITH_EvIb instead of OPC_ARITH_EvIz.
6
7
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
8
Message-Id: <20231228120514.70205-1-pbonzini@redhat.com>
9
[rth: Use a switch on C]
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
---
12
tcg/i386/tcg-target.c.inc | 49 +++++++++++++++++++++++++++------------
13
1 file changed, 34 insertions(+), 15 deletions(-)
14
15
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
16
index XXXXXXX..XXXXXXX 100644
17
--- a/tcg/i386/tcg-target.c.inc
18
+++ b/tcg/i386/tcg-target.c.inc
19
@@ -XXX,XX +XXX,XX @@ static void tgen_arithi(TCGContext *s, int c, int r0,
20
c &= 7;
21
}
22
23
- /* ??? While INC is 2 bytes shorter than ADDL $1, they also induce
24
- partial flags update stalls on Pentium4 and are not recommended
25
- by current Intel optimization manuals. */
26
- if (!cf && (c == ARITH_ADD || c == ARITH_SUB) && (val == 1 || val == -1)) {
27
- int is_inc = (c == ARITH_ADD) ^ (val < 0);
28
- if (TCG_TARGET_REG_BITS == 64) {
29
- /* The single-byte increment encodings are re-tasked as the
30
- REX prefixes. Use the MODRM encoding. */
31
- tcg_out_modrm(s, OPC_GRP5 + rexw,
32
- (is_inc ? EXT5_INC_Ev : EXT5_DEC_Ev), r0);
33
- } else {
34
- tcg_out8(s, (is_inc ? OPC_INC_r32 : OPC_DEC_r32) + r0);
35
+ switch (c) {
36
+ case ARITH_ADD:
37
+ case ARITH_SUB:
38
+ if (!cf) {
39
+ /*
40
+ * ??? While INC is 2 bytes shorter than ADDL $1, they also induce
41
+ * partial flags update stalls on Pentium4 and are not recommended
42
+ * by current Intel optimization manuals.
43
+ */
44
+ if (val == 1 || val == -1) {
45
+ int is_inc = (c == ARITH_ADD) ^ (val < 0);
46
+ if (TCG_TARGET_REG_BITS == 64) {
47
+ /*
48
+ * The single-byte increment encodings are re-tasked
49
+ * as the REX prefixes. Use the MODRM encoding.
50
+ */
51
+ tcg_out_modrm(s, OPC_GRP5 + rexw,
52
+ (is_inc ? EXT5_INC_Ev : EXT5_DEC_Ev), r0);
53
+ } else {
54
+ tcg_out8(s, (is_inc ? OPC_INC_r32 : OPC_DEC_r32) + r0);
55
+ }
56
+ return;
57
+ }
58
+ if (val == 128) {
59
+ /*
60
+ * Facilitate using an 8-bit immediate. Carry is inverted
61
+ * by this transformation, so do it only if cf == 0.
62
+ */
63
+ c ^= ARITH_ADD ^ ARITH_SUB;
64
+ val = -128;
65
+ }
66
}
67
- return;
68
- }
69
+ break;
70
71
- if (c == ARITH_AND) {
72
+ case ARITH_AND:
73
if (TCG_TARGET_REG_BITS == 64) {
74
if (val == 0xffffffffu) {
75
tcg_out_ext32u(s, r0, r0);
76
@@ -XXX,XX +XXX,XX @@ static void tgen_arithi(TCGContext *s, int c, int r0,
77
tcg_out_ext16u(s, r0, r0);
78
return;
79
}
80
+ break;
81
}
82
83
if (val == (int8_t)val) {
84
--
85
2.34.1
diff view generated by jsdifflib
[PULL 2/4] tcg/i386: use 8-bit OR or XOR for unsigned 8-bit immediates
Deleted patch
1
From: Paolo Bonzini <pbonzini@redhat.com>
2
1
3
In the case where OR or XOR has an 8-bit immediate between 128 and 255,
4
we can operate on a low-byte register and shorten the output by two or
5
three bytes (two if a prefix byte is needed for REX.B).
6
7
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
8
Message-Id: <20231228120524.70239-1-pbonzini@redhat.com>
9
[rth: Incorporate into switch.]
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
---
12
tcg/i386/tcg-target.c.inc | 11 +++++++++++
13
1 file changed, 11 insertions(+)
14
15
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
16
index XXXXXXX..XXXXXXX 100644
17
--- a/tcg/i386/tcg-target.c.inc
18
+++ b/tcg/i386/tcg-target.c.inc
19
@@ -XXX,XX +XXX,XX @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct, int vece)
20
#define P_VEXL 0x80000 /* Set VEX.L = 1 */
21
#define P_EVEX 0x100000 /* Requires EVEX encoding */
22
23
+#define OPC_ARITH_EbIb    (0x80)
24
#define OPC_ARITH_EvIz    (0x81)
25
#define OPC_ARITH_EvIb    (0x83)
26
#define OPC_ARITH_GvEv    (0x03)        /* ... plus (ARITH_FOO << 3) */
27
@@ -XXX,XX +XXX,XX @@ static void tgen_arithi(TCGContext *s, int c, int r0,
28
return;
29
}
30
break;
31
+
32
+ case ARITH_OR:
33
+ case ARITH_XOR:
34
+ if (val >= 0x80 && val <= 0xff
35
+ && (r0 < 4 || TCG_TARGET_REG_BITS == 64)) {
36
+ tcg_out_modrm(s, OPC_ARITH_EbIb + P_REXB_RM, c, r0);
37
+ tcg_out8(s, val);
38
+ return;
39
+ }
40
+ break;
41
}
42
43
if (val == (int8_t)val) {
44
--
45
2.34.1
diff view generated by jsdifflib
[PULL 3/4] tcg/ppc: Use new registers for LQ destination
Deleted patch
1
LQ has a constraint that RTp != RA, else SIGILL.
2
Therefore, force the destination of INDEX_op_qemu_*_ld128 to be a
3
new register pair, so that it cannot overlap the input address.
4
1
5
This requires new support in process_op_defs and tcg_reg_alloc_op.
6
7
Cc: qemu-stable@nongnu.org
8
Fixes: 526cd4ec01f ("tcg/ppc: Support 128-bit load/store")
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
Message-Id: <20240102013456.131846-1-richard.henderson@linaro.org>
11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
---
13
tcg/ppc/tcg-target-con-set.h | 2 +-
14
tcg/tcg.c | 21 ++++++++++++++++-----
15
tcg/ppc/tcg-target.c.inc | 3 ++-
16
3 files changed, 19 insertions(+), 7 deletions(-)
17
18
diff --git a/tcg/ppc/tcg-target-con-set.h b/tcg/ppc/tcg-target-con-set.h
19
index XXXXXXX..XXXXXXX 100644
20
--- a/tcg/ppc/tcg-target-con-set.h
21
+++ b/tcg/ppc/tcg-target-con-set.h
22
@@ -XXX,XX +XXX,XX @@ C_O1_I3(v, v, v, v)
23
C_O1_I4(r, r, ri, rZ, rZ)
24
C_O1_I4(r, r, r, ri, ri)
25
C_O2_I1(r, r, r)
26
-C_O2_I1(o, m, r)
27
+C_N1O1_I1(o, m, r)
28
C_O2_I2(r, r, r, r)
29
C_O2_I4(r, r, rI, rZM, r, r)
30
C_O2_I4(r, r, r, r, rI, rZM)
31
diff --git a/tcg/tcg.c b/tcg/tcg.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/tcg/tcg.c
34
+++ b/tcg/tcg.c
35
@@ -XXX,XX +XXX,XX @@ static void tcg_out_movext3(TCGContext *s, const TCGMovExtend *i1,
36
#define C_O1_I4(O1, I1, I2, I3, I4) C_PFX5(c_o1_i4_, O1, I1, I2, I3, I4),
37
38
#define C_N1_I2(O1, I1, I2) C_PFX3(c_n1_i2_, O1, I1, I2),
39
+#define C_N1O1_I1(O1, O2, I1) C_PFX3(c_n1o1_i1_, O1, O2, I1),
40
#define C_N2_I1(O1, O2, I1) C_PFX3(c_n2_i1_, O1, O2, I1),
41
42
#define C_O2_I1(O1, O2, I1) C_PFX3(c_o2_i1_, O1, O2, I1),
43
@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode);
44
#undef C_O1_I3
45
#undef C_O1_I4
46
#undef C_N1_I2
47
+#undef C_N1O1_I1
48
#undef C_N2_I1
49
#undef C_O2_I1
50
#undef C_O2_I2
51
@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode);
52
#define C_O1_I4(O1, I1, I2, I3, I4) { .args_ct_str = { #O1, #I1, #I2, #I3, #I4 } },
53
54
#define C_N1_I2(O1, I1, I2) { .args_ct_str = { "&" #O1, #I1, #I2 } },
55
+#define C_N1O1_I1(O1, O2, I1) { .args_ct_str = { "&" #O1, #O2, #I1 } },
56
#define C_N2_I1(O1, O2, I1) { .args_ct_str = { "&" #O1, "&" #O2, #I1 } },
57
58
#define C_O2_I1(O1, O2, I1) { .args_ct_str = { #O1, #O2, #I1 } },
59
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef constraint_sets[] = {
60
#undef C_O1_I3
61
#undef C_O1_I4
62
#undef C_N1_I2
63
+#undef C_N1O1_I1
64
#undef C_N2_I1
65
#undef C_O2_I1
66
#undef C_O2_I2
67
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef constraint_sets[] = {
68
#define C_O1_I4(O1, I1, I2, I3, I4) C_PFX5(c_o1_i4_, O1, I1, I2, I3, I4)
69
70
#define C_N1_I2(O1, I1, I2) C_PFX3(c_n1_i2_, O1, I1, I2)
71
+#define C_N1O1_I1(O1, O2, I1) C_PFX3(c_n1o1_i1_, O1, O2, I1)
72
#define C_N2_I1(O1, O2, I1) C_PFX3(c_n2_i1_, O1, O2, I1)
73
74
#define C_O2_I1(O1, O2, I1) C_PFX3(c_o2_i1_, O1, O2, I1)
75
@@ -XXX,XX +XXX,XX @@ static void process_op_defs(TCGContext *s)
76
.pair = 2,
77
.pair_index = o,
78
.regs = def->args_ct[o].regs << 1,
79
+ .newreg = def->args_ct[o].newreg,
80
};
81
def->args_ct[o].pair = 1;
82
def->args_ct[o].pair_index = i;
83
@@ -XXX,XX +XXX,XX @@ static void process_op_defs(TCGContext *s)
84
.pair = 1,
85
.pair_index = o,
86
.regs = def->args_ct[o].regs >> 1,
87
+ .newreg = def->args_ct[o].newreg,
88
};
89
def->args_ct[o].pair = 2;
90
def->args_ct[o].pair_index = i;
91
@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
92
break;
93
94
case 1: /* first of pair */
95
- tcg_debug_assert(!arg_ct->newreg);
96
if (arg_ct->oalias) {
97
reg = new_args[arg_ct->alias_index];
98
- break;
99
+ } else if (arg_ct->newreg) {
100
+ reg = tcg_reg_alloc_pair(s, arg_ct->regs,
101
+ i_allocated_regs | o_allocated_regs,
102
+ output_pref(op, k),
103
+ ts->indirect_base);
104
+ } else {
105
+ reg = tcg_reg_alloc_pair(s, arg_ct->regs, o_allocated_regs,
106
+ output_pref(op, k),
107
+ ts->indirect_base);
108
}
109
- reg = tcg_reg_alloc_pair(s, arg_ct->regs, o_allocated_regs,
110
- output_pref(op, k), ts->indirect_base);
111
break;
112
113
case 2: /* second of pair */
114
- tcg_debug_assert(!arg_ct->newreg);
115
if (arg_ct->oalias) {
116
reg = new_args[arg_ct->alias_index];
117
} else {
118
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
119
index XXXXXXX..XXXXXXX 100644
120
--- a/tcg/ppc/tcg-target.c.inc
121
+++ b/tcg/ppc/tcg-target.c.inc
122
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ldst_i128(TCGContext *s, TCGReg datalo, TCGReg datahi,
123
tcg_debug_assert(!need_bswap);
124
tcg_debug_assert(datalo & 1);
125
tcg_debug_assert(datahi == datalo - 1);
126
+ tcg_debug_assert(!is_ld || datahi != index);
127
insn = is_ld ? LQ : STQ;
128
tcg_out32(s, insn | TAI(datahi, index, 0));
129
} else {
130
@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
131
132
case INDEX_op_qemu_ld_a32_i128:
133
case INDEX_op_qemu_ld_a64_i128:
134
- return C_O2_I1(o, m, r);
135
+ return C_N1O1_I1(o, m, r);
136
case INDEX_op_qemu_st_a32_i128:
137
case INDEX_op_qemu_st_a64_i128:
138
return C_O0_I3(o, m, r);
139
--
140
2.34.1
141
142
diff view generated by jsdifflib
[PULL 4/4] util: fix build with musl libc on ppc64le
[PATCH v3 13/28] target/mips: Use VADDR_PRIx for logging pc_next
1
From: Natanael Copa <ncopa@alpinelinux.org>
1
DisasContextBase.pc_next has type vaddr; use the correct log format.
2
2
3
Use PPC_FEATURE2_ISEL and PPC_FEATURE2_VEC_CRYPTO from linux headers
3
Fixes: 85c19af63e7 ("include/exec: Use vaddr in DisasContextBase for virtual addresses")
4
instead of the GNU specific PPC_FEATURE2_HAS_ISEL and
5
PPC_FEATURE2_HAS_VEC_CRYPTO. This fixes build with musl libc.
6
7
Cc: qemu-stable@nongnu.org
8
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1861
9
Signed-off-by: Natanael Copa <ncopa@alpinelinux.org>
10
Fixes: 63922f467a ("tcg/ppc: Replace HAVE_ISEL macro with a variable")
11
Fixes: 68f340d4cd ("tcg/ppc: Enable Altivec detection")
12
Message-Id: <20231219105236.7059-1-ncopa@alpinelinux.org>
13
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14
---
5
---
15
util/cpuinfo-ppc.c | 6 +++---
6
target/mips/tcg/octeon_translate.c | 4 ++--
16
1 file changed, 3 insertions(+), 3 deletions(-)
7
1 file changed, 2 insertions(+), 2 deletions(-)
17
8
18
diff --git a/util/cpuinfo-ppc.c b/util/cpuinfo-ppc.c
9
diff --git a/target/mips/tcg/octeon_translate.c b/target/mips/tcg/octeon_translate.c
19
index XXXXXXX..XXXXXXX 100644
10
index XXXXXXX..XXXXXXX 100644
20
--- a/util/cpuinfo-ppc.c
11
--- a/target/mips/tcg/octeon_translate.c
21
+++ b/util/cpuinfo-ppc.c
12
+++ b/target/mips/tcg/octeon_translate.c
22
@@ -XXX,XX +XXX,XX @@
13
@@ -XXX,XX +XXX,XX @@ static bool trans_BBIT(DisasContext *ctx, arg_BBIT *a)
23
#include "qemu/osdep.h"
14
TCGv p;
24
#include "host/cpuinfo.h"
15
25
16
if (ctx->hflags & MIPS_HFLAG_BMASK) {
26
+#include <asm/cputable.h>
17
- LOG_DISAS("Branch in delay / forbidden slot at PC 0x"
27
#ifdef CONFIG_GETAUXVAL
18
- TARGET_FMT_lx "\n", ctx->base.pc_next);
28
# include <sys/auxv.h>
19
+ LOG_DISAS("Branch in delay / forbidden slot at PC 0x%" VADDR_PRIx "\n",
29
#else
20
+ ctx->base.pc_next);
30
-# include <asm/cputable.h>
21
generate_exception_end(ctx, EXCP_RI);
31
# include "elf.h"
22
return true;
32
#endif
33
34
@@ -XXX,XX +XXX,XX @@ unsigned __attribute__((constructor)) cpuinfo_init(void)
35
info |= CPUINFO_V2_06;
36
}
23
}
37
38
- if (hwcap2 & PPC_FEATURE2_HAS_ISEL) {
39
+ if (hwcap2 & PPC_FEATURE2_ISEL) {
40
info |= CPUINFO_ISEL;
41
}
42
if (hwcap & PPC_FEATURE_HAS_ALTIVEC) {
43
@@ -XXX,XX +XXX,XX @@ unsigned __attribute__((constructor)) cpuinfo_init(void)
44
* always have both anyway, since VSX came with Power7
45
* and crypto came with Power8.
46
*/
47
- if (hwcap2 & PPC_FEATURE2_HAS_VEC_CRYPTO) {
48
+ if (hwcap2 & PPC_FEATURE2_VEC_CRYPTO) {
49
info |= CPUINFO_CRYPTO;
50
}
51
}
52
--
24
--
53
2.34.1
25
2.43.0
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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