Series comparison

 [PULL 0/4] tcg patch queue
-The following changes since commit 34eac35f893664eb8545b98142e23d9954722766:
+Pretty small still, but there are two patches that ought
 to get backported to stable, so no point in delaying.
-  Merge tag 'pull-riscv-to-apply-20240110' of https://github.com/alistair23/qemu into staging (2024-01-10 11:41:56 +0000)
+r~
 The following changes since commit a5ba0a7e4e150d1350a041f0d0ef9ca6c8d7c307:
   Merge tag 'pull-aspeed-20241211' of https://github.com/legoater/qemu into staging (2024-12-11 15:16:47 +0000)
 are available in the Git repository at:
-  https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20240111
+  https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20241212
-for you to fetch changes up to 1d513e06d96697f44de4a1b85c6ff627c443e306:
+for you to fetch changes up to 7ac87b14a92234b6a89b701b4043ad6cf8bdcccf:
-  util: fix build with musl libc on ppc64le (2024-01-11 08:48:16 +1100)
+  target/sparc: Use memcpy() and remove memcpy32() (2024-12-12 14:28:38 -0600)
 ----------------------------------------------------------------
-tcg/i386: Use more 8-bit immediate forms for add, sub, or, xor
+tcg: Reset free_temps before tcg_optimize
-tcg/ppc: Use new registers for LQ destination
+tcg/riscv: Fix StoreStore barrier generation
-util: fix build with musl libc on ppc64le
+include/exec: Introduce fpst alias in helper-head.h.inc
 target/sparc: Use memcpy() and remove memcpy32()
 ----------------------------------------------------------------
-Natanael Copa (1):
+Philippe Mathieu-Daudé (1):
-      util: fix build with musl libc on ppc64le
+      target/sparc: Use memcpy() and remove memcpy32()
-Paolo Bonzini (2):
+Richard Henderson (2):
-      tcg/i386: convert add/sub of 128 to sub/add of -128
+      tcg: Reset free_temps before tcg_optimize
-      tcg/i386: use 8-bit OR or XOR for unsigned 8-bit immediates
+      include/exec: Introduce fpst alias in helper-head.h.inc
-Richard Henderson (1):
+Roman Artemev (1):
-      tcg/ppc: Use new registers for LQ destination
+      tcg/riscv: Fix StoreStore barrier generation
- tcg/ppc/tcg-target-con-set.h |  2 +-
+ include/tcg/tcg-temp-internal.h |  6 ++++++
- tcg/tcg.c                    | 21 ++++++++++++----
+ accel/tcg/plugin-gen.c          |  2 +-
- util/cpuinfo-ppc.c           |  6 ++---
+ target/sparc/win_helper.c       | 26 ++++++++------------------
- tcg/i386/tcg-target.c.inc    | 60 +++++++++++++++++++++++++++++++++-----------
+ tcg/tcg.c                       |  5 ++++-
- tcg/ppc/tcg-target.c.inc     |  3 ++-
+ include/exec/helper-head.h.inc  |  3 +++
-files changed, 67 insertions(+), 25 deletions(-)
+ tcg/riscv/tcg-target.c.inc      |  2 +-
 files changed, 23 insertions(+), 21 deletions(-)

-[PULL 3/4] tcg/ppc: Use new registers for LQ destination
+[PULL 1/4] tcg: Reset free_temps before tcg_optimize
-LQ has a constraint that RTp != RA, else SIGILL.
+When allocating new temps during tcg_optmize, do not re-use
-Therefore, force the destination of INDEX_op_qemu_*_ld128 to be a
+any EBB temps that were used within the TB.  We do not have
-new register pair, so that it cannot overlap the input address.
+any idea what span of the TB in which the temp was live.
-This requires new support in process_op_defs and tcg_reg_alloc_op.
+Introduce tcg_temp_ebb_reset_freed and use before tcg_optimize,
 as well as replacing the equivalent in plugin_gen_inject and
 tcg_func_start.
 Cc: qemu-stable@nongnu.org
-Fixes: 526cd4ec01f ("tcg/ppc: Support 128-bit load/store")
+Fixes: fb04ab7ddd8 ("tcg/optimize: Lower TCG_COND_TST{EQ,NE} if unsupported")
 Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2711
 Reported-by: wannacu <wannacu2049@gmail.com>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Message-Id: <20240102013456.131846-1-richard.henderson@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- tcg/ppc/tcg-target-con-set.h |  2 +-
+ include/tcg/tcg-temp-internal.h | 6 ++++++
- tcg/tcg.c                    | 21 ++++++++++++++++-----
+ accel/tcg/plugin-gen.c          | 2 +-
- tcg/ppc/tcg-target.c.inc     |  3 ++-
+ tcg/tcg.c                       | 5 ++++-
-files changed, 19 insertions(+), 7 deletions(-)
+files changed, 11 insertions(+), 2 deletions(-)
-diff --git a/tcg/ppc/tcg-target-con-set.h b/tcg/ppc/tcg-target-con-set.h
+diff --git a/include/tcg/tcg-temp-internal.h b/include/tcg/tcg-temp-internal.h
 index XXXXXXX..XXXXXXX 100644
---- a/tcg/ppc/tcg-target-con-set.h
+--- a/include/tcg/tcg-temp-internal.h
-+++ b/tcg/ppc/tcg-target-con-set.h
++++ b/include/tcg/tcg-temp-internal.h
-@@ -XXX,XX +XXX,XX @@ C_O1_I3(v, v, v, v)
+@@ -XXX,XX +XXX,XX @@ TCGv_i64 tcg_temp_ebb_new_i64(void);
- C_O1_I4(r, r, ri, rZ, rZ)
+ TCGv_ptr tcg_temp_ebb_new_ptr(void);
- C_O1_I4(r, r, r, ri, ri)
+ TCGv_i128 tcg_temp_ebb_new_i128(void);
- C_O2_I1(r, r, r)
--C_O2_I1(o, m, r)
++/* Forget all freed EBB temps, so that new allocations produce new temps. */
-+C_N1O1_I1(o, m, r)
++static inline void tcg_temp_ebb_reset_freed(TCGContext *s)
- C_O2_I2(r, r, r, r)
++{
- C_O2_I4(r, r, rI, rZM, r, r)
++    memset(s->free_temps, 0, sizeof(s->free_temps));
- C_O2_I4(r, r, r, r, rI, rZM)
++}
 +
  #endif /* TCG_TEMP_FREE_H */
 diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c
 index XXXXXXX..XXXXXXX 100644
 --- a/accel/tcg/plugin-gen.c
 +++ b/accel/tcg/plugin-gen.c
@@ -XXX,XX +XXX,XX @@ static void plugin_gen_inject(struct qemu_plugin_tb *plugin_tb)
       * that might be live within the existing opcode stream.
       * The simplest solution is to release them all and create new.
       */
 -    memset(tcg_ctx->free_temps, 0, sizeof(tcg_ctx->free_temps));
 +    tcg_temp_ebb_reset_freed(tcg_ctx);
      QTAILQ_FOREACH_SAFE(op, &tcg_ctx->ops, link, next) {
          switch (op->opc) {
 diff --git a/tcg/tcg.c b/tcg/tcg.c
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/tcg.c
 +++ b/tcg/tcg.c
-@@ -XXX,XX +XXX,XX @@ static void tcg_out_movext3(TCGContext *s, const TCGMovExtend *i1,
+@@ -XXX,XX +XXX,XX @@ void tcg_func_start(TCGContext *s)
- #define C_O1_I4(O1, I1, I2, I3, I4)     C_PFX5(c_o1_i4_, O1, I1, I2, I3, I4),
+     s->nb_temps = s->nb_globals;
- #define C_N1_I2(O1, I1, I2)             C_PFX3(c_n1_i2_, O1, I1, I2),
+     /* No temps have been previously allocated for size or locality.  */
-+#define C_N1O1_I1(O1, O2, I1)           C_PFX3(c_n1o1_i1_, O1, O2, I1),
+-    memset(s->free_temps, 0, sizeof(s->free_temps));
- #define C_N2_I1(O1, O2, I1)             C_PFX3(c_n2_i1_, O1, O2, I1),
++    tcg_temp_ebb_reset_freed(s);
- #define C_O2_I1(O1, O2, I1)             C_PFX3(c_o2_i1_, O1, O2, I1),
+     /* No constant temps have been previously allocated. */
-@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode);
+     for (int i = 0; i < TCG_TYPE_COUNT; ++i) {
- #undef C_O1_I3
+@@ -XXX,XX +XXX,XX @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb, uint64_t pc_start)
- #undef C_O1_I4
+     }
- #undef C_N1_I2
+ #endif
-+#undef C_N1O1_I1
- #undef C_N2_I1
++    /* Do not reuse any EBB that may be allocated within the TB. */
- #undef C_O2_I1
++    tcg_temp_ebb_reset_freed(s);
- #undef C_O2_I2
++
-@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode);
+     tcg_optimize(s);
- #define C_O1_I4(O1, I1, I2, I3, I4)     { .args_ct_str = { #O1, #I1, #I2, #I3, #I4 } },
+     reachable_code_pass(s);
  #define C_N1_I2(O1, I1, I2)             { .args_ct_str = { "&" #O1, #I1, #I2 } },
 +#define C_N1O1_I1(O1, O2, I1)           { .args_ct_str = { "&" #O1, #O2, #I1 } },
  #define C_N2_I1(O1, O2, I1)             { .args_ct_str = { "&" #O1, "&" #O2, #I1 } },
  #define C_O2_I1(O1, O2, I1)             { .args_ct_str = { #O1, #O2, #I1 } },
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef constraint_sets[] = {
  #undef C_O1_I3
  #undef C_O1_I4
  #undef C_N1_I2
 +#undef C_N1O1_I1
  #undef C_N2_I1
  #undef C_O2_I1
  #undef C_O2_I2
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef constraint_sets[] = {
  #define C_O1_I4(O1, I1, I2, I3, I4)     C_PFX5(c_o1_i4_, O1, I1, I2, I3, I4)
  #define C_N1_I2(O1, I1, I2)             C_PFX3(c_n1_i2_, O1, I1, I2)
 +#define C_N1O1_I1(O1, O2, I1)           C_PFX3(c_n1o1_i1_, O1, O2, I1)
  #define C_N2_I1(O1, O2, I1)             C_PFX3(c_n2_i1_, O1, O2, I1)
  #define C_O2_I1(O1, O2, I1)             C_PFX3(c_o2_i1_, O1, O2, I1)
@@ -XXX,XX +XXX,XX @@ static void process_op_defs(TCGContext *s)
                      .pair = 2,
                      .pair_index = o,
                      .regs = def->args_ct[o].regs << 1,
 +                    .newreg = def->args_ct[o].newreg,
                  };
                  def->args_ct[o].pair = 1;
                  def->args_ct[o].pair_index = i;
@@ -XXX,XX +XXX,XX @@ static void process_op_defs(TCGContext *s)
                      .pair = 1,
                      .pair_index = o,
                      .regs = def->args_ct[o].regs >> 1,
 +                    .newreg = def->args_ct[o].newreg,
                  };
                  def->args_ct[o].pair = 2;
                  def->args_ct[o].pair_index = i;
@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
                  break;
              case 1: /* first of pair */
 -                tcg_debug_assert(!arg_ct->newreg);
                  if (arg_ct->oalias) {
                      reg = new_args[arg_ct->alias_index];
 -                    break;
 +                } else if (arg_ct->newreg) {
 +                    reg = tcg_reg_alloc_pair(s, arg_ct->regs,
 +                                             i_allocated_regs | o_allocated_regs,
 +                                             output_pref(op, k),
 +                                             ts->indirect_base);
 +                } else {
 +                    reg = tcg_reg_alloc_pair(s, arg_ct->regs, o_allocated_regs,
 +                                             output_pref(op, k),
 +                                             ts->indirect_base);
                  }
 -                reg = tcg_reg_alloc_pair(s, arg_ct->regs, o_allocated_regs,
 -                                         output_pref(op, k), ts->indirect_base);
                  break;
              case 2: /* second of pair */
 -                tcg_debug_assert(!arg_ct->newreg);
                  if (arg_ct->oalias) {
                      reg = new_args[arg_ct->alias_index];
                  } else {
 diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/ppc/tcg-target.c.inc
 +++ b/tcg/ppc/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ldst_i128(TCGContext *s, TCGReg datalo, TCGReg datahi,
          tcg_debug_assert(!need_bswap);
          tcg_debug_assert(datalo & 1);
          tcg_debug_assert(datahi == datalo - 1);
 +        tcg_debug_assert(!is_ld || datahi != index);
          insn = is_ld ? LQ : STQ;
          tcg_out32(s, insn | TAI(datahi, index, 0));
      } else {
@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
      case INDEX_op_qemu_ld_a32_i128:
      case INDEX_op_qemu_ld_a64_i128:
 -        return C_O2_I1(o, m, r);
 +        return C_N1O1_I1(o, m, r);
      case INDEX_op_qemu_st_a32_i128:
      case INDEX_op_qemu_st_a64_i128:
          return C_O0_I3(o, m, r);
 --
-.34.1
+.43.0

-[PULL 4/4] util: fix build with musl libc on ppc64le
+[PULL 2/4] tcg/riscv: Fix StoreStore barrier generation
-From: Natanael Copa <ncopa@alpinelinux.org>
+From: Roman Artemev <roman.artemev@syntacore.com>
-Use PPC_FEATURE2_ISEL and PPC_FEATURE2_VEC_CRYPTO from linux headers
+On RISC-V to StoreStore barrier corresponds
-instead of the GNU specific PPC_FEATURE2_HAS_ISEL and
+`fence w, w` not `fence r, r`
 PPC_FEATURE2_HAS_VEC_CRYPTO. This fixes build with musl libc.
 Cc: qemu-stable@nongnu.org
-Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1861
+Fixes: efbea94c76b ("tcg/riscv: Add slowpath load and store instructions")
-Signed-off-by: Natanael Copa <ncopa@alpinelinux.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Fixes: 63922f467a ("tcg/ppc: Replace HAVE_ISEL macro with a variable")
+Signed-off-by: Denis Tomashev <denis.tomashev@syntacore.com>
-Fixes: 68f340d4cd ("tcg/ppc: Enable Altivec detection")
+Signed-off-by: Roman Artemev <roman.artemev@syntacore.com>
-Message-Id: <20231219105236.7059-1-ncopa@alpinelinux.org>
+Message-ID: <e2f2131e294a49e79959d4fa9ec02cf4@syntacore.com>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- util/cpuinfo-ppc.c | 6 +++---
+ tcg/riscv/tcg-target.c.inc | 2 +-
-file changed, 3 insertions(+), 3 deletions(-)
+file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/util/cpuinfo-ppc.c b/util/cpuinfo-ppc.c
+diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/util/cpuinfo-ppc.c
+--- a/tcg/riscv/tcg-target.c.inc
-+++ b/util/cpuinfo-ppc.c
++++ b/tcg/riscv/tcg-target.c.inc
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static void tcg_out_mb(TCGContext *s, TCGArg a0)
- #include "qemu/osdep.h"
+         insn |= 0x02100000;
  #include "host/cpuinfo.h"
 +#include <asm/cputable.h>
  #ifdef CONFIG_GETAUXVAL
  # include <sys/auxv.h>
  #else
 -# include <asm/cputable.h>
  # include "elf.h"
  #endif
@@ -XXX,XX +XXX,XX @@ unsigned __attribute__((constructor)) cpuinfo_init(void)
          info |= CPUINFO_V2_06;
      }
+     if (a0 & TCG_MO_ST_ST) {
--    if (hwcap2 & PPC_FEATURE2_HAS_ISEL) {
+-        insn |= 0x02200000;
-+    if (hwcap2 & PPC_FEATURE2_ISEL) {
++        insn |= 0x01100000;
          info |= CPUINFO_ISEL;
      }
-     if (hwcap & PPC_FEATURE_HAS_ALTIVEC) {
+     tcg_out32(s, insn);
-@@ -XXX,XX +XXX,XX @@ unsigned __attribute__((constructor)) cpuinfo_init(void)
+ }
               * always have both anyway, since VSX came with Power7
               * and crypto came with Power8.
               */
 -            if (hwcap2 & PPC_FEATURE2_HAS_VEC_CRYPTO) {
 +            if (hwcap2 & PPC_FEATURE2_VEC_CRYPTO) {
                  info |= CPUINFO_CRYPTO;
              }
          }
 --
-.34.1
+.43.0

-[PULL 2/4] tcg/i386: use 8-bit OR or XOR for unsigned 8-bit immediates
+[PULL 3/4] include/exec: Introduce fpst alias in helper-head.h.inc
-From: Paolo Bonzini <pbonzini@redhat.com>
+This allows targets to declare that the helper requires a
 float_status pointer and instead of a generic void pointer.
-In the case where OR or XOR has an 8-bit immediate between 128 and 255,
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 we can operate on a low-byte register and shorten the output by two or
 three bytes (two if a prefix byte is needed for REX.B).
 Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
 Message-Id: <20231228120524.70239-1-pbonzini@redhat.com>
 [rth: Incorporate into switch.]
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- tcg/i386/tcg-target.c.inc | 11 +++++++++++
+ include/exec/helper-head.h.inc | 3 +++
-file changed, 11 insertions(+)
+file changed, 3 insertions(+)
-diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
+diff --git a/include/exec/helper-head.h.inc b/include/exec/helper-head.h.inc
 index XXXXXXX..XXXXXXX 100644
---- a/tcg/i386/tcg-target.c.inc
+--- a/include/exec/helper-head.h.inc
-+++ b/tcg/i386/tcg-target.c.inc
++++ b/include/exec/helper-head.h.inc
-@@ -XXX,XX +XXX,XX @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct, int vece)
+@@ -XXX,XX +XXX,XX @@
- #define P_VEXL          0x80000         /* Set VEX.L = 1 */
+ #define dh_alias_ptr ptr
- #define P_EVEX          0x100000        /* Requires EVEX encoding */
+ #define dh_alias_cptr ptr
+ #define dh_alias_env ptr
-+#define OPC_ARITH_EbIb    (0x80)
++#define dh_alias_fpst ptr
- #define OPC_ARITH_EvIz    (0x81)
+ #define dh_alias_void void
- #define OPC_ARITH_EvIb    (0x83)
+ #define dh_alias_noreturn noreturn
- #define OPC_ARITH_GvEv    (0x03)        /* ... plus (ARITH_FOO << 3) */
+ #define dh_alias(t) glue(dh_alias_, t)
-@@ -XXX,XX +XXX,XX @@ static void tgen_arithi(TCGContext *s, int c, int r0,
+@@ -XXX,XX +XXX,XX @@
-             return;
+ #define dh_ctype_ptr void *
-         }
+ #define dh_ctype_cptr const void *
-         break;
+ #define dh_ctype_env CPUArchState *
-+
++#define dh_ctype_fpst float_status *
-+    case ARITH_OR:
+ #define dh_ctype_void void
-+    case ARITH_XOR:
+ #define dh_ctype_noreturn G_NORETURN void
-+        if (val >= 0x80 && val <= 0xff
+ #define dh_ctype(t) dh_ctype_##t
-+            && (r0 < 4 || TCG_TARGET_REG_BITS == 64)) {
+@@ -XXX,XX +XXX,XX @@
-+            tcg_out_modrm(s, OPC_ARITH_EbIb + P_REXB_RM, c, r0);
+ #define dh_typecode_f64 dh_typecode_i64
-+            tcg_out8(s, val);
+ #define dh_typecode_cptr dh_typecode_ptr
-+            return;
+ #define dh_typecode_env dh_typecode_ptr
-+        }
++#define dh_typecode_fpst dh_typecode_ptr
-+        break;
+ #define dh_typecode(t) dh_typecode_##t
-     }
+ #define dh_callflag_i32  0
      if (val == (int8_t)val) {
 --
-.34.1
+.43.0

-[PULL 1/4] tcg/i386: convert add/sub of 128 to sub/add of -128
+[PULL 4/4] target/sparc: Use memcpy() and remove memcpy32()
-From: Paolo Bonzini <pbonzini@redhat.com>
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
-Extend the existing conditional that generates INC/DEC, to also swap an
+Rather than manually copying each register, use
-ADD for a SUB and vice versa when the immediate is 128.  This facilitates
+the libc memcpy(), which is well optimized nowadays.
 using OPC_ARITH_EvIb instead of OPC_ARITH_EvIz.
-Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
+Suggested-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
-Message-Id: <20231228120514.70205-1-pbonzini@redhat.com>
+Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
-[rth: Use a switch on C]
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Message-ID: <20241205205418.67613-1-philmd@linaro.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- tcg/i386/tcg-target.c.inc | 49 +++++++++++++++++++++++++++------------
+ target/sparc/win_helper.c | 26 ++++++++------------------
-file changed, 34 insertions(+), 15 deletions(-)
+file changed, 8 insertions(+), 18 deletions(-)
-diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
+diff --git a/target/sparc/win_helper.c b/target/sparc/win_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/tcg/i386/tcg-target.c.inc
+--- a/target/sparc/win_helper.c
-+++ b/tcg/i386/tcg-target.c.inc
++++ b/target/sparc/win_helper.c
-@@ -XXX,XX +XXX,XX @@ static void tgen_arithi(TCGContext *s, int c, int r0,
+@@ -XXX,XX +XXX,XX @@
-         c &= 7;
+ #include "exec/helper-proto.h"
  #include "trace.h"
 -static inline void memcpy32(target_ulong *dst, const target_ulong *src)
 -{
 -    dst[0] = src[0];
 -    dst[1] = src[1];
 -    dst[2] = src[2];
 -    dst[3] = src[3];
 -    dst[4] = src[4];
 -    dst[5] = src[5];
 -    dst[6] = src[6];
 -    dst[7] = src[7];
 -}
 -
  void cpu_set_cwp(CPUSPARCState *env, int new_cwp)
  {
      /* put the modified wrap registers at their proper location */
      if (env->cwp == env->nwindows - 1) {
 -        memcpy32(env->regbase, env->regbase + env->nwindows * 16);
 +        memcpy(env->regbase, env->regbase + env->nwindows * 16,
 +               sizeof(env->gregs));
      }
+     env->cwp = new_cwp;
--    /* ??? While INC is 2 bytes shorter than ADDL $1, they also induce
--       partial flags update stalls on Pentium4 and are not recommended
+     /* put the wrap registers at their temporary location */
--       by current Intel optimization manuals.  */
+     if (new_cwp == env->nwindows - 1) {
--    if (!cf && (c == ARITH_ADD || c == ARITH_SUB) && (val == 1 || val == -1)) {
+-        memcpy32(env->regbase + env->nwindows * 16, env->regbase);
--        int is_inc = (c == ARITH_ADD) ^ (val < 0);
++        memcpy(env->regbase + env->nwindows * 16, env->regbase,
--        if (TCG_TARGET_REG_BITS == 64) {
++               sizeof(env->gregs));
 -            /* The single-byte increment encodings are re-tasked as the
 -               REX prefixes.  Use the MODRM encoding.  */
 -            tcg_out_modrm(s, OPC_GRP5 + rexw,
 -                          (is_inc ? EXT5_INC_Ev : EXT5_DEC_Ev), r0);
 -        } else {
 -            tcg_out8(s, (is_inc ? OPC_INC_r32 : OPC_DEC_r32) + r0);
 +    switch (c) {
 +    case ARITH_ADD:
 +    case ARITH_SUB:
 +        if (!cf) {
 +            /*
 +             * ??? While INC is 2 bytes shorter than ADDL $1, they also induce
 +             * partial flags update stalls on Pentium4 and are not recommended
 +             * by current Intel optimization manuals.
 +             */
 +            if (val == 1 || val == -1) {
 +                int is_inc = (c == ARITH_ADD) ^ (val < 0);
 +                if (TCG_TARGET_REG_BITS == 64) {
 +                    /*
 +                     * The single-byte increment encodings are re-tasked
 +                     * as the REX prefixes.  Use the MODRM encoding.
 +                     */
 +                    tcg_out_modrm(s, OPC_GRP5 + rexw,
 +                                  (is_inc ? EXT5_INC_Ev : EXT5_DEC_Ev), r0);
 +                } else {
 +                    tcg_out8(s, (is_inc ? OPC_INC_r32 : OPC_DEC_r32) + r0);
 +                }
 +                return;
 +            }
 +            if (val == 128) {
 +                /*
 +                 * Facilitate using an 8-bit immediate.  Carry is inverted
 +                 * by this transformation, so do it only if cf == 0.
 +                 */
 +                c ^= ARITH_ADD ^ ARITH_SUB;
 +                val = -128;
 +            }
          }
 -        return;
 -    }
 +        break;
 -    if (c == ARITH_AND) {
 +    case ARITH_AND:
          if (TCG_TARGET_REG_BITS == 64) {
              if (val == 0xffffffffu) {
                  tcg_out_ext32u(s, r0, r0);
@@ -XXX,XX +XXX,XX @@ static void tgen_arithi(TCGContext *s, int c, int r0,
              tcg_out_ext16u(s, r0, r0);
              return;
          }
 +        break;
      }
+     env->regwptr = env->regbase + (new_cwp * 16);
-     if (val == (int8_t)val) {
+ }
@@ -XXX,XX +XXX,XX @@ void cpu_gl_switch_gregs(CPUSPARCState *env, uint32_t new_gl)
      dst = get_gl_gregset(env, env->gl);
      if (src != dst) {
 -        memcpy32(dst, env->gregs);
 -        memcpy32(env->gregs, src);
 +        memcpy(dst, env->gregs, sizeof(env->gregs));
 +        memcpy(env->gregs, src, sizeof(env->gregs));
      }
  }
@@ -XXX,XX +XXX,XX @@ void cpu_change_pstate(CPUSPARCState *env, uint32_t new_pstate)
          /* Switch global register bank */
          src = get_gregset(env, new_pstate_regs);
          dst = get_gregset(env, pstate_regs);
 -        memcpy32(dst, env->gregs);
 -        memcpy32(env->gregs, src);
 +        memcpy(dst, env->gregs, sizeof(env->gregs));
 +        memcpy(env->gregs, src, sizeof(env->gregs));
      } else {
          trace_win_helper_no_switch_pstate(new_pstate_regs);
      }
 --
-.34.1
+.43.0

The following changes since commit 34eac35f893664eb8545b98142e23d9954722766:

Merge tag 'pull-riscv-to-apply-20240110' of https://github.com/alistair23/qemu into staging (2024-01-10 11:41:56 +0000)

are available in the Git repository at:

https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20240111

for you to fetch changes up to 1d513e06d96697f44de4a1b85c6ff627c443e306:

util: fix build with musl libc on ppc64le (2024-01-11 08:48:16 +1100)

----------------------------------------------------------------
tcg/i386: Use more 8-bit immediate forms for add, sub, or, xor
tcg/ppc: Use new registers for LQ destination
util: fix build with musl libc on ppc64le

----------------------------------------------------------------
Natanael Copa (1):
      util: fix build with musl libc on ppc64le

Paolo Bonzini (2):
      tcg/i386: convert add/sub of 128 to sub/add of -128
      tcg/i386: use 8-bit OR or XOR for unsigned 8-bit immediates

Richard Henderson (1):
      tcg/ppc: Use new registers for LQ destination

tcg/ppc/tcg-target-con-set.h |  2 +-
 tcg/tcg.c                    | 21 ++++++++++++----
 util/cpuinfo-ppc.c           |  6 ++---
 tcg/i386/tcg-target.c.inc    | 60 +++++++++++++++++++++++++++++++++-----------
 tcg/ppc/tcg-target.c.inc     |  3 ++-
 5 files changed, 67 insertions(+), 25 deletions(-)

From: Paolo Bonzini <pbonzini@redhat.com>

Extend the existing conditional that generates INC/DEC, to also swap an
ADD for a SUB and vice versa when the immediate is 128.  This facilitates
using OPC_ARITH_EvIb instead of OPC_ARITH_EvIz.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20231228120514.70205-1-pbonzini@redhat.com>
[rth: Use a switch on C]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/i386/tcg-target.c.inc | 49 +++++++++++++++++++++++++++------------
 1 file changed, 34 insertions(+), 15 deletions(-)

diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static void tgen_arithi(TCGContext *s, int c, int r0,
         c &= 7;
     }
 
-    /* ??? While INC is 2 bytes shorter than ADDL $1, they also induce
-       partial flags update stalls on Pentium4 and are not recommended
-       by current Intel optimization manuals.  */
-    if (!cf && (c == ARITH_ADD || c == ARITH_SUB) && (val == 1 || val == -1)) {
-        int is_inc = (c == ARITH_ADD) ^ (val < 0);
-        if (TCG_TARGET_REG_BITS == 64) {
-            /* The single-byte increment encodings are re-tasked as the
-               REX prefixes.  Use the MODRM encoding.  */
-            tcg_out_modrm(s, OPC_GRP5 + rexw,
-                          (is_inc ? EXT5_INC_Ev : EXT5_DEC_Ev), r0);
-        } else {
-            tcg_out8(s, (is_inc ? OPC_INC_r32 : OPC_DEC_r32) + r0);
+    switch (c) {
+    case ARITH_ADD:
+    case ARITH_SUB:
+        if (!cf) {
+            /*
+             * ??? While INC is 2 bytes shorter than ADDL $1, they also induce
+             * partial flags update stalls on Pentium4 and are not recommended
+             * by current Intel optimization manuals.
+             */
+            if (val == 1 || val == -1) {
+                int is_inc = (c == ARITH_ADD) ^ (val < 0);
+                if (TCG_TARGET_REG_BITS == 64) {
+                    /*
+                     * The single-byte increment encodings are re-tasked
+                     * as the REX prefixes.  Use the MODRM encoding.
+                     */
+                    tcg_out_modrm(s, OPC_GRP5 + rexw,
+                                  (is_inc ? EXT5_INC_Ev : EXT5_DEC_Ev), r0);
+                } else {
+                    tcg_out8(s, (is_inc ? OPC_INC_r32 : OPC_DEC_r32) + r0);
+                }
+                return;
+            }
+            if (val == 128) {
+                /*
+                 * Facilitate using an 8-bit immediate.  Carry is inverted
+                 * by this transformation, so do it only if cf == 0.
+                 */
+                c ^= ARITH_ADD ^ ARITH_SUB;
+                val = -128;
+            }
         }
-        return;
-    }
+        break;
 
-    if (c == ARITH_AND) {
+    case ARITH_AND:
         if (TCG_TARGET_REG_BITS == 64) {
             if (val == 0xffffffffu) {
                 tcg_out_ext32u(s, r0, r0);
@@ -XXX,XX +XXX,XX @@ static void tgen_arithi(TCGContext *s, int c, int r0,
             tcg_out_ext16u(s, r0, r0);
             return;
         }
+        break;
     }
 
     if (val == (int8_t)val) {
-- 
2.34.1

From: Paolo Bonzini <pbonzini@redhat.com>

In the case where OR or XOR has an 8-bit immediate between 128 and 255,
we can operate on a low-byte register and shorten the output by two or
three bytes (two if a prefix byte is needed for REX.B).

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20231228120524.70239-1-pbonzini@redhat.com>
[rth: Incorporate into switch.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/i386/tcg-target.c.inc | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct, int vece)
 #define P_VEXL          0x80000         /* Set VEX.L = 1 */
 #define P_EVEX          0x100000        /* Requires EVEX encoding */
 
+#define OPC_ARITH_EbIb	(0x80)
 #define OPC_ARITH_EvIz	(0x81)
 #define OPC_ARITH_EvIb	(0x83)
 #define OPC_ARITH_GvEv	(0x03)		/* ... plus (ARITH_FOO << 3) */
@@ -XXX,XX +XXX,XX @@ static void tgen_arithi(TCGContext *s, int c, int r0,
             return;
         }
         break;
+
+    case ARITH_OR:
+    case ARITH_XOR:
+        if (val >= 0x80 && val <= 0xff
+            && (r0 < 4 || TCG_TARGET_REG_BITS == 64)) {
+            tcg_out_modrm(s, OPC_ARITH_EbIb + P_REXB_RM, c, r0);
+            tcg_out8(s, val);
+            return;
+        }
+        break;
     }
 
     if (val == (int8_t)val) {
-- 
2.34.1

LQ has a constraint that RTp != RA, else SIGILL.
Therefore, force the destination of INDEX_op_qemu_*_ld128 to be a
new register pair, so that it cannot overlap the input address.

This requires new support in process_op_defs and tcg_reg_alloc_op.

Cc: qemu-stable@nongnu.org
Fixes: 526cd4ec01f ("tcg/ppc: Support 128-bit load/store")
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20240102013456.131846-1-richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/ppc/tcg-target-con-set.h |  2 +-
 tcg/tcg.c                    | 21 ++++++++++++++++-----
 tcg/ppc/tcg-target.c.inc     |  3 ++-
 3 files changed, 19 insertions(+), 7 deletions(-)

diff --git a/tcg/ppc/tcg-target-con-set.h b/tcg/ppc/tcg-target-con-set.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/ppc/tcg-target-con-set.h
+++ b/tcg/ppc/tcg-target-con-set.h
@@ -XXX,XX +XXX,XX @@ C_O1_I3(v, v, v, v)
 C_O1_I4(r, r, ri, rZ, rZ)
 C_O1_I4(r, r, r, ri, ri)
 C_O2_I1(r, r, r)
-C_O2_I1(o, m, r)
+C_N1O1_I1(o, m, r)
 C_O2_I2(r, r, r, r)
 C_O2_I4(r, r, rI, rZM, r, r)
 C_O2_I4(r, r, r, r, rI, rZM)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index XXXXXXX..XXXXXXX 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -XXX,XX +XXX,XX @@ static void tcg_out_movext3(TCGContext *s, const TCGMovExtend *i1,
 #define C_O1_I4(O1, I1, I2, I3, I4)     C_PFX5(c_o1_i4_, O1, I1, I2, I3, I4),
 
 #define C_N1_I2(O1, I1, I2)             C_PFX3(c_n1_i2_, O1, I1, I2),
+#define C_N1O1_I1(O1, O2, I1)           C_PFX3(c_n1o1_i1_, O1, O2, I1),
 #define C_N2_I1(O1, O2, I1)             C_PFX3(c_n2_i1_, O1, O2, I1),
 
 #define C_O2_I1(O1, O2, I1)             C_PFX3(c_o2_i1_, O1, O2, I1),
@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode);
 #undef C_O1_I3
 #undef C_O1_I4
 #undef C_N1_I2
+#undef C_N1O1_I1
 #undef C_N2_I1
 #undef C_O2_I1
 #undef C_O2_I2
@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode);
 #define C_O1_I4(O1, I1, I2, I3, I4)     { .args_ct_str = { #O1, #I1, #I2, #I3, #I4 } },
 
 #define C_N1_I2(O1, I1, I2)             { .args_ct_str = { "&" #O1, #I1, #I2 } },
+#define C_N1O1_I1(O1, O2, I1)           { .args_ct_str = { "&" #O1, #O2, #I1 } },
 #define C_N2_I1(O1, O2, I1)             { .args_ct_str = { "&" #O1, "&" #O2, #I1 } },
 
 #define C_O2_I1(O1, O2, I1)             { .args_ct_str = { #O1, #O2, #I1 } },
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef constraint_sets[] = {
 #undef C_O1_I3
 #undef C_O1_I4
 #undef C_N1_I2
+#undef C_N1O1_I1
 #undef C_N2_I1
 #undef C_O2_I1
 #undef C_O2_I2
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef constraint_sets[] = {
 #define C_O1_I4(O1, I1, I2, I3, I4)     C_PFX5(c_o1_i4_, O1, I1, I2, I3, I4)
 
 #define C_N1_I2(O1, I1, I2)             C_PFX3(c_n1_i2_, O1, I1, I2)
+#define C_N1O1_I1(O1, O2, I1)           C_PFX3(c_n1o1_i1_, O1, O2, I1)
 #define C_N2_I1(O1, O2, I1)             C_PFX3(c_n2_i1_, O1, O2, I1)
 
 #define C_O2_I1(O1, O2, I1)             C_PFX3(c_o2_i1_, O1, O2, I1)
@@ -XXX,XX +XXX,XX @@ static void process_op_defs(TCGContext *s)
                     .pair = 2,
                     .pair_index = o,
                     .regs = def->args_ct[o].regs << 1,
+                    .newreg = def->args_ct[o].newreg,
                 };
                 def->args_ct[o].pair = 1;
                 def->args_ct[o].pair_index = i;
@@ -XXX,XX +XXX,XX @@ static void process_op_defs(TCGContext *s)
                     .pair = 1,
                     .pair_index = o,
                     .regs = def->args_ct[o].regs >> 1,
+                    .newreg = def->args_ct[o].newreg,
                 };
                 def->args_ct[o].pair = 2;
                 def->args_ct[o].pair_index = i;
@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
                 break;
 
             case 1: /* first of pair */
-                tcg_debug_assert(!arg_ct->newreg);
                 if (arg_ct->oalias) {
                     reg = new_args[arg_ct->alias_index];
-                    break;
+                } else if (arg_ct->newreg) {
+                    reg = tcg_reg_alloc_pair(s, arg_ct->regs,
+                                             i_allocated_regs | o_allocated_regs,
+                                             output_pref(op, k),
+                                             ts->indirect_base);
+                } else {
+                    reg = tcg_reg_alloc_pair(s, arg_ct->regs, o_allocated_regs,
+                                             output_pref(op, k),
+                                             ts->indirect_base);
                 }
-                reg = tcg_reg_alloc_pair(s, arg_ct->regs, o_allocated_regs,
-                                         output_pref(op, k), ts->indirect_base);
                 break;
 
             case 2: /* second of pair */
-                tcg_debug_assert(!arg_ct->newreg);
                 if (arg_ct->oalias) {
                     reg = new_args[arg_ct->alias_index];
                 } else {
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ldst_i128(TCGContext *s, TCGReg datalo, TCGReg datahi,
         tcg_debug_assert(!need_bswap);
         tcg_debug_assert(datalo & 1);
         tcg_debug_assert(datahi == datalo - 1);
+        tcg_debug_assert(!is_ld || datahi != index);
         insn = is_ld ? LQ : STQ;
         tcg_out32(s, insn | TAI(datahi, index, 0));
     } else {
@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
 
     case INDEX_op_qemu_ld_a32_i128:
     case INDEX_op_qemu_ld_a64_i128:
-        return C_O2_I1(o, m, r);
+        return C_N1O1_I1(o, m, r);
     case INDEX_op_qemu_st_a32_i128:
     case INDEX_op_qemu_st_a64_i128:
         return C_O0_I3(o, m, r);
-- 
2.34.1

From: Natanael Copa <ncopa@alpinelinux.org>

Use PPC_FEATURE2_ISEL and PPC_FEATURE2_VEC_CRYPTO from linux headers
instead of the GNU specific PPC_FEATURE2_HAS_ISEL and
PPC_FEATURE2_HAS_VEC_CRYPTO. This fixes build with musl libc.

Cc: qemu-stable@nongnu.org
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1861
Signed-off-by: Natanael Copa <ncopa@alpinelinux.org>
Fixes: 63922f467a ("tcg/ppc: Replace HAVE_ISEL macro with a variable")
Fixes: 68f340d4cd ("tcg/ppc: Enable Altivec detection")
Message-Id: <20231219105236.7059-1-ncopa@alpinelinux.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 util/cpuinfo-ppc.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/util/cpuinfo-ppc.c b/util/cpuinfo-ppc.c
index XXXXXXX..XXXXXXX 100644
--- a/util/cpuinfo-ppc.c
+++ b/util/cpuinfo-ppc.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/osdep.h"
 #include "host/cpuinfo.h"
 
+#include <asm/cputable.h>
 #ifdef CONFIG_GETAUXVAL
 # include <sys/auxv.h>
 #else
-# include <asm/cputable.h>
 # include "elf.h"
 #endif
 
@@ -XXX,XX +XXX,XX @@ unsigned __attribute__((constructor)) cpuinfo_init(void)
         info |= CPUINFO_V2_06;
     }
 
-    if (hwcap2 & PPC_FEATURE2_HAS_ISEL) {
+    if (hwcap2 & PPC_FEATURE2_ISEL) {
         info |= CPUINFO_ISEL;
     }
     if (hwcap & PPC_FEATURE_HAS_ALTIVEC) {
@@ -XXX,XX +XXX,XX @@ unsigned __attribute__((constructor)) cpuinfo_init(void)
              * always have both anyway, since VSX came with Power7
              * and crypto came with Power8.
              */
-            if (hwcap2 & PPC_FEATURE2_HAS_VEC_CRYPTO) {
+            if (hwcap2 & PPC_FEATURE2_VEC_CRYPTO) {
                 info |= CPUINFO_CRYPTO;
             }
         }
-- 
2.34.1

Pretty small still, but there are two patches that ought
to get backported to stable, so no point in delaying.

The following changes since commit a5ba0a7e4e150d1350a041f0d0ef9ca6c8d7c307:

Merge tag 'pull-aspeed-20241211' of https://github.com/legoater/qemu into staging (2024-12-11 15:16:47 +0000)

are available in the Git repository at:

https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20241212

for you to fetch changes up to 7ac87b14a92234b6a89b701b4043ad6cf8bdcccf:

target/sparc: Use memcpy() and remove memcpy32() (2024-12-12 14:28:38 -0600)

----------------------------------------------------------------
tcg: Reset free_temps before tcg_optimize
tcg/riscv: Fix StoreStore barrier generation
include/exec: Introduce fpst alias in helper-head.h.inc
target/sparc: Use memcpy() and remove memcpy32()

----------------------------------------------------------------
Philippe Mathieu-Daudé (1):
      target/sparc: Use memcpy() and remove memcpy32()

Richard Henderson (2):
      tcg: Reset free_temps before tcg_optimize
      include/exec: Introduce fpst alias in helper-head.h.inc

Roman Artemev (1):
      tcg/riscv: Fix StoreStore barrier generation

When allocating new temps during tcg_optmize, do not re-use
any EBB temps that were used within the TB.  We do not have
any idea what span of the TB in which the temp was live.

Introduce tcg_temp_ebb_reset_freed and use before tcg_optimize,
as well as replacing the equivalent in plugin_gen_inject and
tcg_func_start.

Cc: qemu-stable@nongnu.org
Fixes: fb04ab7ddd8 ("tcg/optimize: Lower TCG_COND_TST{EQ,NE} if unsupported")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2711
Reported-by: wannacu <wannacu2049@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 include/tcg/tcg-temp-internal.h | 6 ++++++
 accel/tcg/plugin-gen.c          | 2 +-
 tcg/tcg.c                       | 5 ++++-
 3 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/include/tcg/tcg-temp-internal.h b/include/tcg/tcg-temp-internal.h
index XXXXXXX..XXXXXXX 100644
--- a/include/tcg/tcg-temp-internal.h
+++ b/include/tcg/tcg-temp-internal.h
@@ -XXX,XX +XXX,XX @@ TCGv_i64 tcg_temp_ebb_new_i64(void);
 TCGv_ptr tcg_temp_ebb_new_ptr(void);
 TCGv_i128 tcg_temp_ebb_new_i128(void);
 
+/* Forget all freed EBB temps, so that new allocations produce new temps. */
+static inline void tcg_temp_ebb_reset_freed(TCGContext *s)
+{
+    memset(s->free_temps, 0, sizeof(s->free_temps));
+}
+
 #endif /* TCG_TEMP_FREE_H */
diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c
index XXXXXXX..XXXXXXX 100644
--- a/accel/tcg/plugin-gen.c
+++ b/accel/tcg/plugin-gen.c
@@ -XXX,XX +XXX,XX @@ static void plugin_gen_inject(struct qemu_plugin_tb *plugin_tb)
      * that might be live within the existing opcode stream.
      * The simplest solution is to release them all and create new.
      */
-    memset(tcg_ctx->free_temps, 0, sizeof(tcg_ctx->free_temps));
+    tcg_temp_ebb_reset_freed(tcg_ctx);
 
     QTAILQ_FOREACH_SAFE(op, &tcg_ctx->ops, link, next) {
         switch (op->opc) {
diff --git a/tcg/tcg.c b/tcg/tcg.c
index XXXXXXX..XXXXXXX 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -XXX,XX +XXX,XX @@ void tcg_func_start(TCGContext *s)
     s->nb_temps = s->nb_globals;
 
     /* No temps have been previously allocated for size or locality.  */
-    memset(s->free_temps, 0, sizeof(s->free_temps));
+    tcg_temp_ebb_reset_freed(s);
 
     /* No constant temps have been previously allocated. */
     for (int i = 0; i < TCG_TYPE_COUNT; ++i) {
@@ -XXX,XX +XXX,XX @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb, uint64_t pc_start)
     }
 #endif
 
+    /* Do not reuse any EBB that may be allocated within the TB. */
+    tcg_temp_ebb_reset_freed(s);
+
     tcg_optimize(s);
 
     reachable_code_pass(s);
-- 
2.43.0

From: Roman Artemev <roman.artemev@syntacore.com>

On RISC-V to StoreStore barrier corresponds
`fence w, w` not `fence r, r`

Cc: qemu-stable@nongnu.org
Fixes: efbea94c76b ("tcg/riscv: Add slowpath load and store instructions")
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Denis Tomashev <denis.tomashev@syntacore.com>
Signed-off-by: Roman Artemev <roman.artemev@syntacore.com>
Message-ID: <e2f2131e294a49e79959d4fa9ec02cf4@syntacore.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/riscv/tcg-target.c.inc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static void tcg_out_mb(TCGContext *s, TCGArg a0)
         insn |= 0x02100000;
     }
     if (a0 & TCG_MO_ST_ST) {
-        insn |= 0x02200000;
+        insn |= 0x01100000;
     }
     tcg_out32(s, insn);
 }
-- 
2.43.0

This allows targets to declare that the helper requires a
float_status pointer and instead of a generic void pointer.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/exec/helper-head.h.inc | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/include/exec/helper-head.h.inc b/include/exec/helper-head.h.inc
index XXXXXXX..XXXXXXX 100644
--- a/include/exec/helper-head.h.inc
+++ b/include/exec/helper-head.h.inc
@@ -XXX,XX +XXX,XX @@
 #define dh_alias_ptr ptr
 #define dh_alias_cptr ptr
 #define dh_alias_env ptr
+#define dh_alias_fpst ptr
 #define dh_alias_void void
 #define dh_alias_noreturn noreturn
 #define dh_alias(t) glue(dh_alias_, t)
@@ -XXX,XX +XXX,XX @@
 #define dh_ctype_ptr void *
 #define dh_ctype_cptr const void *
 #define dh_ctype_env CPUArchState *
+#define dh_ctype_fpst float_status *
 #define dh_ctype_void void
 #define dh_ctype_noreturn G_NORETURN void
 #define dh_ctype(t) dh_ctype_##t
@@ -XXX,XX +XXX,XX @@
 #define dh_typecode_f64 dh_typecode_i64
 #define dh_typecode_cptr dh_typecode_ptr
 #define dh_typecode_env dh_typecode_ptr
+#define dh_typecode_fpst dh_typecode_ptr
 #define dh_typecode(t) dh_typecode_##t
 
 #define dh_callflag_i32  0
-- 
2.43.0

From: Philippe Mathieu-Daudé <philmd@linaro.org>

Rather than manually copying each register, use
the libc memcpy(), which is well optimized nowadays.

Suggested-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20241205205418.67613-1-philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/sparc/win_helper.c | 26 ++++++++------------------
 1 file changed, 8 insertions(+), 18 deletions(-)

diff --git a/target/sparc/win_helper.c b/target/sparc/win_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/sparc/win_helper.c
+++ b/target/sparc/win_helper.c
@@ -XXX,XX +XXX,XX @@
 #include "exec/helper-proto.h"
 #include "trace.h"
 
-static inline void memcpy32(target_ulong *dst, const target_ulong *src)
-{
-    dst[0] = src[0];
-    dst[1] = src[1];
-    dst[2] = src[2];
-    dst[3] = src[3];
-    dst[4] = src[4];
-    dst[5] = src[5];
-    dst[6] = src[6];
-    dst[7] = src[7];
-}
-
 void cpu_set_cwp(CPUSPARCState *env, int new_cwp)
 {
     /* put the modified wrap registers at their proper location */
     if (env->cwp == env->nwindows - 1) {
-        memcpy32(env->regbase, env->regbase + env->nwindows * 16);
+        memcpy(env->regbase, env->regbase + env->nwindows * 16,
+               sizeof(env->gregs));
     }
     env->cwp = new_cwp;
 
     /* put the wrap registers at their temporary location */
     if (new_cwp == env->nwindows - 1) {
-        memcpy32(env->regbase + env->nwindows * 16, env->regbase);
+        memcpy(env->regbase + env->nwindows * 16, env->regbase,
+               sizeof(env->gregs));
     }
     env->regwptr = env->regbase + (new_cwp * 16);
 }
@@ -XXX,XX +XXX,XX @@ void cpu_gl_switch_gregs(CPUSPARCState *env, uint32_t new_gl)
     dst = get_gl_gregset(env, env->gl);
 
     if (src != dst) {
-        memcpy32(dst, env->gregs);
-        memcpy32(env->gregs, src);
+        memcpy(dst, env->gregs, sizeof(env->gregs));
+        memcpy(env->gregs, src, sizeof(env->gregs));
     }
 }
 
@@ -XXX,XX +XXX,XX @@ void cpu_change_pstate(CPUSPARCState *env, uint32_t new_pstate)
         /* Switch global register bank */
         src = get_gregset(env, new_pstate_regs);
         dst = get_gregset(env, pstate_regs);
-        memcpy32(dst, env->gregs);
-        memcpy32(env->gregs, src);
+        memcpy(dst, env->gregs, sizeof(env->gregs));
+        memcpy(env->gregs, src, sizeof(env->gregs));
     } else {
         trace_win_helper_no_switch_pstate(new_pstate_regs);
     }
-- 
2.43.0