target/riscv: A few bug fixes and Coverity fix

[PATCH 0/3] target/riscv: A few bug fixes and Coverity fix

Alistair Francis posted 3 patches 10 months, 3 weeks ago

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Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20240108001328.280222-1-alistair.francis@wdc.com

Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Bin Meng <bin.meng@windriver.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>

target/riscv/cpu.c        | 8 ++++++++
target/riscv/cpu_helper.c | 4 ++--
target/riscv/csr.c        | 5 ++++-
3 files changed, 14 insertions(+), 3 deletions(-)

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[PATCH 0/3] target/riscv: A few bug fixes and Coverity fix

Posted by Alistair Francis 10 months, 3 weeks ago

A few bug fixes for some Gitlab issues and a Coverity fix

Alistair Francis (3):
  target/riscv: Assert that the CSR numbers will be correct
  target/riscv: Don't adjust vscause for exceptions
  target/riscv: Ensure mideleg is set correctly on reset

 target/riscv/cpu.c        | 8 ++++++++
 target/riscv/cpu_helper.c | 4 ++--
 target/riscv/csr.c        | 5 ++++-
 3 files changed, 14 insertions(+), 3 deletions(-)

-- 
2.43.0

Re: [PATCH 0/3] target/riscv: A few bug fixes and Coverity fix

Posted by Alistair Francis 10 months, 3 weeks ago

On Mon, Jan 8, 2024 at 10:13 AM Alistair Francis <alistair23@gmail.com> wrote:
>
> A few bug fixes for some Gitlab issues and a Coverity fix
>
> Alistair Francis (3):
>   target/riscv: Assert that the CSR numbers will be correct
>   target/riscv: Don't adjust vscause for exceptions
>   target/riscv: Ensure mideleg is set correctly on reset

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>  target/riscv/cpu.c        | 8 ++++++++
>  target/riscv/cpu_helper.c | 4 ++--
>  target/riscv/csr.c        | 5 ++++-
>  3 files changed, 14 insertions(+), 3 deletions(-)
>
> --
> 2.43.0
>