[v3] Add "num-prio-bits" property for Cortex-M devices

[PATCH v3 0/3] Add "num-prio-bits" property for Cortex-M devices

Samuel Tardieu posted 3 patches 10 months, 3 weeks ago

Diff against v1 v2
Download series mbox

Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20240106181503.1746200-1-sam@rfc1149.net

Maintainers: Peter Maydell <peter.maydell@linaro.org>, Alexandre Iooss <erdnaxe@crans.org>, Alistair Francis <alistair@alistair23.me>, Arnaud Minier <arnaud.minier@telecom-paris.fr>, "Inès Varhol" <ines.varhol@telecom-paris.fr>

hw/arm/armv7m.c         |  2 ++
hw/arm/stellaris.c      |  2 ++
hw/arm/stm32f100_soc.c  |  1 +
hw/arm/stm32f205_soc.c  |  1 +
hw/arm/stm32f405_soc.c  |  1 +
hw/arm/stm32l4x5_soc.c  |  1 +
hw/intc/armv7m_nvic.c   | 23 ++++++++++++++++++++++-
include/hw/arm/armv7m.h |  1 +
8 files changed, 31 insertions(+), 1 deletion(-)

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[PATCH v3 0/3] Add "num-prio-bits" property for Cortex-M devices

Posted by Samuel Tardieu 10 months, 3 weeks ago

This patch series builds on a discussion initiated by Anton Kochkov on
this list in 2022. It allows setting the appropriate number of priority
bits for Cortex-M devices. For example, FreeRTOS checks at startup that
the right number of priority bits is available in order to guarantee
its runtime structures safety. They have added a configuration option
to disable this check when running on QEMU because QEMU always use 2
bits for Cortex-M0/M0+/M1 and 8 bits for other devices.

While this change allows the number of priority bits to be properly
configured, it keeps the same default as before in order to preserve
backward compatibility unless the SoC configures the exact value.

Changes from v2:
- Add the description of the new armv7m property in include/hw/arm/armv7m.h.

Changes from v1:
- Add support for the STM32L4x5 SOC family (which is currently
  under review for integration) and fix the Based-on: trailer
  in the cover letter.
- Fix a typo in one of the commit messages ("compatibility")

Based-on: <20240106163905.42027-1-ines.varhol@telecom-paris.fr>
([PATCH v5 0/2] Add minimal support for the B-L475E-IOT01A board)

Samuel Tardieu (3):
  hw/intc/armv7m_nvic: add "num-prio-bits" property
  hw/arm/armv7m: alias the NVIC "num-prio-bits" property
  hw/arm/socs: configure priority bits for existing SOCs

 hw/arm/armv7m.c         |  2 ++
 hw/arm/stellaris.c      |  2 ++
 hw/arm/stm32f100_soc.c  |  1 +
 hw/arm/stm32f205_soc.c  |  1 +
 hw/arm/stm32f405_soc.c  |  1 +
 hw/arm/stm32l4x5_soc.c  |  1 +
 hw/intc/armv7m_nvic.c   | 23 ++++++++++++++++++++++-
 include/hw/arm/armv7m.h |  1 +
 8 files changed, 31 insertions(+), 1 deletion(-)

-- 
2.42.0

Re: [PATCH v3 0/3] Add "num-prio-bits" property for Cortex-M devices

Posted by Peter Maydell 10 months, 3 weeks ago

On Sat, 6 Jan 2024 at 18:15, Samuel Tardieu <sam@rfc1149.net> wrote:
>
> This patch series builds on a discussion initiated by Anton Kochkov on
> this list in 2022. It allows setting the appropriate number of priority
> bits for Cortex-M devices. For example, FreeRTOS checks at startup that
> the right number of priority bits is available in order to guarantee
> its runtime structures safety. They have added a configuration option
> to disable this check when running on QEMU because QEMU always use 2
> bits for Cortex-M0/M0+/M1 and 8 bits for other devices.
>
> While this change allows the number of priority bits to be properly
> configured, it keeps the same default as before in order to preserve
> backward compatibility unless the SoC configures the exact value.



Applied to target-arm.next, thanks.

-- PMM