[PULL v2 0/2] loongarch-to-apply queue
[PULL v2 0/6] loongarch-to-apply queue
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The following changes since commit 0c1eccd368af8805ec0fb11e6cf25d0684d37328:
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The following changes since commit 38d0939b86e2eef6f6a622c6f1f7befda0146595:
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Merge tag 'hw-cpus-20240105' of https://github.com/philmd/qemu into staging (2024-01-05 16:08:58 +0000)
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Merge tag 'pull-vfio-20241226' of https://github.com/legoater/qemu into staging (2024-12-26 04:38:38 -0500)
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are available in the Git repository at:
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are available in the Git repository at:
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https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20240106
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https://gitlab.com/bibo-mao/qemu.git tags/pull-loongarch-20241227
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for you to fetch changes up to 5c23704e4725f935b3171787f00e9922a7fc58cb:
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for you to fetch changes up to 5e360dabedb1ab1f15cce27a134ccbe4b8e18424:
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target/loongarch: move translate modules to tcg/ (2024-01-06 10:18:52 +0800)
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target/loongarch: Use auto method with LASX feature (2024-12-27 11:33:06 +0800)
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----------------------------------------------------------------
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----------------------------------------------------------------
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pull-loongarch-20240106
14
pull-loongarch-20241227
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15
v1 ... v2
16
Fixes patch conflict
16
1. Modify patch auther inconsistent with SOB
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18
----------------------------------------------------------------
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----------------------------------------------------------------
19
Song Gao (2):
19
Bibo Mao (5):
20
target/loongarch/meson: move gdbstub.c to loongarch.ss
20
target/loongarch: Use actual operand size with vbsrl check
21
target/loongarch: move translate modules to tcg/
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hw/loongarch/virt: Create fdt table on machine creation done notification
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hw/loongarch/virt: Improve fdt table creation for CPU object
23
target/loongarch: Use auto method with LSX feature
24
target/loongarch: Use auto method with LASX feature
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25
23
target/loongarch/meson.build | 15 +--------------
26
Guo Hongyu (1):
24
target/loongarch/{ => tcg}/constant_timer.c | 0
27
target/loongarch: Fix vldi inst
25
target/loongarch/{ => tcg}/csr_helper.c | 0
28
26
target/loongarch/{ => tcg}/fpu_helper.c | 0
29
hw/loongarch/virt.c | 142 ++++++++++++++----------
27
.../loongarch/{ => tcg}/insn_trans/trans_arith.c.inc | 0
30
target/loongarch/cpu.c | 86 ++++++++------
28
.../loongarch/{ => tcg}/insn_trans/trans_atomic.c.inc | 0
31
target/loongarch/cpu.h | 4 +
29
target/loongarch/{ => tcg}/insn_trans/trans_bit.c.inc | 0
32
target/loongarch/kvm/kvm.c | 107 ++++++++++++++++++
30
.../loongarch/{ => tcg}/insn_trans/trans_branch.c.inc | 0
33
target/loongarch/tcg/insn_trans/trans_vec.c.inc | 4 +-
31
.../loongarch/{ => tcg}/insn_trans/trans_extra.c.inc | 0
34
5 files changed, 249 insertions(+), 94 deletions(-)
32
.../loongarch/{ => tcg}/insn_trans/trans_farith.c.inc | 0
33
.../loongarch/{ => tcg}/insn_trans/trans_fcmp.c.inc | 0
34
.../loongarch/{ => tcg}/insn_trans/trans_fcnv.c.inc | 0
35
.../{ => tcg}/insn_trans/trans_fmemory.c.inc | 0
36
.../loongarch/{ => tcg}/insn_trans/trans_fmov.c.inc | 0
37
.../loongarch/{ => tcg}/insn_trans/trans_memory.c.inc | 0
38
.../{ => tcg}/insn_trans/trans_privileged.c.inc | 0
39
.../loongarch/{ => tcg}/insn_trans/trans_shift.c.inc | 0
40
target/loongarch/{ => tcg}/insn_trans/trans_vec.c.inc | 0
41
target/loongarch/{ => tcg}/iocsr_helper.c | 0
42
target/loongarch/tcg/meson.build | 19 +++++++++++++++++++
43
target/loongarch/{ => tcg}/op_helper.c | 0
44
target/loongarch/{ => tcg}/tlb_helper.c | 0
45
target/loongarch/{ => tcg}/translate.c | 0
46
target/loongarch/{ => tcg}/vec_helper.c | 0
47
24 files changed, 20 insertions(+), 14 deletions(-)
48
rename target/loongarch/{ => tcg}/constant_timer.c (100%)
49
rename target/loongarch/{ => tcg}/csr_helper.c (100%)
50
rename target/loongarch/{ => tcg}/fpu_helper.c (100%)
51
rename target/loongarch/{ => tcg}/insn_trans/trans_arith.c.inc (100%)
52
rename target/loongarch/{ => tcg}/insn_trans/trans_atomic.c.inc (100%)
53
rename target/loongarch/{ => tcg}/insn_trans/trans_bit.c.inc (100%)
54
rename target/loongarch/{ => tcg}/insn_trans/trans_branch.c.inc (100%)
55
rename target/loongarch/{ => tcg}/insn_trans/trans_extra.c.inc (100%)
56
rename target/loongarch/{ => tcg}/insn_trans/trans_farith.c.inc (100%)
57
rename target/loongarch/{ => tcg}/insn_trans/trans_fcmp.c.inc (100%)
58
rename target/loongarch/{ => tcg}/insn_trans/trans_fcnv.c.inc (100%)
59
rename target/loongarch/{ => tcg}/insn_trans/trans_fmemory.c.inc (100%)
60
rename target/loongarch/{ => tcg}/insn_trans/trans_fmov.c.inc (100%)
61
rename target/loongarch/{ => tcg}/insn_trans/trans_memory.c.inc (100%)
62
rename target/loongarch/{ => tcg}/insn_trans/trans_privileged.c.inc (100%)
63
rename target/loongarch/{ => tcg}/insn_trans/trans_shift.c.inc (100%)
64
rename target/loongarch/{ => tcg}/insn_trans/trans_vec.c.inc (100%)
65
rename target/loongarch/{ => tcg}/iocsr_helper.c (100%)
66
create mode 100644 target/loongarch/tcg/meson.build
67
rename target/loongarch/{ => tcg}/op_helper.c (100%)
68
rename target/loongarch/{ => tcg}/tlb_helper.c (100%)
69
rename target/loongarch/{ => tcg}/translate.c (100%)
70
rename target/loongarch/{ => tcg}/vec_helper.c (100%)
diff view generated by jsdifflib
[PULL v2 2/2] target/loongarch: move translate modules to tcg/
[PULL v2 1/6] target/loongarch: Fix vldi inst
1
Introduce the target/loongarch/tcg directory. Its purpose is to hold the TCG
1
From: Guo Hongyu <guohongyu24@mails.ucas.ac.cn>
2
code that is selected by CONFIG_TCG
3
2
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
3
Refer to the link below for a description of the vldi instructions:
5
Signed-off-by: Song Gao <gaosong@loongson.cn>
4
https://jia.je/unofficial-loongarch-intrinsics-guide/lsx/misc/#synopsis_88
6
Message-Id: <20240102020200.3462097-2-gaosong@loongson.cn>
5
Fixed errors in vldi instruction implementation.
6
7
Signed-off-by: Guo Hongyu <guohongyu24@mails.ucas.ac.cn>
8
Tested-by: Xianglai Li <lixianglai@loongson.cn>
9
Signed-off-by: Xianglai Li <lixianglai@loongson.cn>
10
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
11
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
7
---
12
---
8
target/loongarch/meson.build | 15 +--------------
13
target/loongarch/tcg/insn_trans/trans_vec.c.inc | 2 +-
9
target/loongarch/{ => tcg}/constant_timer.c | 0
14
1 file changed, 1 insertion(+), 1 deletion(-)
10
target/loongarch/{ => tcg}/csr_helper.c | 0
11
target/loongarch/{ => tcg}/fpu_helper.c | 0
12
.../{ => tcg}/insn_trans/trans_arith.c.inc | 0
13
.../{ => tcg}/insn_trans/trans_atomic.c.inc | 0
14
.../{ => tcg}/insn_trans/trans_bit.c.inc | 0
15
.../{ => tcg}/insn_trans/trans_branch.c.inc | 0
16
.../{ => tcg}/insn_trans/trans_extra.c.inc | 0
17
.../{ => tcg}/insn_trans/trans_farith.c.inc | 0
18
.../{ => tcg}/insn_trans/trans_fcmp.c.inc | 0
19
.../{ => tcg}/insn_trans/trans_fcnv.c.inc | 0
20
.../{ => tcg}/insn_trans/trans_fmemory.c.inc | 0
21
.../{ => tcg}/insn_trans/trans_fmov.c.inc | 0
22
.../{ => tcg}/insn_trans/trans_memory.c.inc | 0
23
.../insn_trans/trans_privileged.c.inc | 0
24
.../{ => tcg}/insn_trans/trans_shift.c.inc | 0
25
.../{ => tcg}/insn_trans/trans_vec.c.inc | 0
26
target/loongarch/{ => tcg}/iocsr_helper.c | 0
27
target/loongarch/tcg/meson.build | 19 +++++++++++++++++++
28
target/loongarch/{ => tcg}/op_helper.c | 0
29
target/loongarch/{ => tcg}/tlb_helper.c | 0
30
target/loongarch/{ => tcg}/translate.c | 0
31
target/loongarch/{ => tcg}/vec_helper.c | 0
32
24 files changed, 20 insertions(+), 14 deletions(-)
33
rename target/loongarch/{ => tcg}/constant_timer.c (100%)
34
rename target/loongarch/{ => tcg}/csr_helper.c (100%)
35
rename target/loongarch/{ => tcg}/fpu_helper.c (100%)
36
rename target/loongarch/{ => tcg}/insn_trans/trans_arith.c.inc (100%)
37
rename target/loongarch/{ => tcg}/insn_trans/trans_atomic.c.inc (100%)
38
rename target/loongarch/{ => tcg}/insn_trans/trans_bit.c.inc (100%)
39
rename target/loongarch/{ => tcg}/insn_trans/trans_branch.c.inc (100%)
40
rename target/loongarch/{ => tcg}/insn_trans/trans_extra.c.inc (100%)
41
rename target/loongarch/{ => tcg}/insn_trans/trans_farith.c.inc (100%)
42
rename target/loongarch/{ => tcg}/insn_trans/trans_fcmp.c.inc (100%)
43
rename target/loongarch/{ => tcg}/insn_trans/trans_fcnv.c.inc (100%)
44
rename target/loongarch/{ => tcg}/insn_trans/trans_fmemory.c.inc (100%)
45
rename target/loongarch/{ => tcg}/insn_trans/trans_fmov.c.inc (100%)
46
rename target/loongarch/{ => tcg}/insn_trans/trans_memory.c.inc (100%)
47
rename target/loongarch/{ => tcg}/insn_trans/trans_privileged.c.inc (100%)
48
rename target/loongarch/{ => tcg}/insn_trans/trans_shift.c.inc (100%)
49
rename target/loongarch/{ => tcg}/insn_trans/trans_vec.c.inc (100%)
50
rename target/loongarch/{ => tcg}/iocsr_helper.c (100%)
51
create mode 100644 target/loongarch/tcg/meson.build
52
rename target/loongarch/{ => tcg}/op_helper.c (100%)
53
rename target/loongarch/{ => tcg}/tlb_helper.c (100%)
54
rename target/loongarch/{ => tcg}/translate.c (100%)
55
rename target/loongarch/{ => tcg}/vec_helper.c (100%)
56
15
57
diff --git a/target/loongarch/meson.build b/target/loongarch/meson.build
16
diff --git a/target/loongarch/tcg/insn_trans/trans_vec.c.inc b/target/loongarch/tcg/insn_trans/trans_vec.c.inc
58
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
59
--- a/target/loongarch/meson.build
18
--- a/target/loongarch/tcg/insn_trans/trans_vec.c.inc
60
+++ b/target/loongarch/meson.build
19
+++ b/target/loongarch/tcg/insn_trans/trans_vec.c.inc
61
@@ -XXX,XX +XXX,XX @@ loongarch_ss.add(files(
20
@@ -XXX,XX +XXX,XX @@ static uint64_t vldi_get_value(DisasContext *ctx, uint32_t imm)
62
'cpu.c',
21
break;
63
'gdbstub.c',
22
case 1:
64
))
23
/* data: {2{16'0, imm[7:0], 8'0}} */
65
-loongarch_tcg_ss = ss.source_set()
24
- data = (t << 24) | (t << 8);
66
-loongarch_tcg_ss.add(gen)
25
+ data = (t << 40) | (t << 8);
67
-loongarch_tcg_ss.add(files(
26
break;
68
- 'fpu_helper.c',
27
case 2:
69
- 'op_helper.c',
28
/* data: {2{8'0, imm[7:0], 16'0}} */
70
- 'translate.c',
71
- 'vec_helper.c',
72
-))
73
-loongarch_tcg_ss.add(zlib)
74
75
loongarch_system_ss = ss.source_set()
76
loongarch_system_ss.add(files(
77
'loongarch-qmp-cmds.c',
78
'machine.c',
79
- 'tlb_helper.c',
80
- 'constant_timer.c',
81
- 'csr_helper.c',
82
- 'iocsr_helper.c',
83
))
84
85
common_ss.add(when: 'CONFIG_LOONGARCH_DIS', if_true: [files('disas.c'), gen])
86
87
-loongarch_ss.add_all(when: 'CONFIG_TCG', if_true: [loongarch_tcg_ss])
88
+subdir('tcg')
89
90
target_arch += {'loongarch': loongarch_ss}
91
target_system_arch += {'loongarch': loongarch_system_ss}
92
diff --git a/target/loongarch/constant_timer.c b/target/loongarch/tcg/constant_timer.c
93
similarity index 100%
94
rename from target/loongarch/constant_timer.c
95
rename to target/loongarch/tcg/constant_timer.c
96
diff --git a/target/loongarch/csr_helper.c b/target/loongarch/tcg/csr_helper.c
97
similarity index 100%
98
rename from target/loongarch/csr_helper.c
99
rename to target/loongarch/tcg/csr_helper.c
100
diff --git a/target/loongarch/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c
101
similarity index 100%
102
rename from target/loongarch/fpu_helper.c
103
rename to target/loongarch/tcg/fpu_helper.c
104
diff --git a/target/loongarch/insn_trans/trans_arith.c.inc b/target/loongarch/tcg/insn_trans/trans_arith.c.inc
105
similarity index 100%
106
rename from target/loongarch/insn_trans/trans_arith.c.inc
107
rename to target/loongarch/tcg/insn_trans/trans_arith.c.inc
108
diff --git a/target/loongarch/insn_trans/trans_atomic.c.inc b/target/loongarch/tcg/insn_trans/trans_atomic.c.inc
109
similarity index 100%
110
rename from target/loongarch/insn_trans/trans_atomic.c.inc
111
rename to target/loongarch/tcg/insn_trans/trans_atomic.c.inc
112
diff --git a/target/loongarch/insn_trans/trans_bit.c.inc b/target/loongarch/tcg/insn_trans/trans_bit.c.inc
113
similarity index 100%
114
rename from target/loongarch/insn_trans/trans_bit.c.inc
115
rename to target/loongarch/tcg/insn_trans/trans_bit.c.inc
116
diff --git a/target/loongarch/insn_trans/trans_branch.c.inc b/target/loongarch/tcg/insn_trans/trans_branch.c.inc
117
similarity index 100%
118
rename from target/loongarch/insn_trans/trans_branch.c.inc
119
rename to target/loongarch/tcg/insn_trans/trans_branch.c.inc
120
diff --git a/target/loongarch/insn_trans/trans_extra.c.inc b/target/loongarch/tcg/insn_trans/trans_extra.c.inc
121
similarity index 100%
122
rename from target/loongarch/insn_trans/trans_extra.c.inc
123
rename to target/loongarch/tcg/insn_trans/trans_extra.c.inc
124
diff --git a/target/loongarch/insn_trans/trans_farith.c.inc b/target/loongarch/tcg/insn_trans/trans_farith.c.inc
125
similarity index 100%
126
rename from target/loongarch/insn_trans/trans_farith.c.inc
127
rename to target/loongarch/tcg/insn_trans/trans_farith.c.inc
128
diff --git a/target/loongarch/insn_trans/trans_fcmp.c.inc b/target/loongarch/tcg/insn_trans/trans_fcmp.c.inc
129
similarity index 100%
130
rename from target/loongarch/insn_trans/trans_fcmp.c.inc
131
rename to target/loongarch/tcg/insn_trans/trans_fcmp.c.inc
132
diff --git a/target/loongarch/insn_trans/trans_fcnv.c.inc b/target/loongarch/tcg/insn_trans/trans_fcnv.c.inc
133
similarity index 100%
134
rename from target/loongarch/insn_trans/trans_fcnv.c.inc
135
rename to target/loongarch/tcg/insn_trans/trans_fcnv.c.inc
136
diff --git a/target/loongarch/insn_trans/trans_fmemory.c.inc b/target/loongarch/tcg/insn_trans/trans_fmemory.c.inc
137
similarity index 100%
138
rename from target/loongarch/insn_trans/trans_fmemory.c.inc
139
rename to target/loongarch/tcg/insn_trans/trans_fmemory.c.inc
140
diff --git a/target/loongarch/insn_trans/trans_fmov.c.inc b/target/loongarch/tcg/insn_trans/trans_fmov.c.inc
141
similarity index 100%
142
rename from target/loongarch/insn_trans/trans_fmov.c.inc
143
rename to target/loongarch/tcg/insn_trans/trans_fmov.c.inc
144
diff --git a/target/loongarch/insn_trans/trans_memory.c.inc b/target/loongarch/tcg/insn_trans/trans_memory.c.inc
145
similarity index 100%
146
rename from target/loongarch/insn_trans/trans_memory.c.inc
147
rename to target/loongarch/tcg/insn_trans/trans_memory.c.inc
148
diff --git a/target/loongarch/insn_trans/trans_privileged.c.inc b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
149
similarity index 100%
150
rename from target/loongarch/insn_trans/trans_privileged.c.inc
151
rename to target/loongarch/tcg/insn_trans/trans_privileged.c.inc
152
diff --git a/target/loongarch/insn_trans/trans_shift.c.inc b/target/loongarch/tcg/insn_trans/trans_shift.c.inc
153
similarity index 100%
154
rename from target/loongarch/insn_trans/trans_shift.c.inc
155
rename to target/loongarch/tcg/insn_trans/trans_shift.c.inc
156
diff --git a/target/loongarch/insn_trans/trans_vec.c.inc b/target/loongarch/tcg/insn_trans/trans_vec.c.inc
157
similarity index 100%
158
rename from target/loongarch/insn_trans/trans_vec.c.inc
159
rename to target/loongarch/tcg/insn_trans/trans_vec.c.inc
160
diff --git a/target/loongarch/iocsr_helper.c b/target/loongarch/tcg/iocsr_helper.c
161
similarity index 100%
162
rename from target/loongarch/iocsr_helper.c
163
rename to target/loongarch/tcg/iocsr_helper.c
164
diff --git a/target/loongarch/tcg/meson.build b/target/loongarch/tcg/meson.build
165
new file mode 100644
166
index XXXXXXX..XXXXXXX
167
--- /dev/null
168
+++ b/target/loongarch/tcg/meson.build
169
@@ -XXX,XX +XXX,XX @@
170
+if 'CONFIG_TCG' not in config_all_accel
171
+ subdir_done()
172
+endif
173
+
174
+loongarch_ss.add([zlib, gen])
175
+
176
+loongarch_ss.add(files(
177
+ 'fpu_helper.c',
178
+ 'op_helper.c',
179
+ 'translate.c',
180
+ 'vec_helper.c',
181
+))
182
+
183
+loongarch_system_ss.add(files(
184
+ 'constant_timer.c',
185
+ 'csr_helper.c',
186
+ 'iocsr_helper.c',
187
+ 'tlb_helper.c',
188
+))
189
diff --git a/target/loongarch/op_helper.c b/target/loongarch/tcg/op_helper.c
190
similarity index 100%
191
rename from target/loongarch/op_helper.c
192
rename to target/loongarch/tcg/op_helper.c
193
diff --git a/target/loongarch/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c
194
similarity index 100%
195
rename from target/loongarch/tlb_helper.c
196
rename to target/loongarch/tcg/tlb_helper.c
197
diff --git a/target/loongarch/translate.c b/target/loongarch/tcg/translate.c
198
similarity index 100%
199
rename from target/loongarch/translate.c
200
rename to target/loongarch/tcg/translate.c
201
diff --git a/target/loongarch/vec_helper.c b/target/loongarch/tcg/vec_helper.c
202
similarity index 100%
203
rename from target/loongarch/vec_helper.c
204
rename to target/loongarch/tcg/vec_helper.c
205
--
29
--
206
2.25.1
30
2.43.5
207
208
diff view generated by jsdifflib
[PULL v2 1/2] target/loongarch/meson: move gdbstub.c to loongarch.ss
[PULL v2 2/6] target/loongarch: Use actual operand size with vbsrl check
1
gdbstub.c is not specific to TCG and can be used by
1
Hardcoded 32 bytes is used for vbsrl emulation check, there is
2
other accelerators, such as KVM accelerator
2
problem when options lsx=on,lasx=off is used for vbsrl.v instruction
3
in TCG mode. It injects LASX exception rather LSX exception.
3
4
5
Here actual operand size is used.
6
7
Cc: qemu-stable@nongnu.org
8
Fixes: df97f338076 ("target/loongarch: Implement xvreplve xvinsve0 xvpickve")
9
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
Signed-off-by: Song Gao <gaosong@loongson.cn>
6
Message-Id: <20240102020200.3462097-1-gaosong@loongson.cn>
7
---
12
---
8
target/loongarch/meson.build | 2 +-
13
target/loongarch/tcg/insn_trans/trans_vec.c.inc | 2 +-
9
1 file changed, 1 insertion(+), 1 deletion(-)
14
1 file changed, 1 insertion(+), 1 deletion(-)
10
15
11
diff --git a/target/loongarch/meson.build b/target/loongarch/meson.build
16
diff --git a/target/loongarch/tcg/insn_trans/trans_vec.c.inc b/target/loongarch/tcg/insn_trans/trans_vec.c.inc
12
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
13
--- a/target/loongarch/meson.build
18
--- a/target/loongarch/tcg/insn_trans/trans_vec.c.inc
14
+++ b/target/loongarch/meson.build
19
+++ b/target/loongarch/tcg/insn_trans/trans_vec.c.inc
15
@@ -XXX,XX +XXX,XX @@ gen = decodetree.process('insns.decode')
20
@@ -XXX,XX +XXX,XX @@ static bool do_vbsrl_v(DisasContext *ctx, arg_vv_i *a, uint32_t oprsz)
16
loongarch_ss = ss.source_set()
21
{
17
loongarch_ss.add(files(
22
int i, ofs;
18
'cpu.c',
23
19
+ 'gdbstub.c',
24
- if (!check_vec(ctx, 32)) {
20
))
25
+ if (!check_vec(ctx, oprsz)) {
21
loongarch_tcg_ss = ss.source_set()
26
return true;
22
loongarch_tcg_ss.add(gen)
27
}
23
@@ -XXX,XX +XXX,XX @@ loongarch_tcg_ss.add(files(
28
24
'fpu_helper.c',
25
'op_helper.c',
26
'translate.c',
27
- 'gdbstub.c',
28
'vec_helper.c',
29
))
30
loongarch_tcg_ss.add(zlib)
31
--
29
--
32
2.25.1
30
2.43.5
33
31
34
32
diff view generated by jsdifflib
New patch
[PULL v2 3/6] hw/loongarch/virt: Create fdt table on machine creation done notification
1
The same with ACPI table, fdt table is created on machine done
2
notification. Some objects like CPU objects can be created with cold-plug
3
method with command such as -smp x, -device la464-loongarch-cpu, so all
4
objects finish to create when machine is done.
1
5
6
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
7
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
8
---
9
hw/loongarch/virt.c | 103 ++++++++++++++++++++++++--------------------
10
1 file changed, 57 insertions(+), 46 deletions(-)
11
12
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/hw/loongarch/virt.c
15
+++ b/hw/loongarch/virt.c
16
@@ -XXX,XX +XXX,XX @@ static void virt_build_smbios(LoongArchVirtMachineState *lvms)
17
}
18
}
19
20
+static void virt_fdt_setup(LoongArchVirtMachineState *lvms)
21
+{
22
+ MachineState *machine = MACHINE(lvms);
23
+ uint32_t cpuintc_phandle, eiointc_phandle, pch_pic_phandle, pch_msi_phandle;
24
+ int i;
25
+
26
+ create_fdt(lvms);
27
+ fdt_add_cpu_nodes(lvms);
28
+ fdt_add_memory_nodes(machine);
29
+ fdt_add_fw_cfg_node(lvms);
30
+ fdt_add_flash_node(lvms);
31
+
32
+ /* Add cpu interrupt-controller */
33
+ fdt_add_cpuic_node(lvms, &cpuintc_phandle);
34
+ /* Add Extend I/O Interrupt Controller node */
35
+ fdt_add_eiointc_node(lvms, &cpuintc_phandle, &eiointc_phandle);
36
+ /* Add PCH PIC node */
37
+ fdt_add_pch_pic_node(lvms, &eiointc_phandle, &pch_pic_phandle);
38
+ /* Add PCH MSI node */
39
+ fdt_add_pch_msi_node(lvms, &eiointc_phandle, &pch_msi_phandle);
40
+ /* Add pcie node */
41
+ fdt_add_pcie_node(lvms, &pch_pic_phandle, &pch_msi_phandle);
42
+
43
+ /*
44
+ * Create uart fdt node in reverse order so that they appear
45
+ * in the finished device tree lowest address first
46
+ */
47
+ for (i = VIRT_UART_COUNT; i-- > 0;) {
48
+ hwaddr base = VIRT_UART_BASE + i * VIRT_UART_SIZE;
49
+ int irq = VIRT_UART_IRQ + i - VIRT_GSI_BASE;
50
+ fdt_add_uart_node(lvms, &pch_pic_phandle, base, irq, i == 0);
51
+ }
52
+
53
+ fdt_add_rtc_node(lvms, &pch_pic_phandle);
54
+ fdt_add_ged_reset(lvms);
55
+ platform_bus_add_all_fdt_nodes(machine->fdt, "/platic",
56
+ VIRT_PLATFORM_BUS_BASEADDRESS,
57
+ VIRT_PLATFORM_BUS_SIZE,
58
+ VIRT_PLATFORM_BUS_IRQ);
59
+
60
+ /*
61
+ * Since lowmem region starts from 0 and Linux kernel legacy start address
62
+ * at 2 MiB, FDT base address is located at 1 MiB to avoid NULL pointer
63
+ * access. FDT size limit with 1 MiB.
64
+ * Put the FDT into the memory map as a ROM image: this will ensure
65
+ * the FDT is copied again upon reset, even if addr points into RAM.
66
+ */
67
+ qemu_fdt_dumpdtb(machine->fdt, lvms->fdt_size);
68
+ rom_add_blob_fixed_as("fdt", machine->fdt, lvms->fdt_size, FDT_BASE,
69
+ &address_space_memory);
70
+ qemu_register_reset_nosnapshotload(qemu_fdt_randomize_seeds,
71
+ rom_ptr_for_as(&address_space_memory, FDT_BASE, lvms->fdt_size));
72
+}
73
+
74
static void virt_done(Notifier *notifier, void *data)
75
{
76
LoongArchVirtMachineState *lvms = container_of(notifier,
77
LoongArchVirtMachineState, machine_done);
78
virt_build_smbios(lvms);
79
loongarch_acpi_setup(lvms);
80
+ virt_fdt_setup(lvms);
81
}
82
83
static void virt_powerdown_req(Notifier *notifier, void *opaque)
84
@@ -XXX,XX +XXX,XX @@ static DeviceState *create_platform_bus(DeviceState *pch_pic)
85
}
86
87
static void virt_devices_init(DeviceState *pch_pic,
88
- LoongArchVirtMachineState *lvms,
89
- uint32_t *pch_pic_phandle,
90
- uint32_t *pch_msi_phandle)
91
+ LoongArchVirtMachineState *lvms)
92
{
93
MachineClass *mc = MACHINE_GET_CLASS(lvms);
94
DeviceState *gpex_dev;
95
@@ -XXX,XX +XXX,XX @@ static void virt_devices_init(DeviceState *pch_pic,
96
gpex_set_irq_num(GPEX_HOST(gpex_dev), i, 16 + i);
97
}
98
99
- /* Add pcie node */
100
- fdt_add_pcie_node(lvms, pch_pic_phandle, pch_msi_phandle);
101
-
102
/*
103
* Create uart fdt node in reverse order so that they appear
104
* in the finished device tree lowest address first
105
@@ -XXX,XX +XXX,XX @@ static void virt_devices_init(DeviceState *pch_pic,
106
serial_mm_init(get_system_memory(), base, 0,
107
qdev_get_gpio_in(pch_pic, irq),
108
115200, serial_hd(i), DEVICE_LITTLE_ENDIAN);
109
- fdt_add_uart_node(lvms, pch_pic_phandle, base, irq, i == 0);
110
}
111
112
/* Network init */
113
@@ -XXX,XX +XXX,XX @@ static void virt_devices_init(DeviceState *pch_pic,
114
sysbus_create_simple("ls7a_rtc", VIRT_RTC_REG_BASE,
115
qdev_get_gpio_in(pch_pic,
116
VIRT_RTC_IRQ - VIRT_GSI_BASE));
117
- fdt_add_rtc_node(lvms, pch_pic_phandle);
118
- fdt_add_ged_reset(lvms);
119
120
/* acpi ged */
121
lvms->acpi_ged = create_acpi_ged(pch_pic, lvms);
122
@@ -XXX,XX +XXX,XX @@ static void virt_irq_init(LoongArchVirtMachineState *lvms)
123
CPULoongArchState *env;
124
CPUState *cpu_state;
125
int cpu, pin, i, start, num;
126
- uint32_t cpuintc_phandle, eiointc_phandle, pch_pic_phandle, pch_msi_phandle;
127
128
/*
129
* Extended IRQ model.
130
@@ -XXX,XX +XXX,XX @@ static void virt_irq_init(LoongArchVirtMachineState *lvms)
131
memory_region_add_subregion(&lvms->system_iocsr, MAIL_SEND_ADDR,
132
sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 1));
133
134
- /* Add cpu interrupt-controller */
135
- fdt_add_cpuic_node(lvms, &cpuintc_phandle);
136
-
137
for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
138
cpu_state = qemu_get_cpu(cpu);
139
cpudev = DEVICE(cpu_state);
140
@@ -XXX,XX +XXX,XX @@ static void virt_irq_init(LoongArchVirtMachineState *lvms)
141
}
142
}
143
144
- /* Add Extend I/O Interrupt Controller node */
145
- fdt_add_eiointc_node(lvms, &cpuintc_phandle, &eiointc_phandle);
146
-
147
pch_pic = qdev_new(TYPE_LOONGARCH_PIC);
148
num = VIRT_PCH_PIC_IRQ_NUM;
149
qdev_prop_set_uint32(pch_pic, "pch_pic_irq_num", num);
150
@@ -XXX,XX +XXX,XX @@ static void virt_irq_init(LoongArchVirtMachineState *lvms)
151
qdev_connect_gpio_out(DEVICE(d), i, qdev_get_gpio_in(extioi, i));
152
}
153
154
- /* Add PCH PIC node */
155
- fdt_add_pch_pic_node(lvms, &eiointc_phandle, &pch_pic_phandle);
156
-
157
pch_msi = qdev_new(TYPE_LOONGARCH_PCH_MSI);
158
start = num;
159
num = EXTIOI_IRQS - start;
160
@@ -XXX,XX +XXX,XX @@ static void virt_irq_init(LoongArchVirtMachineState *lvms)
161
qdev_get_gpio_in(extioi, i + start));
162
}
163
164
- /* Add PCH MSI node */
165
- fdt_add_pch_msi_node(lvms, &eiointc_phandle, &pch_msi_phandle);
166
-
167
- virt_devices_init(pch_pic, lvms, &pch_pic_phandle, &pch_msi_phandle);
168
+ virt_devices_init(pch_pic, lvms);
169
}
170
171
static void virt_firmware_init(LoongArchVirtMachineState *lvms)
172
@@ -XXX,XX +XXX,XX @@ static void virt_init(MachineState *machine)
173
cpu_model = LOONGARCH_CPU_TYPE_NAME("la464");
174
}
175
176
- create_fdt(lvms);
177
-
178
/* Create IOCSR space */
179
memory_region_init_io(&lvms->system_iocsr, OBJECT(machine), NULL,
180
machine, "iocsr", UINT64_MAX);
181
@@ -XXX,XX +XXX,XX @@ static void virt_init(MachineState *machine)
182
lacpu = LOONGARCH_CPU(cpu);
183
lacpu->phy_id = machine->possible_cpus->cpus[i].arch_id;
184
}
185
- fdt_add_cpu_nodes(lvms);
186
- fdt_add_memory_nodes(machine);
187
fw_cfg_add_memory(machine);
188
189
/* Node0 memory */
190
@@ -XXX,XX +XXX,XX @@ static void virt_init(MachineState *machine)
191
memmap_table,
192
sizeof(struct memmap_entry) * (memmap_entries));
193
}
194
- fdt_add_fw_cfg_node(lvms);
195
- fdt_add_flash_node(lvms);
196
197
/* Initialize the IO interrupt subsystem */
198
virt_irq_init(lvms);
199
- platform_bus_add_all_fdt_nodes(machine->fdt, "/platic",
200
- VIRT_PLATFORM_BUS_BASEADDRESS,
201
- VIRT_PLATFORM_BUS_SIZE,
202
- VIRT_PLATFORM_BUS_IRQ);
203
lvms->machine_done.notify = virt_done;
204
qemu_add_machine_init_done_notifier(&lvms->machine_done);
205
/* connect powerdown request */
206
lvms->powerdown_notifier.notify = virt_powerdown_req;
207
qemu_register_powerdown_notifier(&lvms->powerdown_notifier);
208
209
- /*
210
- * Since lowmem region starts from 0 and Linux kernel legacy start address
211
- * at 2 MiB, FDT base address is located at 1 MiB to avoid NULL pointer
212
- * access. FDT size limit with 1 MiB.
213
- * Put the FDT into the memory map as a ROM image: this will ensure
214
- * the FDT is copied again upon reset, even if addr points into RAM.
215
- */
216
- qemu_fdt_dumpdtb(machine->fdt, lvms->fdt_size);
217
- rom_add_blob_fixed_as("fdt", machine->fdt, lvms->fdt_size, FDT_BASE,
218
- &address_space_memory);
219
- qemu_register_reset_nosnapshotload(qemu_fdt_randomize_seeds,
220
- rom_ptr_for_as(&address_space_memory, FDT_BASE, lvms->fdt_size));
221
-
222
lvms->bootinfo.ram_size = ram_size;
223
loongarch_load_kernel(machine, &lvms->bootinfo);
224
}
225
--
226
2.43.5
diff view generated by jsdifflib
New patch
[PULL v2 4/6] hw/loongarch/virt: Improve fdt table creation for CPU object
1
For CPU object, possible_cpu_arch_ids() function is used rather than
2
smp.cpus. With command -smp x, -device la464-loongarch-cpu, smp.cpus
3
is not accurate for all possible CPU objects, possible_cpu_arch_ids()
4
is used here.
1
5
6
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
7
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
8
---
9
hw/loongarch/virt.c | 39 +++++++++++++++++++++++++--------------
10
1 file changed, 25 insertions(+), 14 deletions(-)
11
12
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/hw/loongarch/virt.c
15
+++ b/hw/loongarch/virt.c
16
@@ -XXX,XX +XXX,XX @@ static void create_fdt(LoongArchVirtMachineState *lvms)
17
static void fdt_add_cpu_nodes(const LoongArchVirtMachineState *lvms)
18
{
19
int num;
20
- const MachineState *ms = MACHINE(lvms);
21
- int smp_cpus = ms->smp.cpus;
22
+ MachineState *ms = MACHINE(lvms);
23
+ MachineClass *mc = MACHINE_GET_CLASS(ms);
24
+ const CPUArchIdList *possible_cpus;
25
+ LoongArchCPU *cpu;
26
+ CPUState *cs;
27
+ char *nodename, *map_path;
28
29
qemu_fdt_add_subnode(ms->fdt, "/cpus");
30
qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1);
31
qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0);
32
33
/* cpu nodes */
34
- for (num = smp_cpus - 1; num >= 0; num--) {
35
- char *nodename = g_strdup_printf("/cpus/cpu@%d", num);
36
- LoongArchCPU *cpu = LOONGARCH_CPU(qemu_get_cpu(num));
37
- CPUState *cs = CPU(cpu);
38
+ possible_cpus = mc->possible_cpu_arch_ids(ms);
39
+ for (num = 0; num < possible_cpus->len; num++) {
40
+ cs = possible_cpus->cpus[num].cpu;
41
+ if (cs == NULL) {
42
+ continue;
43
+ }
44
+
45
+ nodename = g_strdup_printf("/cpus/cpu@%d", num);
46
+ cpu = LOONGARCH_CPU(cs);
47
48
qemu_fdt_add_subnode(ms->fdt, nodename);
49
qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu");
50
qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
51
cpu->dtb_compatible);
52
- if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) {
53
+ if (possible_cpus->cpus[num].props.has_node_id) {
54
qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id",
55
- ms->possible_cpus->cpus[cs->cpu_index].props.node_id);
56
+ possible_cpus->cpus[num].props.node_id);
57
}
58
qemu_fdt_setprop_cell(ms->fdt, nodename, "reg", num);
59
qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle",
60
@@ -XXX,XX +XXX,XX @@ static void fdt_add_cpu_nodes(const LoongArchVirtMachineState *lvms)
61
62
/*cpu map */
63
qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map");
64
+ for (num = 0; num < possible_cpus->len; num++) {
65
+ cs = possible_cpus->cpus[num].cpu;
66
+ if (cs == NULL) {
67
+ continue;
68
+ }
69
70
- for (num = smp_cpus - 1; num >= 0; num--) {
71
- char *cpu_path = g_strdup_printf("/cpus/cpu@%d", num);
72
- char *map_path;
73
-
74
+ nodename = g_strdup_printf("/cpus/cpu@%d", num);
75
if (ms->smp.threads > 1) {
76
map_path = g_strdup_printf(
77
"/cpus/cpu-map/socket%d/core%d/thread%d",
78
@@ -XXX,XX +XXX,XX @@ static void fdt_add_cpu_nodes(const LoongArchVirtMachineState *lvms)
79
num % ms->smp.cores);
80
}
81
qemu_fdt_add_path(ms->fdt, map_path);
82
- qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", cpu_path);
83
+ qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", nodename);
84
85
g_free(map_path);
86
- g_free(cpu_path);
87
+ g_free(nodename);
88
}
89
}
90
91
--
92
2.43.5
diff view generated by jsdifflib
New patch
[PULL v2 5/6] target/loongarch: Use auto method with LSX feature
1
Like LBT feature, add type OnOffAuto for LSX feature setting. Also
2
add LSX feature detection with new VM ioctl command, fallback to old
3
method if it is not supported.
1
4
5
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
6
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
7
---
8
target/loongarch/cpu.c | 38 +++++++++++++++------------
9
target/loongarch/cpu.h | 2 ++
10
target/loongarch/kvm/kvm.c | 54 ++++++++++++++++++++++++++++++++++++++
11
3 files changed, 77 insertions(+), 17 deletions(-)
12
13
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/loongarch/cpu.c
16
+++ b/target/loongarch/cpu.c
17
@@ -XXX,XX +XXX,XX @@ static void loongarch_la464_initfn(Object *obj)
18
{
19
LoongArchCPU *cpu = LOONGARCH_CPU(obj);
20
CPULoongArchState *env = &cpu->env;
21
+ uint32_t data = 0;
22
int i;
23
24
for (i = 0; i < 21; i++) {
25
@@ -XXX,XX +XXX,XX @@ static void loongarch_la464_initfn(Object *obj)
26
cpu->dtb_compatible = "loongarch,Loongson-3A5000";
27
env->cpucfg[0] = 0x14c010; /* PRID */
28
29
- uint32_t data = 0;
30
data = FIELD_DP32(data, CPUCFG1, ARCH, 2);
31
data = FIELD_DP32(data, CPUCFG1, PGMMU, 1);
32
data = FIELD_DP32(data, CPUCFG1, IOCSR, 1);
33
@@ -XXX,XX +XXX,XX @@ static void loongarch_la132_initfn(Object *obj)
34
{
35
LoongArchCPU *cpu = LOONGARCH_CPU(obj);
36
CPULoongArchState *env = &cpu->env;
37
-
38
+ uint32_t data = 0;
39
int i;
40
41
for (i = 0; i < 21; i++) {
42
@@ -XXX,XX +XXX,XX @@ static void loongarch_la132_initfn(Object *obj)
43
cpu->dtb_compatible = "loongarch,Loongson-1C103";
44
env->cpucfg[0] = 0x148042; /* PRID */
45
46
- uint32_t data = 0;
47
data = FIELD_DP32(data, CPUCFG1, ARCH, 1); /* LA32 */
48
data = FIELD_DP32(data, CPUCFG1, PGMMU, 1);
49
data = FIELD_DP32(data, CPUCFG1, IOCSR, 1);
50
@@ -XXX,XX +XXX,XX @@ static void loongarch_cpu_realizefn(DeviceState *dev, Error **errp)
51
52
static bool loongarch_get_lsx(Object *obj, Error **errp)
53
{
54
- LoongArchCPU *cpu = LOONGARCH_CPU(obj);
55
- bool ret;
56
-
57
- if (FIELD_EX32(cpu->env.cpucfg[2], CPUCFG2, LSX)) {
58
- ret = true;
59
- } else {
60
- ret = false;
61
- }
62
- return ret;
63
+ return LOONGARCH_CPU(obj)->lsx != ON_OFF_AUTO_OFF;
64
}
65
66
static void loongarch_set_lsx(Object *obj, bool value, Error **errp)
67
{
68
LoongArchCPU *cpu = LOONGARCH_CPU(obj);
69
+ uint32_t val;
70
71
- if (value) {
72
- cpu->env.cpucfg[2] = FIELD_DP32(cpu->env.cpucfg[2], CPUCFG2, LSX, 1);
73
- } else {
74
- cpu->env.cpucfg[2] = FIELD_DP32(cpu->env.cpucfg[2], CPUCFG2, LSX, 0);
75
- cpu->env.cpucfg[2] = FIELD_DP32(cpu->env.cpucfg[2], CPUCFG2, LASX, 0);
76
+ cpu->lsx = value ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF;
77
+ if (kvm_enabled()) {
78
+ /* kvm feature detection in function kvm_arch_init_vcpu */
79
+ return;
80
}
81
+
82
+ /* LSX feature detection in TCG mode */
83
+ val = cpu->env.cpucfg[2];
84
+ if (cpu->lsx == ON_OFF_AUTO_ON) {
85
+ if (FIELD_EX32(val, CPUCFG2, LSX) == 0) {
86
+ error_setg(errp, "Failed to enable LSX in TCG mode");
87
+ return;
88
+ }
89
+ }
90
+
91
+ cpu->env.cpucfg[2] = FIELD_DP32(val, CPUCFG2, LSX, value);
92
}
93
94
static bool loongarch_get_lasx(Object *obj, Error **errp)
95
@@ -XXX,XX +XXX,XX @@ void loongarch_cpu_post_init(Object *obj)
96
{
97
LoongArchCPU *cpu = LOONGARCH_CPU(obj);
98
99
+ cpu->lsx = ON_OFF_AUTO_AUTO;
100
object_property_add_bool(obj, "lsx", loongarch_get_lsx,
101
loongarch_set_lsx);
102
object_property_add_bool(obj, "lasx", loongarch_get_lasx,
103
@@ -XXX,XX +XXX,XX @@ void loongarch_cpu_post_init(Object *obj)
104
105
} else {
106
cpu->lbt = ON_OFF_AUTO_OFF;
107
+ cpu->pmu = ON_OFF_AUTO_OFF;
108
}
109
}
110
111
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
112
index XXXXXXX..XXXXXXX 100644
113
--- a/target/loongarch/cpu.h
114
+++ b/target/loongarch/cpu.h
115
@@ -XXX,XX +XXX,XX @@ typedef struct LoongArchTLB LoongArchTLB;
116
#endif
117
118
enum loongarch_features {
119
+ LOONGARCH_FEATURE_LSX,
120
LOONGARCH_FEATURE_LBT, /* loongson binary translation extension */
121
LOONGARCH_FEATURE_PMU,
122
};
123
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
124
uint32_t phy_id;
125
OnOffAuto lbt;
126
OnOffAuto pmu;
127
+ OnOffAuto lsx;
128
129
/* 'compatible' string for this CPU for Linux device trees */
130
const char *dtb_compatible;
131
diff --git a/target/loongarch/kvm/kvm.c b/target/loongarch/kvm/kvm.c
132
index XXXXXXX..XXXXXXX 100644
133
--- a/target/loongarch/kvm/kvm.c
134
+++ b/target/loongarch/kvm/kvm.c
135
@@ -XXX,XX +XXX,XX @@ static bool kvm_feature_supported(CPUState *cs, enum loongarch_features feature)
136
{
137
int ret;
138
struct kvm_device_attr attr;
139
+ uint64_t val;
140
141
switch (feature) {
142
+ case LOONGARCH_FEATURE_LSX:
143
+ attr.group = KVM_LOONGARCH_VM_FEAT_CTRL;
144
+ attr.attr = KVM_LOONGARCH_VM_FEAT_LSX;
145
+ ret = kvm_vm_ioctl(kvm_state, KVM_HAS_DEVICE_ATTR, &attr);
146
+ if (ret == 0) {
147
+ return true;
148
+ }
149
+
150
+ /* Fallback to old kernel detect interface */
151
+ val = 0;
152
+ attr.group = KVM_LOONGARCH_VCPU_CPUCFG;
153
+ /* Cpucfg2 */
154
+ attr.attr = 2;
155
+ attr.addr = (uint64_t)&val;
156
+ ret = kvm_vcpu_ioctl(cs, KVM_HAS_DEVICE_ATTR, &attr);
157
+ if (!ret) {
158
+ ret = kvm_vcpu_ioctl(cs, KVM_GET_DEVICE_ATTR, &attr);
159
+ if (ret) {
160
+ return false;
161
+ }
162
+
163
+ ret = FIELD_EX32((uint32_t)val, CPUCFG2, LSX);
164
+ return (ret != 0);
165
+ }
166
+ return false;
167
+
168
case LOONGARCH_FEATURE_LBT:
169
/*
170
* Return all if all the LBT features are supported such as:
171
@@ -XXX,XX +XXX,XX @@ static bool kvm_feature_supported(CPUState *cs, enum loongarch_features feature)
172
return false;
173
}
174
175
+static int kvm_cpu_check_lsx(CPUState *cs, Error **errp)
176
+{
177
+ CPULoongArchState *env = cpu_env(cs);
178
+ LoongArchCPU *cpu = LOONGARCH_CPU(cs);
179
+ bool kvm_supported;
180
+
181
+ kvm_supported = kvm_feature_supported(cs, LOONGARCH_FEATURE_LSX);
182
+ env->cpucfg[2] = FIELD_DP32(env->cpucfg[2], CPUCFG2, LSX, 0);
183
+ if (cpu->lsx == ON_OFF_AUTO_ON) {
184
+ if (kvm_supported) {
185
+ env->cpucfg[2] = FIELD_DP32(env->cpucfg[2], CPUCFG2, LSX, 1);
186
+ } else {
187
+ error_setg(errp, "'lsx' feature not supported by KVM on this host");
188
+ return -ENOTSUP;
189
+ }
190
+ } else if ((cpu->lsx == ON_OFF_AUTO_AUTO) && kvm_supported) {
191
+ env->cpucfg[2] = FIELD_DP32(env->cpucfg[2], CPUCFG2, LSX, 1);
192
+ }
193
+
194
+ return 0;
195
+}
196
+
197
static int kvm_cpu_check_lbt(CPUState *cs, Error **errp)
198
{
199
CPULoongArchState *env = cpu_env(cs);
200
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
201
brk_insn = val;
202
}
203
204
+ ret = kvm_cpu_check_lsx(cs, &local_err);
205
+ if (ret < 0) {
206
+ error_report_err(local_err);
207
+ }
208
+
209
ret = kvm_cpu_check_lbt(cs, &local_err);
210
if (ret < 0) {
211
error_report_err(local_err);
212
--
213
2.43.5
diff view generated by jsdifflib
New patch
[PULL v2 6/6] target/loongarch: Use auto method with LASX feature
1
Like LSX feature, add type OnOffAuto for LASX feature setting.
1
2
3
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
4
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
5
---
6
target/loongarch/cpu.c | 50 +++++++++++++++++++++++------------
7
target/loongarch/cpu.h | 2 ++
8
target/loongarch/kvm/kvm.c | 53 ++++++++++++++++++++++++++++++++++++++
9
3 files changed, 89 insertions(+), 16 deletions(-)
10
11
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/loongarch/cpu.c
14
+++ b/target/loongarch/cpu.c
15
@@ -XXX,XX +XXX,XX @@ static void loongarch_set_lsx(Object *obj, bool value, Error **errp)
16
uint32_t val;
17
18
cpu->lsx = value ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF;
19
+ if (cpu->lsx == ON_OFF_AUTO_OFF) {
20
+ cpu->lasx = ON_OFF_AUTO_OFF;
21
+ if (cpu->lasx == ON_OFF_AUTO_ON) {
22
+ error_setg(errp, "Failed to disable LSX since LASX is enabled");
23
+ return;
24
+ }
25
+ }
26
+
27
if (kvm_enabled()) {
28
/* kvm feature detection in function kvm_arch_init_vcpu */
29
return;
30
@@ -XXX,XX +XXX,XX @@ static void loongarch_set_lsx(Object *obj, bool value, Error **errp)
31
error_setg(errp, "Failed to enable LSX in TCG mode");
32
return;
33
}
34
+ } else {
35
+ cpu->env.cpucfg[2] = FIELD_DP32(val, CPUCFG2, LASX, 0);
36
+ val = cpu->env.cpucfg[2];
37
}
38
39
cpu->env.cpucfg[2] = FIELD_DP32(val, CPUCFG2, LSX, value);
40
@@ -XXX,XX +XXX,XX @@ static void loongarch_set_lsx(Object *obj, bool value, Error **errp)
41
42
static bool loongarch_get_lasx(Object *obj, Error **errp)
43
{
44
- LoongArchCPU *cpu = LOONGARCH_CPU(obj);
45
- bool ret;
46
-
47
- if (FIELD_EX32(cpu->env.cpucfg[2], CPUCFG2, LASX)) {
48
- ret = true;
49
- } else {
50
- ret = false;
51
- }
52
- return ret;
53
+ return LOONGARCH_CPU(obj)->lasx != ON_OFF_AUTO_OFF;
54
}
55
56
static void loongarch_set_lasx(Object *obj, bool value, Error **errp)
57
{
58
LoongArchCPU *cpu = LOONGARCH_CPU(obj);
59
+ uint32_t val;
60
61
- if (value) {
62
-    if (!FIELD_EX32(cpu->env.cpucfg[2], CPUCFG2, LSX)) {
63
- cpu->env.cpucfg[2] = FIELD_DP32(cpu->env.cpucfg[2], CPUCFG2, LSX, 1);
64
-    }
65
- cpu->env.cpucfg[2] = FIELD_DP32(cpu->env.cpucfg[2], CPUCFG2, LASX, 1);
66
- } else {
67
- cpu->env.cpucfg[2] = FIELD_DP32(cpu->env.cpucfg[2], CPUCFG2, LASX, 0);
68
+ cpu->lasx = value ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF;
69
+ if ((cpu->lsx == ON_OFF_AUTO_OFF) && (cpu->lasx == ON_OFF_AUTO_ON)) {
70
+ error_setg(errp, "Failed to enable LASX since lSX is disabled");
71
+ return;
72
+ }
73
+
74
+ if (kvm_enabled()) {
75
+ /* kvm feature detection in function kvm_arch_init_vcpu */
76
+ return;
77
}
78
+
79
+ /* LASX feature detection in TCG mode */
80
+ val = cpu->env.cpucfg[2];
81
+ if (cpu->lasx == ON_OFF_AUTO_ON) {
82
+ if (FIELD_EX32(val, CPUCFG2, LASX) == 0) {
83
+ error_setg(errp, "Failed to enable LASX in TCG mode");
84
+ return;
85
+ }
86
+ }
87
+
88
+ cpu->env.cpucfg[2] = FIELD_DP32(val, CPUCFG2, LASX, value);
89
}
90
91
static bool loongarch_get_lbt(Object *obj, Error **errp)
92
@@ -XXX,XX +XXX,XX @@ void loongarch_cpu_post_init(Object *obj)
93
LoongArchCPU *cpu = LOONGARCH_CPU(obj);
94
95
cpu->lsx = ON_OFF_AUTO_AUTO;
96
+ cpu->lasx = ON_OFF_AUTO_AUTO;
97
object_property_add_bool(obj, "lsx", loongarch_get_lsx,
98
loongarch_set_lsx);
99
object_property_add_bool(obj, "lasx", loongarch_get_lasx,
100
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
101
index XXXXXXX..XXXXXXX 100644
102
--- a/target/loongarch/cpu.h
103
+++ b/target/loongarch/cpu.h
104
@@ -XXX,XX +XXX,XX @@ typedef struct LoongArchTLB LoongArchTLB;
105
106
enum loongarch_features {
107
LOONGARCH_FEATURE_LSX,
108
+ LOONGARCH_FEATURE_LASX,
109
LOONGARCH_FEATURE_LBT, /* loongson binary translation extension */
110
LOONGARCH_FEATURE_PMU,
111
};
112
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
113
OnOffAuto lbt;
114
OnOffAuto pmu;
115
OnOffAuto lsx;
116
+ OnOffAuto lasx;
117
118
/* 'compatible' string for this CPU for Linux device trees */
119
const char *dtb_compatible;
120
diff --git a/target/loongarch/kvm/kvm.c b/target/loongarch/kvm/kvm.c
121
index XXXXXXX..XXXXXXX 100644
122
--- a/target/loongarch/kvm/kvm.c
123
+++ b/target/loongarch/kvm/kvm.c
124
@@ -XXX,XX +XXX,XX @@ static bool kvm_feature_supported(CPUState *cs, enum loongarch_features feature)
125
}
126
return false;
127
128
+ case LOONGARCH_FEATURE_LASX:
129
+ attr.group = KVM_LOONGARCH_VM_FEAT_CTRL;
130
+ attr.attr = KVM_LOONGARCH_VM_FEAT_LASX;
131
+ ret = kvm_vm_ioctl(kvm_state, KVM_HAS_DEVICE_ATTR, &attr);
132
+ if (ret == 0) {
133
+ return true;
134
+ }
135
+
136
+ /* Fallback to old kernel detect interface */
137
+ val = 0;
138
+ attr.group = KVM_LOONGARCH_VCPU_CPUCFG;
139
+ /* Cpucfg2 */
140
+ attr.attr = 2;
141
+ attr.addr = (uint64_t)&val;
142
+ ret = kvm_vcpu_ioctl(cs, KVM_HAS_DEVICE_ATTR, &attr);
143
+ if (!ret) {
144
+ ret = kvm_vcpu_ioctl(cs, KVM_GET_DEVICE_ATTR, &attr);
145
+ if (ret) {
146
+ return false;
147
+ }
148
+
149
+ ret = FIELD_EX32((uint32_t)val, CPUCFG2, LASX);
150
+ return (ret != 0);
151
+ }
152
+ return false;
153
+
154
case LOONGARCH_FEATURE_LBT:
155
/*
156
* Return all if all the LBT features are supported such as:
157
@@ -XXX,XX +XXX,XX @@ static int kvm_cpu_check_lsx(CPUState *cs, Error **errp)
158
return 0;
159
}
160
161
+static int kvm_cpu_check_lasx(CPUState *cs, Error **errp)
162
+{
163
+ CPULoongArchState *env = cpu_env(cs);
164
+ LoongArchCPU *cpu = LOONGARCH_CPU(cs);
165
+ bool kvm_supported;
166
+
167
+ kvm_supported = kvm_feature_supported(cs, LOONGARCH_FEATURE_LASX);
168
+ env->cpucfg[2] = FIELD_DP32(env->cpucfg[2], CPUCFG2, LASX, 0);
169
+ if (cpu->lasx == ON_OFF_AUTO_ON) {
170
+ if (kvm_supported) {
171
+ env->cpucfg[2] = FIELD_DP32(env->cpucfg[2], CPUCFG2, LASX, 1);
172
+ } else {
173
+ error_setg(errp, "'lasx' feature not supported by KVM on host");
174
+ return -ENOTSUP;
175
+ }
176
+ } else if ((cpu->lasx == ON_OFF_AUTO_AUTO) && kvm_supported) {
177
+ env->cpucfg[2] = FIELD_DP32(env->cpucfg[2], CPUCFG2, LASX, 1);
178
+ }
179
+
180
+ return 0;
181
+}
182
+
183
static int kvm_cpu_check_lbt(CPUState *cs, Error **errp)
184
{
185
CPULoongArchState *env = cpu_env(cs);
186
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
187
error_report_err(local_err);
188
}
189
190
+ ret = kvm_cpu_check_lasx(cs, &local_err);
191
+ if (ret < 0) {
192
+ error_report_err(local_err);
193
+ }
194
+
195
ret = kvm_cpu_check_lbt(cs, &local_err);
196
if (ret < 0) {
197
error_report_err(local_err);
198
--
199
2.43.5
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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