'priv_spec' and 'vext_spec' are two string options used as a fancy way
of setting integers in the CPU state (cpu->env.priv_ver and
cpu->env.vext_ver). It requires us to deal with string parsing and to
store them in cpu_cfg.
We must support these string options, but we don't need to store them.
We have a precedence for this kind of arrangement in target/ppc/compat.c,
ppc_compat_prop_get|set, getters and setters used for the
'max-cpu-compat' class property of the pseries ppc64 machine. We'll do
the same with both 'priv_spec' and 'vext_spec'.
For 'priv_spec', the validation from riscv_cpu_validate_priv_spec() will
be done by the prop_priv_spec_set() setter, while also preventing it to
be changed for vendor CPUs. Add two helpers that converts env->priv_ver
back and forth to its string representation. These helpers allow us to
get a string and set 'env->priv_ver' and return a string giving the
current env->priv_ver value. In other words, make the cpu->cfg.priv_spec
string obsolete.
Last but not the least, move the reworked 'priv_spec' option to
riscv_cpu_properties[].
After all said and done, we don't need to store the 'priv_spec' string in
the CPU state, and we're now protecting vendor CPUs from priv_ver
changes:
$ ./build/qemu-system-riscv64 -M virt -cpu sifive-e51,priv_spec="v1.12.0"
qemu-system-riscv64: can't apply global sifive-e51-riscv-cpu.priv_spec=v1.12.0:
CPU 'sifive-e51' does not allow changing the value of 'priv_spec'
Current 'priv_spec' val: v1.10.0
$
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/cpu.c | 73 +++++++++++++++++++++++++++++++++++++-
target/riscv/cpu.h | 3 ++
target/riscv/cpu_cfg.h | 1 -
target/riscv/tcg/tcg-cpu.c | 29 ---------------
4 files changed, 75 insertions(+), 31 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 01b3b57cee..657569d8a6 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1631,8 +1631,77 @@ static const PropertyInfo prop_pmp = {
.set = prop_pmp_set,
};
+static int priv_spec_from_str(const char *priv_spec_str)
+{
+ int priv_version = -1;
+
+ if (!g_strcmp0(priv_spec_str, PRIV_VER_1_12_0_STR)) {
+ priv_version = PRIV_VERSION_1_12_0;
+ } else if (!g_strcmp0(priv_spec_str, PRIV_VER_1_11_0_STR)) {
+ priv_version = PRIV_VERSION_1_11_0;
+ } else if (!g_strcmp0(priv_spec_str, PRIV_VER_1_10_0_STR)) {
+ priv_version = PRIV_VERSION_1_10_0;
+ }
+
+ return priv_version;
+}
+
+static const char *priv_spec_to_str(int priv_version)
+{
+ switch (priv_version) {
+ case PRIV_VERSION_1_10_0:
+ return PRIV_VER_1_10_0_STR;
+ case PRIV_VERSION_1_11_0:
+ return PRIV_VER_1_11_0_STR;
+ case PRIV_VERSION_1_12_0:
+ return PRIV_VER_1_12_0_STR;
+ default:
+ return NULL;
+ }
+}
+
+static void prop_priv_spec_set(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ RISCVCPU *cpu = RISCV_CPU(obj);
+ g_autofree char *value = NULL;
+ int priv_version = -1;
+
+ visit_type_str(v, name, &value, errp);
+
+ priv_version = priv_spec_from_str(value);
+ if (priv_version < 0) {
+ error_setg(errp, "Unsupported privilege spec version '%s'", value);
+ return;
+ }
+
+ if (priv_version != cpu->env.priv_ver && riscv_cpu_is_vendor(obj)) {
+ cpu_set_prop_err(cpu, name, errp);
+ error_append_hint(errp, "Current '%s' val: %s\n", name,
+ object_property_get_str(obj, name, NULL));
+ return;
+ }
+
+ cpu_option_add_user_setting(name, priv_version);
+ cpu->env.priv_ver = priv_version;
+}
+
+static void prop_priv_spec_get(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ RISCVCPU *cpu = RISCV_CPU(obj);
+ const char *value = priv_spec_to_str(cpu->env.priv_ver);
+
+ visit_type_str(v, name, (char **)&value, errp);
+}
+
+static const PropertyInfo prop_priv_spec = {
+ .name = "priv_spec",
+ .get = prop_priv_spec_get,
+ .set = prop_priv_spec_set,
+};
+
Property riscv_cpu_options[] = {
- DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
@@ -1653,6 +1722,8 @@ static Property riscv_cpu_properties[] = {
{.name = "mmu", .info = &prop_mmu},
{.name = "pmp", .info = &prop_pmp},
+ {.name = "priv_spec", .info = &prop_priv_spec},
+
#ifndef CONFIG_USER_ONLY
DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC),
#endif
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index bf69cb9a27..aa3d3372e3 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -77,6 +77,9 @@ const char *riscv_get_misa_ext_description(uint32_t bit);
#define CPU_CFG_OFFSET(_prop) offsetof(struct RISCVCPUConfig, _prop)
/* Privileged specification version */
+#define PRIV_VER_1_10_0_STR "v1.10.0"
+#define PRIV_VER_1_11_0_STR "v1.11.0"
+#define PRIV_VER_1_12_0_STR "v1.12.0"
enum {
PRIV_VERSION_1_10_0 = 0,
PRIV_VERSION_1_11_0,
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index c67a8731d3..2dba1f0007 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -135,7 +135,6 @@ struct RISCVCPUConfig {
bool ext_XVentanaCondOps;
uint32_t pmu_mask;
- char *priv_spec;
char *vext_spec;
uint16_t vlen;
uint16_t elen;
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index a09300e908..4d67b72d9e 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -175,29 +175,6 @@ static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp)
}
}
-static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp)
-{
- CPURISCVState *env = &cpu->env;
- int priv_version = -1;
-
- if (cpu->cfg.priv_spec) {
- if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) {
- priv_version = PRIV_VERSION_1_12_0;
- } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) {
- priv_version = PRIV_VERSION_1_11_0;
- } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
- priv_version = PRIV_VERSION_1_10_0;
- } else {
- error_setg(errp,
- "Unsupported privilege spec version '%s'",
- cpu->cfg.priv_spec);
- return;
- }
-
- env->priv_ver = priv_version;
- }
-}
-
static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg,
Error **errp)
{
@@ -625,12 +602,6 @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
CPURISCVState *env = &cpu->env;
Error *local_err = NULL;
- riscv_cpu_validate_priv_spec(cpu, &local_err);
- if (local_err != NULL) {
- error_propagate(errp, local_err);
- return;
- }
-
riscv_cpu_validate_misa_priv(env, &local_err);
if (local_err != NULL) {
error_propagate(errp, local_err);
--
2.43.0On Thu, Jan 4, 2024 at 3:41 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> 'priv_spec' and 'vext_spec' are two string options used as a fancy way
> of setting integers in the CPU state (cpu->env.priv_ver and
> cpu->env.vext_ver). It requires us to deal with string parsing and to
> store them in cpu_cfg.
>
> We must support these string options, but we don't need to store them.
> We have a precedence for this kind of arrangement in target/ppc/compat.c,
> ppc_compat_prop_get|set, getters and setters used for the
> 'max-cpu-compat' class property of the pseries ppc64 machine. We'll do
> the same with both 'priv_spec' and 'vext_spec'.
>
> For 'priv_spec', the validation from riscv_cpu_validate_priv_spec() will
> be done by the prop_priv_spec_set() setter, while also preventing it to
> be changed for vendor CPUs. Add two helpers that converts env->priv_ver
> back and forth to its string representation. These helpers allow us to
> get a string and set 'env->priv_ver' and return a string giving the
> current env->priv_ver value. In other words, make the cpu->cfg.priv_spec
> string obsolete.
>
> Last but not the least, move the reworked 'priv_spec' option to
> riscv_cpu_properties[].
>
> After all said and done, we don't need to store the 'priv_spec' string in
> the CPU state, and we're now protecting vendor CPUs from priv_ver
> changes:
>
> $ ./build/qemu-system-riscv64 -M virt -cpu sifive-e51,priv_spec="v1.12.0"
> qemu-system-riscv64: can't apply global sifive-e51-riscv-cpu.priv_spec=v1.12.0:
> CPU 'sifive-e51' does not allow changing the value of 'priv_spec'
> Current 'priv_spec' val: v1.10.0
> $
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 73 +++++++++++++++++++++++++++++++++++++-
> target/riscv/cpu.h | 3 ++
> target/riscv/cpu_cfg.h | 1 -
> target/riscv/tcg/tcg-cpu.c | 29 ---------------
> 4 files changed, 75 insertions(+), 31 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 01b3b57cee..657569d8a6 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -1631,8 +1631,77 @@ static const PropertyInfo prop_pmp = {
> .set = prop_pmp_set,
> };
>
> +static int priv_spec_from_str(const char *priv_spec_str)
> +{
> + int priv_version = -1;
> +
> + if (!g_strcmp0(priv_spec_str, PRIV_VER_1_12_0_STR)) {
> + priv_version = PRIV_VERSION_1_12_0;
> + } else if (!g_strcmp0(priv_spec_str, PRIV_VER_1_11_0_STR)) {
> + priv_version = PRIV_VERSION_1_11_0;
> + } else if (!g_strcmp0(priv_spec_str, PRIV_VER_1_10_0_STR)) {
> + priv_version = PRIV_VERSION_1_10_0;
> + }
> +
> + return priv_version;
> +}
> +
> +static const char *priv_spec_to_str(int priv_version)
> +{
> + switch (priv_version) {
> + case PRIV_VERSION_1_10_0:
> + return PRIV_VER_1_10_0_STR;
> + case PRIV_VERSION_1_11_0:
> + return PRIV_VER_1_11_0_STR;
> + case PRIV_VERSION_1_12_0:
> + return PRIV_VER_1_12_0_STR;
> + default:
> + return NULL;
> + }
> +}
> +
> +static void prop_priv_spec_set(Object *obj, Visitor *v, const char *name,
> + void *opaque, Error **errp)
> +{
> + RISCVCPU *cpu = RISCV_CPU(obj);
> + g_autofree char *value = NULL;
> + int priv_version = -1;
> +
> + visit_type_str(v, name, &value, errp);
> +
> + priv_version = priv_spec_from_str(value);
> + if (priv_version < 0) {
> + error_setg(errp, "Unsupported privilege spec version '%s'", value);
> + return;
> + }
> +
> + if (priv_version != cpu->env.priv_ver && riscv_cpu_is_vendor(obj)) {
> + cpu_set_prop_err(cpu, name, errp);
> + error_append_hint(errp, "Current '%s' val: %s\n", name,
> + object_property_get_str(obj, name, NULL));
> + return;
> + }
> +
> + cpu_option_add_user_setting(name, priv_version);
> + cpu->env.priv_ver = priv_version;
> +}
> +
> +static void prop_priv_spec_get(Object *obj, Visitor *v, const char *name,
> + void *opaque, Error **errp)
> +{
> + RISCVCPU *cpu = RISCV_CPU(obj);
> + const char *value = priv_spec_to_str(cpu->env.priv_ver);
> +
> + visit_type_str(v, name, (char **)&value, errp);
> +}
> +
> +static const PropertyInfo prop_priv_spec = {
> + .name = "priv_spec",
> + .get = prop_priv_spec_get,
> + .set = prop_priv_spec_set,
> +};
> +
> Property riscv_cpu_options[] = {
> - DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
> DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
>
> DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
> @@ -1653,6 +1722,8 @@ static Property riscv_cpu_properties[] = {
> {.name = "mmu", .info = &prop_mmu},
> {.name = "pmp", .info = &prop_pmp},
>
> + {.name = "priv_spec", .info = &prop_priv_spec},
> +
> #ifndef CONFIG_USER_ONLY
> DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC),
> #endif
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index bf69cb9a27..aa3d3372e3 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -77,6 +77,9 @@ const char *riscv_get_misa_ext_description(uint32_t bit);
> #define CPU_CFG_OFFSET(_prop) offsetof(struct RISCVCPUConfig, _prop)
>
> /* Privileged specification version */
> +#define PRIV_VER_1_10_0_STR "v1.10.0"
> +#define PRIV_VER_1_11_0_STR "v1.11.0"
> +#define PRIV_VER_1_12_0_STR "v1.12.0"
> enum {
> PRIV_VERSION_1_10_0 = 0,
> PRIV_VERSION_1_11_0,
> diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
> index c67a8731d3..2dba1f0007 100644
> --- a/target/riscv/cpu_cfg.h
> +++ b/target/riscv/cpu_cfg.h
> @@ -135,7 +135,6 @@ struct RISCVCPUConfig {
> bool ext_XVentanaCondOps;
>
> uint32_t pmu_mask;
> - char *priv_spec;
> char *vext_spec;
> uint16_t vlen;
> uint16_t elen;
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index a09300e908..4d67b72d9e 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -175,29 +175,6 @@ static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp)
> }
> }
>
> -static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp)
> -{
> - CPURISCVState *env = &cpu->env;
> - int priv_version = -1;
> -
> - if (cpu->cfg.priv_spec) {
> - if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) {
> - priv_version = PRIV_VERSION_1_12_0;
> - } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) {
> - priv_version = PRIV_VERSION_1_11_0;
> - } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
> - priv_version = PRIV_VERSION_1_10_0;
> - } else {
> - error_setg(errp,
> - "Unsupported privilege spec version '%s'",
> - cpu->cfg.priv_spec);
> - return;
> - }
> -
> - env->priv_ver = priv_version;
> - }
> -}
> -
> static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg,
> Error **errp)
> {
> @@ -625,12 +602,6 @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
> CPURISCVState *env = &cpu->env;
> Error *local_err = NULL;
>
> - riscv_cpu_validate_priv_spec(cpu, &local_err);
> - if (local_err != NULL) {
> - error_propagate(errp, local_err);
> - return;
> - }
> -
> riscv_cpu_validate_misa_priv(env, &local_err);
> if (local_err != NULL) {
> error_propagate(errp, local_err);
> --
> 2.43.0
>
>
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