Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
---
hw/arm/Kconfig | 1 +
hw/arm/stm32l4x5_soc.c | 56 ++++++++++++++++++++++++++++++++--
include/hw/arm/stm32l4x5_soc.h | 3 ++
3 files changed, 58 insertions(+), 2 deletions(-)
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 7520dc5cc0..9c9d5bb541 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -458,6 +458,7 @@ config STM32L4X5_SOC
bool
select ARM_V7M
select OR_IRQ
+ select STM32L4X5_EXTI
config XLNX_ZYNQMP_ARM
bool
diff --git a/hw/arm/stm32l4x5_soc.c b/hw/arm/stm32l4x5_soc.c
index 7513db0d6a..08b8a4c2ed 100644
--- a/hw/arm/stm32l4x5_soc.c
+++ b/hw/arm/stm32l4x5_soc.c
@@ -36,10 +36,51 @@
#define SRAM2_BASE_ADDRESS 0x10000000
#define SRAM2_SIZE (32 * KiB)
+#define EXTI_ADDR 0x40010400
+
+#define NUM_EXTI_IRQ 40
+/* Match exti line connections with their CPU IRQ number */
+/* See Vector Table (Reference Manual p.396) */
+static const int exti_irq[NUM_EXTI_IRQ] = {
+ 6, /* GPIO[0] */
+ 7, /* GPIO[1] */
+ 8, /* GPIO[2] */
+ 9, /* GPIO[3] */
+ 10, /* GPIO[4] */
+ 23, 23, 23, 23, 23, /* GPIO[5..9] */
+ 40, 40, 40, 40, 40, 40, /* GPIO[10..15] */
+ 1, /* PVD */
+ 67, /* OTG_FS_WKUP, Direct */
+ 41, /* RTC_ALARM */
+ 2, /* RTC_TAMP_STAMP2/CSS_LSE */
+ 3, /* RTC wakeup timer */
+ 63, /* COMP1 */
+ 63, /* COMP2 */
+ 31, /* I2C1 wakeup, Direct */
+ 33, /* I2C2 wakeup, Direct */
+ 72, /* I2C3 wakeup, Direct */
+ 37, /* USART1 wakeup, Direct */
+ 38, /* USART2 wakeup, Direct */
+ 39, /* USART3 wakeup, Direct */
+ 52, /* UART4 wakeup, Direct */
+ 53, /* UART4 wakeup, Direct */
+ 70, /* LPUART1 wakeup, Direct */
+ 65, /* LPTIM1, Direct */
+ 66, /* LPTIM2, Direct */
+ 76, /* SWPMI1 wakeup, Direct */
+ 1, /* PVM1 wakeup */
+ 1, /* PVM2 wakeup */
+ 1, /* PVM3 wakeup */
+ 1, /* PVM4 wakeup */
+ 78 /* LCD wakeup, Direct */
+};
+
static void stm32l4x5_soc_initfn(Object *obj)
{
Stm32l4x5SocState *s = STM32L4X5_SOC(obj);
+ object_initialize_child(obj, "exti", &s->exti, TYPE_STM32L4X5_EXTI);
+
s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
s->refclk = qdev_init_clock_in(DEVICE(s), "refclk", NULL, NULL, 0);
}
@@ -50,7 +91,9 @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
Stm32l4x5SocState *s = STM32L4X5_SOC(dev_soc);
const Stm32l4x5SocClass *sc = STM32L4X5_SOC_GET_CLASS(dev_soc);
MemoryRegion *system_memory = get_system_memory();
- DeviceState *armv7m;
+ DeviceState *dev, *armv7m;
+ SysBusDevice *busdev;
+ int i;
/*
* We use s->refclk internally and only define it with qdev_init_clock_in()
@@ -115,6 +158,16 @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
return;
}
+ dev = DEVICE(&s->exti);
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->exti), errp)) {
+ return;
+ }
+ busdev = SYS_BUS_DEVICE(dev);
+ sysbus_mmio_map(busdev, 0, EXTI_ADDR);
+ for (i = 0; i < NUM_EXTI_IRQ; i++) {
+ sysbus_connect_irq(busdev, i, qdev_get_gpio_in(armv7m, exti_irq[i]));
+ }
+
/* APB1 BUS */
create_unimplemented_device("TIM2", 0x40000000, 0x400);
create_unimplemented_device("TIM3", 0x40000400, 0x400);
@@ -155,7 +208,6 @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
create_unimplemented_device("SYSCFG", 0x40010000, 0x30);
create_unimplemented_device("VREFBUF", 0x40010030, 0x1D0);
create_unimplemented_device("COMP", 0x40010200, 0x200);
- create_unimplemented_device("EXTI", 0x40010400, 0x400);
/* RESERVED: 0x40010800, 0x1400 */
create_unimplemented_device("FIREWALL", 0x40011C00, 0x400);
/* RESERVED: 0x40012000, 0x800 */
diff --git a/include/hw/arm/stm32l4x5_soc.h b/include/hw/arm/stm32l4x5_soc.h
index dce13a023d..6cba566a31 100644
--- a/include/hw/arm/stm32l4x5_soc.h
+++ b/include/hw/arm/stm32l4x5_soc.h
@@ -28,6 +28,7 @@
#include "qemu/units.h"
#include "hw/qdev-core.h"
#include "hw/arm/armv7m.h"
+#include "hw/misc/stm32l4x5_exti.h"
#include "qom/object.h"
#define TYPE_STM32L4X5_SOC "stm32l4x5-soc"
@@ -41,6 +42,8 @@ struct Stm32l4x5SocState {
ARMv7MState armv7m;
+ Stm32l4x5ExtiState exti;
+
MemoryRegion sram1;
MemoryRegion sram2;
MemoryRegion flash;
--
2.43.0