On Fri, 2023-12-08 at 09:53 +0000, Alex Bennée wrote:
> Ilya Leoshkevich <iii@linux.ibm.com> writes:
>
> > Preparation for moving perf.c to tcg/.
> >
> > This affects only profiling guest code, which has code in a non-0
> > based
> > segment, e.g., 16-bit code, which is not particularly important.
>
> I have no objection to removing the wart. Is it worth adding a note::
> to
> tcg.rst to say that profiles of 16-bit x64 code will be junk?
>
> Anyway:
>
> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
I haven't tried them, but I don't think they work well anyway. With the
current logic, the samples are assigned to ip (without cs!), so if
there is code in different segments, there will be, to put it mildly,
ambiguities. Come to think of it, the patch even improves the
situation, since now the samples are assigned to cs*16+ip. In any
case, I don't think there is any good tooling to work with 16-bit
profiles.
> > Suggested-by: Richard Henderson <richard.henderson@linaro.org>
> > Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
> > ---
> > accel/tcg/perf.c | 4 ----
> > 1 file changed, 4 deletions(-)
> >
> > diff --git a/accel/tcg/perf.c b/accel/tcg/perf.c
> > index ba75c1bbe45..68a46b1b524 100644
> > --- a/accel/tcg/perf.c
> > +++ b/accel/tcg/perf.c
> > @@ -337,10 +337,6 @@ void perf_report_code(uint64_t guest_pc,
> > TranslationBlock *tb,
> > q[insn].address = gen_insn_data[insn * start_words + 0];
> > if (tb_cflags(tb) & CF_PCREL) {
> > q[insn].address |= (guest_pc &
> > qemu_target_page_mask());
> > - } else {
> > -#if defined(TARGET_I386)
> > - q[insn].address -= tb->cs_base;
> > -#endif
> > }
> > q[insn].flags = DEBUGINFO_SYMBOL | (jitdump ?
> > DEBUGINFO_LINE : 0);
> > }
>