Add support for (ratified) Zacas extension

[PATCH 2/2] disas/riscv: Add amocas.[w,d,q] instructions

Posted by Rob Bradford 11 months, 3 weeks ago

Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
---
 disas/riscv.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/disas/riscv.c b/disas/riscv.c
index e9458e574b..8a546d5ea5 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -903,6 +903,9 @@ typedef enum {
     rv_op_vwsll_vv = 872,
     rv_op_vwsll_vx = 873,
     rv_op_vwsll_vi = 874,
+    rv_op_amocas_w = 875,
+    rv_op_amocas_d = 876,
+    rv_op_amocas_q = 877,
 } rv_op;
 
 /* register names */
@@ -2090,6 +2093,9 @@ const rv_opcode_data rvi_opcode_data[] = {
     { "vwsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
     { "vwsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
     { "vwsll.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
+    { "amocas.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
+    { "amocas.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
+    { "amocas.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
 };
 
 /* CSR names */
@@ -2841,6 +2847,9 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
             case 34: op = rv_op_amoxor_w; break;
             case 35: op = rv_op_amoxor_d; break;
             case 36: op = rv_op_amoxor_q; break;
+            case 42: op = rv_op_amocas_w; break;
+            case 43: op = rv_op_amocas_d; break;
+            case 44: op = rv_op_amocas_q; break;
             case 66: op = rv_op_amoor_w; break;
             case 67: op = rv_op_amoor_d; break;
             case 68: op = rv_op_amoor_q; break;
-- 
2.43.0

Re: [PATCH 2/2] disas/riscv: Add amocas.[w,d,q] instructions

Posted by Alistair Francis 11 months, 2 weeks ago

On Fri, Dec 8, 2023 at 3:07 AM Rob Bradford <rbradford@rivosinc.com> wrote:
>
> Signed-off-by: Rob Bradford <rbradford@rivosinc.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  disas/riscv.c | 9 +++++++++
>  1 file changed, 9 insertions(+)
>
> diff --git a/disas/riscv.c b/disas/riscv.c
> index e9458e574b..8a546d5ea5 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -903,6 +903,9 @@ typedef enum {
>      rv_op_vwsll_vv = 872,
>      rv_op_vwsll_vx = 873,
>      rv_op_vwsll_vi = 874,
> +    rv_op_amocas_w = 875,
> +    rv_op_amocas_d = 876,
> +    rv_op_amocas_q = 877,
>  } rv_op;
>
>  /* register names */
> @@ -2090,6 +2093,9 @@ const rv_opcode_data rvi_opcode_data[] = {
>      { "vwsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
>      { "vwsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
>      { "vwsll.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
> +    { "amocas.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
> +    { "amocas.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
> +    { "amocas.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
>  };
>
>  /* CSR names */
> @@ -2841,6 +2847,9 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
>              case 34: op = rv_op_amoxor_w; break;
>              case 35: op = rv_op_amoxor_d; break;
>              case 36: op = rv_op_amoxor_q; break;
> +            case 42: op = rv_op_amocas_w; break;
> +            case 43: op = rv_op_amocas_d; break;
> +            case 44: op = rv_op_amocas_q; break;
>              case 66: op = rv_op_amoor_w; break;
>              case 67: op = rv_op_amoor_d; break;
>              case 68: op = rv_op_amoor_q; break;
> --
> 2.43.0
>
>

Re: [PATCH 2/2] disas/riscv: Add amocas.[w,d,q] instructions

Posted by Daniel Henrique Barboza 11 months, 3 weeks ago


On 12/7/23 12:32, Rob Bradford wrote:
> Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
> ---
>   disas/riscv.c | 9 +++++++++
>   1 file changed, 9 insertions(+)
> 
> diff --git a/disas/riscv.c b/disas/riscv.c
> index e9458e574b..8a546d5ea5 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -903,6 +903,9 @@ typedef enum {
>       rv_op_vwsll_vv = 872,
>       rv_op_vwsll_vx = 873,
>       rv_op_vwsll_vi = 874,
> +    rv_op_amocas_w = 875,
> +    rv_op_amocas_d = 876,
> +    rv_op_amocas_q = 877,
>   } rv_op;
>   
>   /* register names */
> @@ -2090,6 +2093,9 @@ const rv_opcode_data rvi_opcode_data[] = {
>       { "vwsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
>       { "vwsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
>       { "vwsll.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
> +    { "amocas.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
> +    { "amocas.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
> +    { "amocas.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
>   };
>   
>   /* CSR names */
> @@ -2841,6 +2847,9 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
>               case 34: op = rv_op_amoxor_w; break;
>               case 35: op = rv_op_amoxor_d; break;
>               case 36: op = rv_op_amoxor_q; break;
> +            case 42: op = rv_op_amocas_w; break;
> +            case 43: op = rv_op_amocas_d; break;
> +            case 44: op = rv_op_amocas_q; break;

scripts/checkpatch.pl will complain about this change:

2/2 Checking commit 9bddd6d4337d (disas/riscv: Add amocas.[w,d,q] instructions)
ERROR: trailing statements should be on next line
#40: FILE: disas/riscv.c:2850:
+            case 42: op = rv_op_amocas_w; break;

ERROR: trailing statements should be on next line
#41: FILE: disas/riscv.c:2851:
+            case 43: op = rv_op_amocas_d; break;

ERROR: trailing statements should be on next line
#42: FILE: disas/riscv.c:2852:
+            case 44: op = rv_op_amocas_q; break;

total: 3 errors, 0 warnings, 27 lines checked


This is an existing style problem thus I'm ignoring it. We can drop a separated patch
to fix the coding style.

Patch LGTM.


Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>



>               case 66: op = rv_op_amoor_w; break;
>               case 67: op = rv_op_amoor_d; break;
>               case 68: op = rv_op_amoor_q; break;