[v1] target/riscv: add RVV CSRs

[PATCH for-9.0 4/4] target/riscv/kvm: add RVV and Vector CSR regs

Posted by Daniel Henrique Barboza 12 months ago

Add support for RVV and Vector CSR KVM regs vstart, vl and vtype.

Support for vregs[] requires KVM side changes and an extra reg (vlenb)
and will be added later.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
 target/riscv/kvm/kvm-cpu.c | 74 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 74 insertions(+)

diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index 273c71baea..5408ead81c 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -89,6 +89,10 @@ static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type,
 
 #define RISCV_FP_D_REG(env, idx)  kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_D, idx)
 
+#define RISCV_VECTOR_CSR_REG(env, name) \
+    kvm_riscv_reg_id(env, KVM_REG_RISCV_VECTOR, \
+                     KVM_REG_RISCV_VECTOR_CSR_REG(name))
+
 #define KVM_RISCV_GET_CSR(cs, env, csr, reg) \
     do { \
         int _ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, csr), &reg); \
@@ -142,6 +146,7 @@ static KVMCPUConfig kvm_misa_ext_cfgs[] = {
     KVM_MISA_CFG(RVH, KVM_RISCV_ISA_EXT_H),
     KVM_MISA_CFG(RVI, KVM_RISCV_ISA_EXT_I),
     KVM_MISA_CFG(RVM, KVM_RISCV_ISA_EXT_M),
+    KVM_MISA_CFG(RVV, KVM_RISCV_ISA_EXT_V),
 };
 
 static void kvm_cpu_get_misa_ext_cfg(Object *obj, Visitor *v,
@@ -688,6 +693,65 @@ static void kvm_riscv_put_regs_timer(CPUState *cs)
     env->kvm_timer_dirty = false;
 }
 
+static int kvm_riscv_get_regs_vector(CPUState *cs)
+{
+    CPURISCVState *env = &RISCV_CPU(cs)->env;
+    target_ulong reg;
+    int ret = 0;
+
+    if (!riscv_has_ext(env, RVV)) {
+        return 0;
+    }
+
+    ret = kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vstart), &reg);
+    if (ret) {
+        return ret;
+    }
+    env->vstart = reg;
+
+    ret = kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vl), &reg);
+    if (ret) {
+        return ret;
+    }
+    env->vl = reg;
+
+    ret = kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vtype), &reg);
+    if (ret) {
+        return ret;
+    }
+    env->vtype = reg;
+
+    return 0;
+}
+
+static int kvm_riscv_put_regs_vector(CPUState *cs)
+{
+    CPURISCVState *env = &RISCV_CPU(cs)->env;
+    target_ulong reg;
+    int ret = 0;
+
+    if (!riscv_has_ext(env, RVV)) {
+        return 0;
+    }
+
+    reg = env->vstart;
+    ret = kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vstart), &reg);
+    if (ret) {
+        return ret;
+    }
+
+    reg = env->vl;
+    ret = kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vl), &reg);
+    if (ret) {
+        return ret;
+    }
+
+    reg = env->vtype;
+    ret = kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vtype), &reg);
+
+    return ret;
+}
+
 typedef struct KVMScratchCPU {
     int kvmfd;
     int vmfd;
@@ -989,6 +1053,11 @@ int kvm_arch_get_registers(CPUState *cs)
         return ret;
     }
 
+    ret = kvm_riscv_get_regs_vector(cs);
+    if (ret) {
+        return ret;
+    }
+
     return ret;
 }
 
@@ -1029,6 +1098,11 @@ int kvm_arch_put_registers(CPUState *cs, int level)
         return ret;
     }
 
+    ret = kvm_riscv_put_regs_vector(cs);
+    if (ret) {
+        return ret;
+    }
+
     if (KVM_PUT_RESET_STATE == level) {
         RISCVCPU *cpu = RISCV_CPU(cs);
         if (cs->cpu_index == 0) {
-- 
2.41.0

Re: [PATCH for-9.0 4/4] target/riscv/kvm: add RVV and Vector CSR regs

Posted by Alistair Francis 11 months, 3 weeks ago

On Fri, Dec 1, 2023 at 5:40 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> Add support for RVV and Vector CSR KVM regs vstart, vl and vtype.
>
> Support for vregs[] requires KVM side changes and an extra reg (vlenb)
> and will be added later.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/kvm/kvm-cpu.c | 74 ++++++++++++++++++++++++++++++++++++++
>  1 file changed, 74 insertions(+)
>
> diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
> index 273c71baea..5408ead81c 100644
> --- a/target/riscv/kvm/kvm-cpu.c
> +++ b/target/riscv/kvm/kvm-cpu.c
> @@ -89,6 +89,10 @@ static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type,
>
>  #define RISCV_FP_D_REG(env, idx)  kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_D, idx)
>
> +#define RISCV_VECTOR_CSR_REG(env, name) \
> +    kvm_riscv_reg_id(env, KVM_REG_RISCV_VECTOR, \
> +                     KVM_REG_RISCV_VECTOR_CSR_REG(name))
> +
>  #define KVM_RISCV_GET_CSR(cs, env, csr, reg) \
>      do { \
>          int _ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, csr), &reg); \
> @@ -142,6 +146,7 @@ static KVMCPUConfig kvm_misa_ext_cfgs[] = {
>      KVM_MISA_CFG(RVH, KVM_RISCV_ISA_EXT_H),
>      KVM_MISA_CFG(RVI, KVM_RISCV_ISA_EXT_I),
>      KVM_MISA_CFG(RVM, KVM_RISCV_ISA_EXT_M),
> +    KVM_MISA_CFG(RVV, KVM_RISCV_ISA_EXT_V),
>  };
>
>  static void kvm_cpu_get_misa_ext_cfg(Object *obj, Visitor *v,
> @@ -688,6 +693,65 @@ static void kvm_riscv_put_regs_timer(CPUState *cs)
>      env->kvm_timer_dirty = false;
>  }
>
> +static int kvm_riscv_get_regs_vector(CPUState *cs)
> +{
> +    CPURISCVState *env = &RISCV_CPU(cs)->env;
> +    target_ulong reg;
> +    int ret = 0;
> +
> +    if (!riscv_has_ext(env, RVV)) {
> +        return 0;
> +    }
> +
> +    ret = kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vstart), &reg);
> +    if (ret) {
> +        return ret;
> +    }
> +    env->vstart = reg;
> +
> +    ret = kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vl), &reg);
> +    if (ret) {
> +        return ret;
> +    }
> +    env->vl = reg;
> +
> +    ret = kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vtype), &reg);
> +    if (ret) {
> +        return ret;
> +    }
> +    env->vtype = reg;
> +
> +    return 0;
> +}
> +
> +static int kvm_riscv_put_regs_vector(CPUState *cs)
> +{
> +    CPURISCVState *env = &RISCV_CPU(cs)->env;
> +    target_ulong reg;
> +    int ret = 0;
> +
> +    if (!riscv_has_ext(env, RVV)) {
> +        return 0;
> +    }
> +
> +    reg = env->vstart;
> +    ret = kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vstart), &reg);
> +    if (ret) {
> +        return ret;
> +    }
> +
> +    reg = env->vl;
> +    ret = kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vl), &reg);
> +    if (ret) {
> +        return ret;
> +    }
> +
> +    reg = env->vtype;
> +    ret = kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vtype), &reg);
> +
> +    return ret;
> +}
> +
>  typedef struct KVMScratchCPU {
>      int kvmfd;
>      int vmfd;
> @@ -989,6 +1053,11 @@ int kvm_arch_get_registers(CPUState *cs)
>          return ret;
>      }
>
> +    ret = kvm_riscv_get_regs_vector(cs);
> +    if (ret) {
> +        return ret;
> +    }
> +
>      return ret;
>  }
>
> @@ -1029,6 +1098,11 @@ int kvm_arch_put_registers(CPUState *cs, int level)
>          return ret;
>      }
>
> +    ret = kvm_riscv_put_regs_vector(cs);
> +    if (ret) {
> +        return ret;
> +    }
> +
>      if (KVM_PUT_RESET_STATE == level) {
>          RISCVCPU *cpu = RISCV_CPU(cs);
>          if (cs->cpu_index == 0) {
> --
> 2.41.0
>
>

[PATCH for-9.0 1/4] linux-headers: Update to Linux v6.7-rc3
[PATCH for-9.0 2/4] linux-headers: riscv: add ptrace.h
[PATCH for-9.0 3/4] target/riscv/kvm: do PR_RISCV_V_SET_CONTROL during realize()
[PATCH for-9.0 4/4] target/riscv/kvm: add RVV and Vector CSR regs