[v1] target/riscv: add RVV CSRs

[PATCH for-9.0 2/4] linux-headers: riscv: add ptrace.h

Posted by Daniel Henrique Barboza 12 months ago

KVM vector support for RISC-V requires the linux-header ptrace.h.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
 linux-headers/asm-riscv/ptrace.h | 132 +++++++++++++++++++++++++++++++
 scripts/update-linux-headers.sh  |   3 +
 2 files changed, 135 insertions(+)
 create mode 100644 linux-headers/asm-riscv/ptrace.h

diff --git a/linux-headers/asm-riscv/ptrace.h b/linux-headers/asm-riscv/ptrace.h
new file mode 100644
index 0000000000..1e3166caca
--- /dev/null
+++ b/linux-headers/asm-riscv/ptrace.h
@@ -0,0 +1,132 @@
+/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */
+/*
+ * Copyright (C) 2012 Regents of the University of California
+ */
+
+#ifndef _ASM_RISCV_PTRACE_H
+#define _ASM_RISCV_PTRACE_H
+
+#ifndef __ASSEMBLY__
+
+#include <linux/types.h>
+
+#define PTRACE_GETFDPIC		33
+
+#define PTRACE_GETFDPIC_EXEC	0
+#define PTRACE_GETFDPIC_INTERP	1
+
+/*
+ * User-mode register state for core dumps, ptrace, sigcontext
+ *
+ * This decouples struct pt_regs from the userspace ABI.
+ * struct user_regs_struct must form a prefix of struct pt_regs.
+ */
+struct user_regs_struct {
+	unsigned long pc;
+	unsigned long ra;
+	unsigned long sp;
+	unsigned long gp;
+	unsigned long tp;
+	unsigned long t0;
+	unsigned long t1;
+	unsigned long t2;
+	unsigned long s0;
+	unsigned long s1;
+	unsigned long a0;
+	unsigned long a1;
+	unsigned long a2;
+	unsigned long a3;
+	unsigned long a4;
+	unsigned long a5;
+	unsigned long a6;
+	unsigned long a7;
+	unsigned long s2;
+	unsigned long s3;
+	unsigned long s4;
+	unsigned long s5;
+	unsigned long s6;
+	unsigned long s7;
+	unsigned long s8;
+	unsigned long s9;
+	unsigned long s10;
+	unsigned long s11;
+	unsigned long t3;
+	unsigned long t4;
+	unsigned long t5;
+	unsigned long t6;
+};
+
+struct __riscv_f_ext_state {
+	__u32 f[32];
+	__u32 fcsr;
+};
+
+struct __riscv_d_ext_state {
+	__u64 f[32];
+	__u32 fcsr;
+};
+
+struct __riscv_q_ext_state {
+	__u64 f[64] __attribute__((aligned(16)));
+	__u32 fcsr;
+	/*
+	 * Reserved for expansion of sigcontext structure.  Currently zeroed
+	 * upon signal, and must be zero upon sigreturn.
+	 */
+	__u32 reserved[3];
+};
+
+struct __riscv_ctx_hdr {
+	__u32 magic;
+	__u32 size;
+};
+
+struct __riscv_extra_ext_header {
+	__u32 __padding[129] __attribute__((aligned(16)));
+	/*
+	 * Reserved for expansion of sigcontext structure.  Currently zeroed
+	 * upon signal, and must be zero upon sigreturn.
+	 */
+	__u32 reserved;
+	struct __riscv_ctx_hdr hdr;
+};
+
+union __riscv_fp_state {
+	struct __riscv_f_ext_state f;
+	struct __riscv_d_ext_state d;
+	struct __riscv_q_ext_state q;
+};
+
+struct __riscv_v_ext_state {
+	unsigned long vstart;
+	unsigned long vl;
+	unsigned long vtype;
+	unsigned long vcsr;
+	unsigned long vlenb;
+	void *datap;
+	/*
+	 * In signal handler, datap will be set a correct user stack offset
+	 * and vector registers will be copied to the address of datap
+	 * pointer.
+	 */
+};
+
+struct __riscv_v_regset_state {
+	unsigned long vstart;
+	unsigned long vl;
+	unsigned long vtype;
+	unsigned long vcsr;
+	unsigned long vlenb;
+	char vreg[];
+};
+
+/*
+ * According to spec: The number of bits in a single vector register,
+ * VLEN >= ELEN, which must be a power of 2, and must be no greater than
+ * 2^16 = 65536bits = 8192bytes
+ */
+#define RISCV_MAX_VLENB (8192)
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* _ASM_RISCV_PTRACE_H */
diff --git a/scripts/update-linux-headers.sh b/scripts/update-linux-headers.sh
index 34295c0fe5..a0006eec6f 100755
--- a/scripts/update-linux-headers.sh
+++ b/scripts/update-linux-headers.sh
@@ -156,6 +156,9 @@ for arch in $ARCHLIST; do
         cp_portable "$tmpdir/bootparam.h" \
                     "$output/include/standard-headers/asm-$arch"
     fi
+    if [ $arch = riscv ]; then
+        cp "$tmpdir/include/asm/ptrace.h" "$output/linux-headers/asm-riscv/"
+    fi
 done
 
 rm -rf "$output/linux-headers/linux"
-- 
2.41.0

Re: [PATCH for-9.0 2/4] linux-headers: riscv: add ptrace.h

Posted by Alistair Francis 11 months, 3 weeks ago

On Fri, Dec 1, 2023 at 4:29 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> KVM vector support for RISC-V requires the linux-header ptrace.h.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Acked-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  linux-headers/asm-riscv/ptrace.h | 132 +++++++++++++++++++++++++++++++
>  scripts/update-linux-headers.sh  |   3 +
>  2 files changed, 135 insertions(+)
>  create mode 100644 linux-headers/asm-riscv/ptrace.h
>
> diff --git a/linux-headers/asm-riscv/ptrace.h b/linux-headers/asm-riscv/ptrace.h
> new file mode 100644
> index 0000000000..1e3166caca
> --- /dev/null
> +++ b/linux-headers/asm-riscv/ptrace.h
> @@ -0,0 +1,132 @@
> +/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */
> +/*
> + * Copyright (C) 2012 Regents of the University of California
> + */
> +
> +#ifndef _ASM_RISCV_PTRACE_H
> +#define _ASM_RISCV_PTRACE_H
> +
> +#ifndef __ASSEMBLY__
> +
> +#include <linux/types.h>
> +
> +#define PTRACE_GETFDPIC                33
> +
> +#define PTRACE_GETFDPIC_EXEC   0
> +#define PTRACE_GETFDPIC_INTERP 1
> +
> +/*
> + * User-mode register state for core dumps, ptrace, sigcontext
> + *
> + * This decouples struct pt_regs from the userspace ABI.
> + * struct user_regs_struct must form a prefix of struct pt_regs.
> + */
> +struct user_regs_struct {
> +       unsigned long pc;
> +       unsigned long ra;
> +       unsigned long sp;
> +       unsigned long gp;
> +       unsigned long tp;
> +       unsigned long t0;
> +       unsigned long t1;
> +       unsigned long t2;
> +       unsigned long s0;
> +       unsigned long s1;
> +       unsigned long a0;
> +       unsigned long a1;
> +       unsigned long a2;
> +       unsigned long a3;
> +       unsigned long a4;
> +       unsigned long a5;
> +       unsigned long a6;
> +       unsigned long a7;
> +       unsigned long s2;
> +       unsigned long s3;
> +       unsigned long s4;
> +       unsigned long s5;
> +       unsigned long s6;
> +       unsigned long s7;
> +       unsigned long s8;
> +       unsigned long s9;
> +       unsigned long s10;
> +       unsigned long s11;
> +       unsigned long t3;
> +       unsigned long t4;
> +       unsigned long t5;
> +       unsigned long t6;
> +};
> +
> +struct __riscv_f_ext_state {
> +       __u32 f[32];
> +       __u32 fcsr;
> +};
> +
> +struct __riscv_d_ext_state {
> +       __u64 f[32];
> +       __u32 fcsr;
> +};
> +
> +struct __riscv_q_ext_state {
> +       __u64 f[64] __attribute__((aligned(16)));
> +       __u32 fcsr;
> +       /*
> +        * Reserved for expansion of sigcontext structure.  Currently zeroed
> +        * upon signal, and must be zero upon sigreturn.
> +        */
> +       __u32 reserved[3];
> +};
> +
> +struct __riscv_ctx_hdr {
> +       __u32 magic;
> +       __u32 size;
> +};
> +
> +struct __riscv_extra_ext_header {
> +       __u32 __padding[129] __attribute__((aligned(16)));
> +       /*
> +        * Reserved for expansion of sigcontext structure.  Currently zeroed
> +        * upon signal, and must be zero upon sigreturn.
> +        */
> +       __u32 reserved;
> +       struct __riscv_ctx_hdr hdr;
> +};
> +
> +union __riscv_fp_state {
> +       struct __riscv_f_ext_state f;
> +       struct __riscv_d_ext_state d;
> +       struct __riscv_q_ext_state q;
> +};
> +
> +struct __riscv_v_ext_state {
> +       unsigned long vstart;
> +       unsigned long vl;
> +       unsigned long vtype;
> +       unsigned long vcsr;
> +       unsigned long vlenb;
> +       void *datap;
> +       /*
> +        * In signal handler, datap will be set a correct user stack offset
> +        * and vector registers will be copied to the address of datap
> +        * pointer.
> +        */
> +};
> +
> +struct __riscv_v_regset_state {
> +       unsigned long vstart;
> +       unsigned long vl;
> +       unsigned long vtype;
> +       unsigned long vcsr;
> +       unsigned long vlenb;
> +       char vreg[];
> +};
> +
> +/*
> + * According to spec: The number of bits in a single vector register,
> + * VLEN >= ELEN, which must be a power of 2, and must be no greater than
> + * 2^16 = 65536bits = 8192bytes
> + */
> +#define RISCV_MAX_VLENB (8192)
> +
> +#endif /* __ASSEMBLY__ */
> +
> +#endif /* _ASM_RISCV_PTRACE_H */
> diff --git a/scripts/update-linux-headers.sh b/scripts/update-linux-headers.sh
> index 34295c0fe5..a0006eec6f 100755
> --- a/scripts/update-linux-headers.sh
> +++ b/scripts/update-linux-headers.sh
> @@ -156,6 +156,9 @@ for arch in $ARCHLIST; do
>          cp_portable "$tmpdir/bootparam.h" \
>                      "$output/include/standard-headers/asm-$arch"
>      fi
> +    if [ $arch = riscv ]; then
> +        cp "$tmpdir/include/asm/ptrace.h" "$output/linux-headers/asm-riscv/"
> +    fi
>  done
>
>  rm -rf "$output/linux-headers/linux"
> --
> 2.41.0
>
>

[PATCH for-9.0 1/4] linux-headers: Update to Linux v6.7-rc3
[PATCH for-9.0 2/4] linux-headers: riscv: add ptrace.h
[PATCH for-9.0 3/4] target/riscv/kvm: do PR_RISCV_V_SET_CONTROL during realize()
[PATCH for-9.0 4/4] target/riscv/kvm: add RVV and Vector CSR regs