The ratified v1.0 version of RISC-V V spec section 16.6 says that 
`The instructions operate as if EEW=SEW.`.

So the whole vector register move instructions depend on the vtype
register that means the implementation needs to be fixed to raise an
illegal-instruction exception when vtype.vill=1, as is the case with
most other vector instructions.

Reference:
- https://github.com/riscv/riscv-v-spec/blob/v1.0/v-spec.adoc#whole-vector-register-move
- https://github.com/riscv/riscv-v-spec/commit/856fe5bd1cb135c39258e6ca941bf234ae63e1b1

Max Chou (2):
  target/riscv: Add vill check for whole vector register move
    instructions
  target/riscv: The whole vector register move instructions depend on
    vsew

 target/riscv/insn_trans/trans_rvv.c.inc | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

-- 
2.34.1

On Thu, Nov 30, 2023 at 3:05 AM Max Chou <max.chou@sifive.com> wrote:
>
> The ratified v1.0 version of RISC-V V spec section 16.6 says that
> `The instructions operate as if EEW=SEW.`.
>
> So the whole vector register move instructions depend on the vtype
> register that means the implementation needs to be fixed to raise an
> illegal-instruction exception when vtype.vill=1, as is the case with
> most other vector instructions.
>
> Reference:
> - https://github.com/riscv/riscv-v-spec/blob/v1.0/v-spec.adoc#whole-vector-register-move
> - https://github.com/riscv/riscv-v-spec/commit/856fe5bd1cb135c39258e6ca941bf234ae63e1b1
>
> Max Chou (2):
>   target/riscv: Add vill check for whole vector register move
>     instructions
>   target/riscv: The whole vector register move instructions depend on
>     vsew

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>  target/riscv/insn_trans/trans_rvv.c.inc | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
>
> --
> 2.34.1
>
>