On 11/24/23 07:39, Nicholas Piggin wrote:
> The timebase in ppc started out with the mftb instruction which is like
> mfspr but addressed timebase registers (TBRs) rather than SPRs. These
> instructions could be used to read TB and TBU at 268 and 269. Timebase
> could be written via the TBL and TBU SPRs at 284 and 285.
>
> The ISA changed around v2.03 to bring TB and TBU reads into the SPR
> space at 268 and 269 (access via mftb TBR-space is still supported
> but will be phased out). Later, VTB was added which is an entirely
> different register.
>
> The SPR number defines in QEMU are understandably inconsistently named.
> Change SPR 268, 269, 284, 285 to TBL, TBU, WR_TBL, WR_TBU, respectively.
>
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
> ---
> target/ppc/cpu.h | 8 ++++----
> target/ppc/helper_regs.c | 10 +++++-----
> 2 files changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index f8101ffa29..848e583c2d 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -1750,8 +1750,8 @@ void ppc_compat_add_property(Object *obj, const char *name,
> #define SPR_USPRG5 (0x105)
> #define SPR_USPRG6 (0x106)
> #define SPR_USPRG7 (0x107)
> -#define SPR_VTBL (0x10C)
> -#define SPR_VTBU (0x10D)
> +#define SPR_TBL (0x10C)
> +#define SPR_TBU (0x10D)
> #define SPR_SPRG0 (0x110)
> #define SPR_SPRG1 (0x111)
> #define SPR_SPRG2 (0x112)
> @@ -1764,8 +1764,8 @@ void ppc_compat_add_property(Object *obj, const char *name,
> #define SPR_SPRG7 (0x117)
> #define SPR_ASR (0x118)
> #define SPR_EAR (0x11A)
> -#define SPR_TBL (0x11C)
> -#define SPR_TBU (0x11D)
> +#define SPR_WR_TBL (0x11C)
> +#define SPR_WR_TBU (0x11D)
> #define SPR_TBU40 (0x11E)
> #define SPR_SVR (0x11E)
> #define SPR_BOOKE_PIR (0x11E)
> diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c
> index 8c00ed8c06..6f190ab13b 100644
> --- a/target/ppc/helper_regs.c
> +++ b/target/ppc/helper_regs.c
> @@ -461,22 +461,22 @@ void register_generic_sprs(PowerPCCPU *cpu)
>
> /* Time base */
> #if defined(TARGET_PPC64)
> - spr_register(env, SPR_VTBL, "TB",
> + spr_register(env, SPR_TBL, "TB",
> #else
> - spr_register(env, SPR_VTBL, "TBL",
> + spr_register(env, SPR_TBL, "TBL",
> #endif
> &spr_read_tbl, SPR_NOACCESS,
> &spr_read_tbl, SPR_NOACCESS,
> 0x00000000);
> - spr_register(env, SPR_TBL, "TBL",
> + spr_register(env, SPR_WR_TBL, "TBL",
> &spr_read_tbl, SPR_NOACCESS,
> &spr_read_tbl, &spr_write_tbl,
> 0x00000000);
> - spr_register(env, SPR_VTBU, "TBU",
> + spr_register(env, SPR_TBU, "TBU",
> &spr_read_tbu, SPR_NOACCESS,
> &spr_read_tbu, SPR_NOACCESS,
> 0x00000000);
> - spr_register(env, SPR_TBU, "TBU",
> + spr_register(env, SPR_WR_TBU, "TBU",
> &spr_read_tbu, SPR_NOACCESS,
> &spr_read_tbu, &spr_write_tbu,
> 0x00000000);