On Sun, 12 Nov 2023 at 16:57, Nikita Ostrenkov <n.ostrenkov@gmail.com> wrote:
>
> According to the technical reference manual Cortex A9 like Cortex A7 and Cortex A15 has Perfomance Unit Monitor (PMU)
> https://developer.arm.com/documentation/100511/0401/performance-monitoring-unit/about-the-performance-monitoring-unit
>
> Signed-off-by: Nikita Ostrenkov <n.ostrenkov@gmail.com>
> ---
> target/arm/tcg/cpu32.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
> index 0d5d8e307d..0008c3f890 100644
> --- a/target/arm/tcg/cpu32.c
> +++ b/target/arm/tcg/cpu32.c
> @@ -418,6 +418,7 @@ static void cortex_a9_initfn(Object *obj)
> set_feature(&cpu->env, ARM_FEATURE_NEON);
> set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
> set_feature(&cpu->env, ARM_FEATURE_EL3);
> + set_feature(&cpu->env, ARM_FEATURE_PMU);
> /*
> * Note that A9 supports the MP extensions even for
> * A9UP and single-core A9MP (which are both different
Thanks for this patch.
There definitely seem to be some weirdnesses in our PMU emulation
for older CPUs like the A9. In particular we define the registers
in v7_cp_reginfo[], so you get them on all v7 cores, even if
ARM_FEATURE_PMU is turned off; they just don't actually do anything.
This seems to affect the cortex-a8 and cortex-a9; everything
newer defines ARM_FEATURE_PMU. We really ought to have the PMU
registers separated out and only defined for ARM_FEATURE_PMU CPUs.
(Annoyingly, we can't drop ARM_FEATURE_PMU and look at ID_DFR0
instead, because the A8 and A9 have a PMU but don't advertise
it in ID_DFR0, because they predate the PMUv2 standardization
of the ID_DFR0 field for that.)
The other thing here is that these CPUs are older versions
of the PMU, so strictly we ought to check whether they
have deviations from the registers we define. But since
we're already defining all those registers anyway, it seems
safe enough to let them actually work.
I've applied this to target-arm.next, with an update to also
set ARM_FEATURE_PMU for the Cortex-A8, since that was the
only other CPU in this odd "PMU registers present but not
really working" state.
thanks
-- PMM