[PULL 00/12] target-arm queue
[PULL 00/19] target-arm queue
1
Hi; here's another arm pullreq. These changes are all bug fixes
1
Hi; this is one last arm pullreq before the end of the year.
2
(including some Coverity issue fixes), so are OK for applying
2
Mostly minor cleanups, and also implementation of the
3
either before or after softfreeze.
3
FEAT_XS architectural feature.
4
4
5
thanks
5
thanks
6
-- PMM
6
-- PMM
7
7
8
The following changes since commit 3e01f1147a16ca566694b97eafc941d62fa1e8d8:
8
The following changes since commit 8032c78e556cd0baec111740a6c636863f9bd7c8:
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9
10
Merge tag 'pull-sp-20231105' of https://gitlab.com/rth7680/qemu into staging (2023-11-06 09:34:22 +0800)
10
Merge tag 'firmware-20241216-pull-request' of https://gitlab.com/kraxel/qemu into staging (2024-12-16 14:20:33 -0500)
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11
12
are available in the Git repository at:
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are available in the Git repository at:
13
13
14
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20231106
14
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20241217
15
15
16
for you to fetch changes up to 5722fc471296d5f042df4b005a851cc8008df0c9:
16
for you to fetch changes up to e91254250acb8570bd7b8a8f89d30e6d18291d02:
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17
18
target/arm: Fix A64 LDRA immediate decode (2023-11-06 15:00:29 +0000)
18
tests/functional: update sbsa-ref firmware used in test (2024-12-17 15:21:06 +0000)
19
19
20
----------------------------------------------------------------
20
----------------------------------------------------------------
21
target-arm queue:
21
target-arm queue:
22
* hw/arm/virt: fix PMU IRQ registration
22
* remove a line of redundant code
23
* hw/arm/virt: Report correct register sizes in ACPI DBG2/SPCR tables
23
* convert various TCG helper fns to use 'fpst' alias
24
* hw/i386/intel_iommu: vtd_slpte_nonzero_rsvd(): assert no overflow
24
* Use float_status in helper_fcvtx_f64_to_f32
25
* util/filemonitor-inotify: qemu_file_monitor_watch(): assert no overflow
25
* Use float_status in helper_vfp_fcvt{ds,sd}
26
* mc146818rtc: rtc_set_time(): initialize tm to zeroes
26
* Implement FEAT_XS
27
* block/nvme: nvme_process_completion() fix bound for cid
27
* hw/intc/arm_gicv3_its: Zero initialize local DTEntry etc structs
28
* hw/core/loader: gunzip(): initialize z_stream
28
* tests/functional: update sbsa-ref firmware used in test
29
* io/channel-socket: qio_channel_socket_flush(): improve msg validation
30
* hw/arm/vexpress-a9: Remove useless mapping of RAM at address 0
31
* target/arm: Fix A64 LDRA immediate decode
32
29
33
----------------------------------------------------------------
30
----------------------------------------------------------------
31
Denis Rastyogin (1):
32
target/arm: remove redundant code
33
34
Manos Pitsidianakis (3):
35
target/arm: Add decodetree entry for DSB nXS variant
36
target/arm: Enable FEAT_XS for the max cpu
37
tests/tcg/aarch64: add system test for FEAT_XS
38
39
Marcin Juszkiewicz (1):
40
tests/functional: update sbsa-ref firmware used in test
41
34
Peter Maydell (4):
42
Peter Maydell (4):
35
tests/qtest/bios-tables-test: Allow changes to virt SPCR and DBG2
43
target/arm: Implement fine-grained-trap handling for FEAT_XS
36
tests/qtest/bios-tables-test: Update virt SPCR and DBG2 golden references
44
target/arm: Add ARM_CP_ADD_TLBI_NXS type flag for NXS insns
37
hw/arm/vexpress-a9: Remove useless mapping of RAM at address 0
45
target/arm: Add ARM_CP_ADD_TLBI_NXS type flag to TLBI insns
38
target/arm: Fix A64 LDRA immediate decode
46
hw/intc/arm_gicv3_its: Zero initialize local DTEntry etc structs
39
47
40
Sebastian Ott (1):
48
Richard Henderson (10):
41
hw/arm/virt: fix PMU IRQ registration
49
target/arm: Convert vfp_helper.c to fpst alias
50
target/arm: Convert helper-a64.c to fpst alias
51
target/arm: Convert vec_helper.c to fpst alias
52
target/arm: Convert neon_helper.c to fpst alias
53
target/arm: Convert sve_helper.c to fpst alias
54
target/arm: Convert sme_helper.c to fpst alias
55
target/arm: Convert vec_helper.c to use env alias
56
target/arm: Convert neon_helper.c to use env alias
57
target/arm: Use float_status in helper_fcvtx_f64_to_f32
58
target/arm: Use float_status in helper_vfp_fcvt{ds,sd}
42
59
43
Udo Steinberg (1):
60
docs/system/arm/emulation.rst | 1 +
44
hw/arm/virt: Report correct register sizes in ACPI DBG2/SPCR tables.
61
target/arm/cpregs.h | 80 ++--
45
62
target/arm/cpu-features.h | 5 +
46
Vladimir Sementsov-Ogievskiy (6):
63
target/arm/helper.h | 638 +++++++++++++++----------------
47
hw/i386/intel_iommu: vtd_slpte_nonzero_rsvd(): assert no overflow
64
target/arm/tcg/helper-a64.h | 116 +++---
48
util/filemonitor-inotify: qemu_file_monitor_watch(): assert no overflow
65
target/arm/tcg/helper-sme.h | 4 +-
49
mc146818rtc: rtc_set_time(): initialize tm to zeroes
66
target/arm/tcg/helper-sve.h | 426 ++++++++++-----------
50
block/nvme: nvme_process_completion() fix bound for cid
67
target/arm/tcg/a64.decode | 3 +
51
hw/core/loader: gunzip(): initialize z_stream
68
hw/intc/arm_gicv3_its.c | 44 +--
52
io/channel-socket: qio_channel_socket_flush(): improve msg validation
69
target/arm/helper.c | 30 +-
53
70
target/arm/tcg/cpu64.c | 1 +
54
docs/system/arm/vexpress.rst | 3 +++
71
target/arm/tcg/helper-a64.c | 101 ++---
55
target/arm/tcg/translate.h | 5 +++++
72
target/arm/tcg/neon_helper.c | 27 +-
56
target/arm/tcg/a64.decode | 2 +-
73
target/arm/tcg/op_helper.c | 11 +-
57
block/nvme.c | 7 ++++---
74
target/arm/tcg/sme_helper.c | 8 +-
58
hw/arm/vexpress.c | 14 +++-----------
75
target/arm/tcg/sve_helper.c | 96 ++---
59
hw/arm/virt-acpi-build.c | 4 ++--
76
target/arm/tcg/tlb-insns.c | 202 ++++++----
60
hw/arm/virt.c | 3 ++-
77
target/arm/tcg/translate-a64.c | 26 +-
61
hw/core/loader.c | 2 +-
78
target/arm/tcg/translate-vfp.c | 4 +-
62
hw/i386/intel_iommu.c | 23 ++++++++++++++++++++---
79
target/arm/tcg/vec_helper.c | 81 ++--
63
hw/rtc/mc146818rtc.c | 2 +-
80
target/arm/vfp_helper.c | 130 +++----
64
io/channel-socket.c | 5 +++++
81
tests/tcg/aarch64/system/feat-xs.c | 27 ++
65
util/filemonitor-inotify.c | 25 +++++++++++++++++--------
82
tests/functional/test_aarch64_sbsaref.py | 20 +-
66
tests/data/acpi/virt/DBG2 | Bin 87 -> 87 bytes
83
23 files changed, 1083 insertions(+), 998 deletions(-)
67
tests/data/acpi/virt/SPCR | Bin 80 -> 80 bytes
84
create mode 100644 tests/tcg/aarch64/system/feat-xs.c
68
14 files changed, 64 insertions(+), 31 deletions(-)
diff view generated by jsdifflib
[PULL 10/12] io/channel-socket: qio_channel_socket_flush(): improve msg validation
[PULL 01/19] target/arm: remove redundant code
1
From: Vladimir Sementsov-Ogievskiy <vsementsov@yandex-team.ru>
1
From: Denis Rastyogin <gerben@altlinux.org>
2
2
3
For SO_EE_ORIGIN_ZEROCOPY the 32-bit notification range is encoded
3
This call is redundant as it only retrieves a value that is not used further.
4
as [ee_info, ee_data] inclusively, so ee_info should be less or
5
equal to ee_data.
6
4
7
Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@yandex-team.ru>
5
Found by Linux Verification Center (linuxtesting.org) with SVACE.
8
Reviewed-by: Maksim Davydov <davydov-max@yandex-team.ru>
6
9
Message-id: 20231017125941.810461-7-vsementsov@yandex-team.ru
7
Signed-off-by: Denis Rastyogin <gerben@altlinux.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20241212120618.518369-1-gerben@altlinux.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
11
---
12
io/channel-socket.c | 5 +++++
12
target/arm/vfp_helper.c | 2 --
13
1 file changed, 5 insertions(+)
13
1 file changed, 2 deletions(-)
14
14
15
diff --git a/io/channel-socket.c b/io/channel-socket.c
15
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
16
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
17
--- a/io/channel-socket.c
17
--- a/target/arm/vfp_helper.c
18
+++ b/io/channel-socket.c
18
+++ b/target/arm/vfp_helper.c
19
@@ -XXX,XX +XXX,XX @@ static int qio_channel_socket_flush(QIOChannel *ioc,
19
@@ -XXX,XX +XXX,XX @@ float64 HELPER(rintd)(float64 x, void *fp_status)
20
"Error not from zero copy");
20
21
return -1;
21
ret = float64_round_to_int(x, fp_status);
22
}
22
23
+ if (serr->ee_data < serr->ee_info) {
23
- new_flags = get_float_exception_flags(fp_status);
24
+ error_setg_errno(errp, serr->ee_origin,
24
-
25
+ "Wrong notification bounds");
25
/* Suppress any inexact exceptions the conversion produced */
26
+ return -1;
26
if (!(old_flags & float_flag_inexact)) {
27
+ }
27
new_flags = get_float_exception_flags(fp_status);
28
29
/* No errors, count successfully finished sendmsg()*/
30
sioc->zero_copy_sent += serr->ee_data - serr->ee_info + 1;
31
--
28
--
32
2.34.1
29
2.34.1
diff view generated by jsdifflib
[PULL 05/12] hw/i386/intel_iommu: vtd_slpte_nonzero_rsvd(): assert no overflow
[PULL 02/19] target/arm: Convert vfp_helper.c to fpst alias
1
From: Vladimir Sementsov-Ogievskiy <vsementsov@yandex-team.ru>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
We support only 3- and 4-level page-tables, which is firstly checked in
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
vtd_decide_config(), then setup in vtd_init(). Than level fields are
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
checked by vtd_is_level_supported().
5
Message-id: 20241206031224.78525-3-richard.henderson@linaro.org
6
7
So here we can't have level out from 1..4 inclusive range. Let's assert
8
it. That also explains Coverity that we are not going to overflow the
9
array.
10
11
CID: 1487158, 1487186
12
Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@yandex-team.ru>
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Maksim Davydov <davydov-max@yandex-team.ru>
15
Message-id: 20231017125941.810461-2-vsementsov@yandex-team.ru
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
7
---
18
hw/i386/intel_iommu.c | 23 ++++++++++++++++++++---
8
target/arm/helper.h | 268 ++++++++++++++++++++--------------------
19
1 file changed, 20 insertions(+), 3 deletions(-)
9
target/arm/vfp_helper.c | 120 ++++++++----------
10
2 files changed, 186 insertions(+), 202 deletions(-)
20
11
21
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
12
diff --git a/target/arm/helper.h b/target/arm/helper.h
22
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
23
--- a/hw/i386/intel_iommu.c
14
--- a/target/arm/helper.h
24
+++ b/hw/i386/intel_iommu.c
15
+++ b/target/arm/helper.h
25
@@ -XXX,XX +XXX,XX @@ static dma_addr_t vtd_get_iova_pgtbl_base(IntelIOMMUState *s,
16
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(probe_access, TCG_CALL_NO_WG, void, env, tl, i32, i32, i32)
26
* Rsvd field masks for spte:
17
DEF_HELPER_1(vfp_get_fpscr, i32, env)
27
* vtd_spte_rsvd 4k pages
18
DEF_HELPER_2(vfp_set_fpscr, void, env, i32)
28
* vtd_spte_rsvd_large large pages
19
29
+ *
20
-DEF_HELPER_3(vfp_addh, f16, f16, f16, ptr)
30
+ * We support only 3-level and 4-level page tables (see vtd_init() which
21
-DEF_HELPER_3(vfp_adds, f32, f32, f32, ptr)
31
+ * sets only VTD_CAP_SAGAW_39bit and maybe VTD_CAP_SAGAW_48bit bits in s->cap).
22
-DEF_HELPER_3(vfp_addd, f64, f64, f64, ptr)
23
-DEF_HELPER_3(vfp_subh, f16, f16, f16, ptr)
24
-DEF_HELPER_3(vfp_subs, f32, f32, f32, ptr)
25
-DEF_HELPER_3(vfp_subd, f64, f64, f64, ptr)
26
-DEF_HELPER_3(vfp_mulh, f16, f16, f16, ptr)
27
-DEF_HELPER_3(vfp_muls, f32, f32, f32, ptr)
28
-DEF_HELPER_3(vfp_muld, f64, f64, f64, ptr)
29
-DEF_HELPER_3(vfp_divh, f16, f16, f16, ptr)
30
-DEF_HELPER_3(vfp_divs, f32, f32, f32, ptr)
31
-DEF_HELPER_3(vfp_divd, f64, f64, f64, ptr)
32
-DEF_HELPER_3(vfp_maxh, f16, f16, f16, ptr)
33
-DEF_HELPER_3(vfp_maxs, f32, f32, f32, ptr)
34
-DEF_HELPER_3(vfp_maxd, f64, f64, f64, ptr)
35
-DEF_HELPER_3(vfp_minh, f16, f16, f16, ptr)
36
-DEF_HELPER_3(vfp_mins, f32, f32, f32, ptr)
37
-DEF_HELPER_3(vfp_mind, f64, f64, f64, ptr)
38
-DEF_HELPER_3(vfp_maxnumh, f16, f16, f16, ptr)
39
-DEF_HELPER_3(vfp_maxnums, f32, f32, f32, ptr)
40
-DEF_HELPER_3(vfp_maxnumd, f64, f64, f64, ptr)
41
-DEF_HELPER_3(vfp_minnumh, f16, f16, f16, ptr)
42
-DEF_HELPER_3(vfp_minnums, f32, f32, f32, ptr)
43
-DEF_HELPER_3(vfp_minnumd, f64, f64, f64, ptr)
44
-DEF_HELPER_2(vfp_sqrth, f16, f16, ptr)
45
-DEF_HELPER_2(vfp_sqrts, f32, f32, ptr)
46
-DEF_HELPER_2(vfp_sqrtd, f64, f64, ptr)
47
+DEF_HELPER_3(vfp_addh, f16, f16, f16, fpst)
48
+DEF_HELPER_3(vfp_adds, f32, f32, f32, fpst)
49
+DEF_HELPER_3(vfp_addd, f64, f64, f64, fpst)
50
+DEF_HELPER_3(vfp_subh, f16, f16, f16, fpst)
51
+DEF_HELPER_3(vfp_subs, f32, f32, f32, fpst)
52
+DEF_HELPER_3(vfp_subd, f64, f64, f64, fpst)
53
+DEF_HELPER_3(vfp_mulh, f16, f16, f16, fpst)
54
+DEF_HELPER_3(vfp_muls, f32, f32, f32, fpst)
55
+DEF_HELPER_3(vfp_muld, f64, f64, f64, fpst)
56
+DEF_HELPER_3(vfp_divh, f16, f16, f16, fpst)
57
+DEF_HELPER_3(vfp_divs, f32, f32, f32, fpst)
58
+DEF_HELPER_3(vfp_divd, f64, f64, f64, fpst)
59
+DEF_HELPER_3(vfp_maxh, f16, f16, f16, fpst)
60
+DEF_HELPER_3(vfp_maxs, f32, f32, f32, fpst)
61
+DEF_HELPER_3(vfp_maxd, f64, f64, f64, fpst)
62
+DEF_HELPER_3(vfp_minh, f16, f16, f16, fpst)
63
+DEF_HELPER_3(vfp_mins, f32, f32, f32, fpst)
64
+DEF_HELPER_3(vfp_mind, f64, f64, f64, fpst)
65
+DEF_HELPER_3(vfp_maxnumh, f16, f16, f16, fpst)
66
+DEF_HELPER_3(vfp_maxnums, f32, f32, f32, fpst)
67
+DEF_HELPER_3(vfp_maxnumd, f64, f64, f64, fpst)
68
+DEF_HELPER_3(vfp_minnumh, f16, f16, f16, fpst)
69
+DEF_HELPER_3(vfp_minnums, f32, f32, f32, fpst)
70
+DEF_HELPER_3(vfp_minnumd, f64, f64, f64, fpst)
71
+DEF_HELPER_2(vfp_sqrth, f16, f16, fpst)
72
+DEF_HELPER_2(vfp_sqrts, f32, f32, fpst)
73
+DEF_HELPER_2(vfp_sqrtd, f64, f64, fpst)
74
DEF_HELPER_3(vfp_cmph, void, f16, f16, env)
75
DEF_HELPER_3(vfp_cmps, void, f32, f32, env)
76
DEF_HELPER_3(vfp_cmpd, void, f64, f64, env)
77
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(vfp_cmped, void, f64, f64, env)
78
79
DEF_HELPER_2(vfp_fcvtds, f64, f32, env)
80
DEF_HELPER_2(vfp_fcvtsd, f32, f64, env)
81
-DEF_HELPER_FLAGS_2(bfcvt, TCG_CALL_NO_RWG, i32, f32, ptr)
82
-DEF_HELPER_FLAGS_2(bfcvt_pair, TCG_CALL_NO_RWG, i32, i64, ptr)
83
+DEF_HELPER_FLAGS_2(bfcvt, TCG_CALL_NO_RWG, i32, f32, fpst)
84
+DEF_HELPER_FLAGS_2(bfcvt_pair, TCG_CALL_NO_RWG, i32, i64, fpst)
85
86
-DEF_HELPER_2(vfp_uitoh, f16, i32, ptr)
87
-DEF_HELPER_2(vfp_uitos, f32, i32, ptr)
88
-DEF_HELPER_2(vfp_uitod, f64, i32, ptr)
89
-DEF_HELPER_2(vfp_sitoh, f16, i32, ptr)
90
-DEF_HELPER_2(vfp_sitos, f32, i32, ptr)
91
-DEF_HELPER_2(vfp_sitod, f64, i32, ptr)
92
+DEF_HELPER_2(vfp_uitoh, f16, i32, fpst)
93
+DEF_HELPER_2(vfp_uitos, f32, i32, fpst)
94
+DEF_HELPER_2(vfp_uitod, f64, i32, fpst)
95
+DEF_HELPER_2(vfp_sitoh, f16, i32, fpst)
96
+DEF_HELPER_2(vfp_sitos, f32, i32, fpst)
97
+DEF_HELPER_2(vfp_sitod, f64, i32, fpst)
98
99
-DEF_HELPER_2(vfp_touih, i32, f16, ptr)
100
-DEF_HELPER_2(vfp_touis, i32, f32, ptr)
101
-DEF_HELPER_2(vfp_touid, i32, f64, ptr)
102
-DEF_HELPER_2(vfp_touizh, i32, f16, ptr)
103
-DEF_HELPER_2(vfp_touizs, i32, f32, ptr)
104
-DEF_HELPER_2(vfp_touizd, i32, f64, ptr)
105
-DEF_HELPER_2(vfp_tosih, s32, f16, ptr)
106
-DEF_HELPER_2(vfp_tosis, s32, f32, ptr)
107
-DEF_HELPER_2(vfp_tosid, s32, f64, ptr)
108
-DEF_HELPER_2(vfp_tosizh, s32, f16, ptr)
109
-DEF_HELPER_2(vfp_tosizs, s32, f32, ptr)
110
-DEF_HELPER_2(vfp_tosizd, s32, f64, ptr)
111
+DEF_HELPER_2(vfp_touih, i32, f16, fpst)
112
+DEF_HELPER_2(vfp_touis, i32, f32, fpst)
113
+DEF_HELPER_2(vfp_touid, i32, f64, fpst)
114
+DEF_HELPER_2(vfp_touizh, i32, f16, fpst)
115
+DEF_HELPER_2(vfp_touizs, i32, f32, fpst)
116
+DEF_HELPER_2(vfp_touizd, i32, f64, fpst)
117
+DEF_HELPER_2(vfp_tosih, s32, f16, fpst)
118
+DEF_HELPER_2(vfp_tosis, s32, f32, fpst)
119
+DEF_HELPER_2(vfp_tosid, s32, f64, fpst)
120
+DEF_HELPER_2(vfp_tosizh, s32, f16, fpst)
121
+DEF_HELPER_2(vfp_tosizs, s32, f32, fpst)
122
+DEF_HELPER_2(vfp_tosizd, s32, f64, fpst)
123
124
-DEF_HELPER_3(vfp_toshh_round_to_zero, i32, f16, i32, ptr)
125
-DEF_HELPER_3(vfp_toslh_round_to_zero, i32, f16, i32, ptr)
126
-DEF_HELPER_3(vfp_touhh_round_to_zero, i32, f16, i32, ptr)
127
-DEF_HELPER_3(vfp_toulh_round_to_zero, i32, f16, i32, ptr)
128
-DEF_HELPER_3(vfp_toshs_round_to_zero, i32, f32, i32, ptr)
129
-DEF_HELPER_3(vfp_tosls_round_to_zero, i32, f32, i32, ptr)
130
-DEF_HELPER_3(vfp_touhs_round_to_zero, i32, f32, i32, ptr)
131
-DEF_HELPER_3(vfp_touls_round_to_zero, i32, f32, i32, ptr)
132
-DEF_HELPER_3(vfp_toshd_round_to_zero, i64, f64, i32, ptr)
133
-DEF_HELPER_3(vfp_tosld_round_to_zero, i64, f64, i32, ptr)
134
-DEF_HELPER_3(vfp_tosqd_round_to_zero, i64, f64, i32, ptr)
135
-DEF_HELPER_3(vfp_touhd_round_to_zero, i64, f64, i32, ptr)
136
-DEF_HELPER_3(vfp_tould_round_to_zero, i64, f64, i32, ptr)
137
-DEF_HELPER_3(vfp_touqd_round_to_zero, i64, f64, i32, ptr)
138
-DEF_HELPER_3(vfp_touhh, i32, f16, i32, ptr)
139
-DEF_HELPER_3(vfp_toshh, i32, f16, i32, ptr)
140
-DEF_HELPER_3(vfp_toulh, i32, f16, i32, ptr)
141
-DEF_HELPER_3(vfp_toslh, i32, f16, i32, ptr)
142
-DEF_HELPER_3(vfp_touqh, i64, f16, i32, ptr)
143
-DEF_HELPER_3(vfp_tosqh, i64, f16, i32, ptr)
144
-DEF_HELPER_3(vfp_toshs, i32, f32, i32, ptr)
145
-DEF_HELPER_3(vfp_tosls, i32, f32, i32, ptr)
146
-DEF_HELPER_3(vfp_tosqs, i64, f32, i32, ptr)
147
-DEF_HELPER_3(vfp_touhs, i32, f32, i32, ptr)
148
-DEF_HELPER_3(vfp_touls, i32, f32, i32, ptr)
149
-DEF_HELPER_3(vfp_touqs, i64, f32, i32, ptr)
150
-DEF_HELPER_3(vfp_toshd, i64, f64, i32, ptr)
151
-DEF_HELPER_3(vfp_tosld, i64, f64, i32, ptr)
152
-DEF_HELPER_3(vfp_tosqd, i64, f64, i32, ptr)
153
-DEF_HELPER_3(vfp_touhd, i64, f64, i32, ptr)
154
-DEF_HELPER_3(vfp_tould, i64, f64, i32, ptr)
155
-DEF_HELPER_3(vfp_touqd, i64, f64, i32, ptr)
156
-DEF_HELPER_3(vfp_shtos, f32, i32, i32, ptr)
157
-DEF_HELPER_3(vfp_sltos, f32, i32, i32, ptr)
158
-DEF_HELPER_3(vfp_sqtos, f32, i64, i32, ptr)
159
-DEF_HELPER_3(vfp_uhtos, f32, i32, i32, ptr)
160
-DEF_HELPER_3(vfp_ultos, f32, i32, i32, ptr)
161
-DEF_HELPER_3(vfp_uqtos, f32, i64, i32, ptr)
162
-DEF_HELPER_3(vfp_shtod, f64, i64, i32, ptr)
163
-DEF_HELPER_3(vfp_sltod, f64, i64, i32, ptr)
164
-DEF_HELPER_3(vfp_sqtod, f64, i64, i32, ptr)
165
-DEF_HELPER_3(vfp_uhtod, f64, i64, i32, ptr)
166
-DEF_HELPER_3(vfp_ultod, f64, i64, i32, ptr)
167
-DEF_HELPER_3(vfp_uqtod, f64, i64, i32, ptr)
168
-DEF_HELPER_3(vfp_shtoh, f16, i32, i32, ptr)
169
-DEF_HELPER_3(vfp_uhtoh, f16, i32, i32, ptr)
170
-DEF_HELPER_3(vfp_sltoh, f16, i32, i32, ptr)
171
-DEF_HELPER_3(vfp_ultoh, f16, i32, i32, ptr)
172
-DEF_HELPER_3(vfp_sqtoh, f16, i64, i32, ptr)
173
-DEF_HELPER_3(vfp_uqtoh, f16, i64, i32, ptr)
174
+DEF_HELPER_3(vfp_toshh_round_to_zero, i32, f16, i32, fpst)
175
+DEF_HELPER_3(vfp_toslh_round_to_zero, i32, f16, i32, fpst)
176
+DEF_HELPER_3(vfp_touhh_round_to_zero, i32, f16, i32, fpst)
177
+DEF_HELPER_3(vfp_toulh_round_to_zero, i32, f16, i32, fpst)
178
+DEF_HELPER_3(vfp_toshs_round_to_zero, i32, f32, i32, fpst)
179
+DEF_HELPER_3(vfp_tosls_round_to_zero, i32, f32, i32, fpst)
180
+DEF_HELPER_3(vfp_touhs_round_to_zero, i32, f32, i32, fpst)
181
+DEF_HELPER_3(vfp_touls_round_to_zero, i32, f32, i32, fpst)
182
+DEF_HELPER_3(vfp_toshd_round_to_zero, i64, f64, i32, fpst)
183
+DEF_HELPER_3(vfp_tosld_round_to_zero, i64, f64, i32, fpst)
184
+DEF_HELPER_3(vfp_tosqd_round_to_zero, i64, f64, i32, fpst)
185
+DEF_HELPER_3(vfp_touhd_round_to_zero, i64, f64, i32, fpst)
186
+DEF_HELPER_3(vfp_tould_round_to_zero, i64, f64, i32, fpst)
187
+DEF_HELPER_3(vfp_touqd_round_to_zero, i64, f64, i32, fpst)
188
+DEF_HELPER_3(vfp_touhh, i32, f16, i32, fpst)
189
+DEF_HELPER_3(vfp_toshh, i32, f16, i32, fpst)
190
+DEF_HELPER_3(vfp_toulh, i32, f16, i32, fpst)
191
+DEF_HELPER_3(vfp_toslh, i32, f16, i32, fpst)
192
+DEF_HELPER_3(vfp_touqh, i64, f16, i32, fpst)
193
+DEF_HELPER_3(vfp_tosqh, i64, f16, i32, fpst)
194
+DEF_HELPER_3(vfp_toshs, i32, f32, i32, fpst)
195
+DEF_HELPER_3(vfp_tosls, i32, f32, i32, fpst)
196
+DEF_HELPER_3(vfp_tosqs, i64, f32, i32, fpst)
197
+DEF_HELPER_3(vfp_touhs, i32, f32, i32, fpst)
198
+DEF_HELPER_3(vfp_touls, i32, f32, i32, fpst)
199
+DEF_HELPER_3(vfp_touqs, i64, f32, i32, fpst)
200
+DEF_HELPER_3(vfp_toshd, i64, f64, i32, fpst)
201
+DEF_HELPER_3(vfp_tosld, i64, f64, i32, fpst)
202
+DEF_HELPER_3(vfp_tosqd, i64, f64, i32, fpst)
203
+DEF_HELPER_3(vfp_touhd, i64, f64, i32, fpst)
204
+DEF_HELPER_3(vfp_tould, i64, f64, i32, fpst)
205
+DEF_HELPER_3(vfp_touqd, i64, f64, i32, fpst)
206
+DEF_HELPER_3(vfp_shtos, f32, i32, i32, fpst)
207
+DEF_HELPER_3(vfp_sltos, f32, i32, i32, fpst)
208
+DEF_HELPER_3(vfp_sqtos, f32, i64, i32, fpst)
209
+DEF_HELPER_3(vfp_uhtos, f32, i32, i32, fpst)
210
+DEF_HELPER_3(vfp_ultos, f32, i32, i32, fpst)
211
+DEF_HELPER_3(vfp_uqtos, f32, i64, i32, fpst)
212
+DEF_HELPER_3(vfp_shtod, f64, i64, i32, fpst)
213
+DEF_HELPER_3(vfp_sltod, f64, i64, i32, fpst)
214
+DEF_HELPER_3(vfp_sqtod, f64, i64, i32, fpst)
215
+DEF_HELPER_3(vfp_uhtod, f64, i64, i32, fpst)
216
+DEF_HELPER_3(vfp_ultod, f64, i64, i32, fpst)
217
+DEF_HELPER_3(vfp_uqtod, f64, i64, i32, fpst)
218
+DEF_HELPER_3(vfp_shtoh, f16, i32, i32, fpst)
219
+DEF_HELPER_3(vfp_uhtoh, f16, i32, i32, fpst)
220
+DEF_HELPER_3(vfp_sltoh, f16, i32, i32, fpst)
221
+DEF_HELPER_3(vfp_ultoh, f16, i32, i32, fpst)
222
+DEF_HELPER_3(vfp_sqtoh, f16, i64, i32, fpst)
223
+DEF_HELPER_3(vfp_uqtoh, f16, i64, i32, fpst)
224
225
-DEF_HELPER_3(vfp_shtos_round_to_nearest, f32, i32, i32, ptr)
226
-DEF_HELPER_3(vfp_sltos_round_to_nearest, f32, i32, i32, ptr)
227
-DEF_HELPER_3(vfp_uhtos_round_to_nearest, f32, i32, i32, ptr)
228
-DEF_HELPER_3(vfp_ultos_round_to_nearest, f32, i32, i32, ptr)
229
-DEF_HELPER_3(vfp_shtod_round_to_nearest, f64, i64, i32, ptr)
230
-DEF_HELPER_3(vfp_sltod_round_to_nearest, f64, i64, i32, ptr)
231
-DEF_HELPER_3(vfp_uhtod_round_to_nearest, f64, i64, i32, ptr)
232
-DEF_HELPER_3(vfp_ultod_round_to_nearest, f64, i64, i32, ptr)
233
-DEF_HELPER_3(vfp_shtoh_round_to_nearest, f16, i32, i32, ptr)
234
-DEF_HELPER_3(vfp_uhtoh_round_to_nearest, f16, i32, i32, ptr)
235
-DEF_HELPER_3(vfp_sltoh_round_to_nearest, f16, i32, i32, ptr)
236
-DEF_HELPER_3(vfp_ultoh_round_to_nearest, f16, i32, i32, ptr)
237
+DEF_HELPER_3(vfp_shtos_round_to_nearest, f32, i32, i32, fpst)
238
+DEF_HELPER_3(vfp_sltos_round_to_nearest, f32, i32, i32, fpst)
239
+DEF_HELPER_3(vfp_uhtos_round_to_nearest, f32, i32, i32, fpst)
240
+DEF_HELPER_3(vfp_ultos_round_to_nearest, f32, i32, i32, fpst)
241
+DEF_HELPER_3(vfp_shtod_round_to_nearest, f64, i64, i32, fpst)
242
+DEF_HELPER_3(vfp_sltod_round_to_nearest, f64, i64, i32, fpst)
243
+DEF_HELPER_3(vfp_uhtod_round_to_nearest, f64, i64, i32, fpst)
244
+DEF_HELPER_3(vfp_ultod_round_to_nearest, f64, i64, i32, fpst)
245
+DEF_HELPER_3(vfp_shtoh_round_to_nearest, f16, i32, i32, fpst)
246
+DEF_HELPER_3(vfp_uhtoh_round_to_nearest, f16, i32, i32, fpst)
247
+DEF_HELPER_3(vfp_sltoh_round_to_nearest, f16, i32, i32, fpst)
248
+DEF_HELPER_3(vfp_ultoh_round_to_nearest, f16, i32, i32, fpst)
249
250
-DEF_HELPER_FLAGS_2(set_rmode, TCG_CALL_NO_RWG, i32, i32, ptr)
251
+DEF_HELPER_FLAGS_2(set_rmode, TCG_CALL_NO_RWG, i32, i32, fpst)
252
253
-DEF_HELPER_FLAGS_3(vfp_fcvt_f16_to_f32, TCG_CALL_NO_RWG, f32, f16, ptr, i32)
254
-DEF_HELPER_FLAGS_3(vfp_fcvt_f32_to_f16, TCG_CALL_NO_RWG, f16, f32, ptr, i32)
255
-DEF_HELPER_FLAGS_3(vfp_fcvt_f16_to_f64, TCG_CALL_NO_RWG, f64, f16, ptr, i32)
256
-DEF_HELPER_FLAGS_3(vfp_fcvt_f64_to_f16, TCG_CALL_NO_RWG, f16, f64, ptr, i32)
257
+DEF_HELPER_FLAGS_3(vfp_fcvt_f16_to_f32, TCG_CALL_NO_RWG, f32, f16, fpst, i32)
258
+DEF_HELPER_FLAGS_3(vfp_fcvt_f32_to_f16, TCG_CALL_NO_RWG, f16, f32, fpst, i32)
259
+DEF_HELPER_FLAGS_3(vfp_fcvt_f16_to_f64, TCG_CALL_NO_RWG, f64, f16, fpst, i32)
260
+DEF_HELPER_FLAGS_3(vfp_fcvt_f64_to_f16, TCG_CALL_NO_RWG, f16, f64, fpst, i32)
261
262
-DEF_HELPER_4(vfp_muladdd, f64, f64, f64, f64, ptr)
263
-DEF_HELPER_4(vfp_muladds, f32, f32, f32, f32, ptr)
264
-DEF_HELPER_4(vfp_muladdh, f16, f16, f16, f16, ptr)
265
+DEF_HELPER_4(vfp_muladdd, f64, f64, f64, f64, fpst)
266
+DEF_HELPER_4(vfp_muladds, f32, f32, f32, f32, fpst)
267
+DEF_HELPER_4(vfp_muladdh, f16, f16, f16, f16, fpst)
268
269
-DEF_HELPER_FLAGS_2(recpe_f16, TCG_CALL_NO_RWG, f16, f16, ptr)
270
-DEF_HELPER_FLAGS_2(recpe_f32, TCG_CALL_NO_RWG, f32, f32, ptr)
271
-DEF_HELPER_FLAGS_2(recpe_f64, TCG_CALL_NO_RWG, f64, f64, ptr)
272
-DEF_HELPER_FLAGS_2(rsqrte_f16, TCG_CALL_NO_RWG, f16, f16, ptr)
273
-DEF_HELPER_FLAGS_2(rsqrte_f32, TCG_CALL_NO_RWG, f32, f32, ptr)
274
-DEF_HELPER_FLAGS_2(rsqrte_f64, TCG_CALL_NO_RWG, f64, f64, ptr)
275
+DEF_HELPER_FLAGS_2(recpe_f16, TCG_CALL_NO_RWG, f16, f16, fpst)
276
+DEF_HELPER_FLAGS_2(recpe_f32, TCG_CALL_NO_RWG, f32, f32, fpst)
277
+DEF_HELPER_FLAGS_2(recpe_f64, TCG_CALL_NO_RWG, f64, f64, fpst)
278
+DEF_HELPER_FLAGS_2(rsqrte_f16, TCG_CALL_NO_RWG, f16, f16, fpst)
279
+DEF_HELPER_FLAGS_2(rsqrte_f32, TCG_CALL_NO_RWG, f32, f32, fpst)
280
+DEF_HELPER_FLAGS_2(rsqrte_f64, TCG_CALL_NO_RWG, f64, f64, fpst)
281
DEF_HELPER_FLAGS_1(recpe_u32, TCG_CALL_NO_RWG, i32, i32)
282
DEF_HELPER_FLAGS_1(rsqrte_u32, TCG_CALL_NO_RWG, i32, i32)
283
DEF_HELPER_FLAGS_4(neon_tbl, TCG_CALL_NO_RWG, i64, env, i32, i64, i64)
284
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(shr_cc, i32, env, i32, i32)
285
DEF_HELPER_3(sar_cc, i32, env, i32, i32)
286
DEF_HELPER_3(ror_cc, i32, env, i32, i32)
287
288
-DEF_HELPER_FLAGS_2(rinth_exact, TCG_CALL_NO_RWG, f16, f16, ptr)
289
-DEF_HELPER_FLAGS_2(rints_exact, TCG_CALL_NO_RWG, f32, f32, ptr)
290
-DEF_HELPER_FLAGS_2(rintd_exact, TCG_CALL_NO_RWG, f64, f64, ptr)
291
-DEF_HELPER_FLAGS_2(rinth, TCG_CALL_NO_RWG, f16, f16, ptr)
292
-DEF_HELPER_FLAGS_2(rints, TCG_CALL_NO_RWG, f32, f32, ptr)
293
-DEF_HELPER_FLAGS_2(rintd, TCG_CALL_NO_RWG, f64, f64, ptr)
294
+DEF_HELPER_FLAGS_2(rinth_exact, TCG_CALL_NO_RWG, f16, f16, fpst)
295
+DEF_HELPER_FLAGS_2(rints_exact, TCG_CALL_NO_RWG, f32, f32, fpst)
296
+DEF_HELPER_FLAGS_2(rintd_exact, TCG_CALL_NO_RWG, f64, f64, fpst)
297
+DEF_HELPER_FLAGS_2(rinth, TCG_CALL_NO_RWG, f16, f16, fpst)
298
+DEF_HELPER_FLAGS_2(rints, TCG_CALL_NO_RWG, f32, f32, fpst)
299
+DEF_HELPER_FLAGS_2(rintd, TCG_CALL_NO_RWG, f64, f64, fpst)
300
301
DEF_HELPER_FLAGS_2(vjcvt, TCG_CALL_NO_RWG, i32, f64, env)
302
-DEF_HELPER_FLAGS_2(fjcvtzs, TCG_CALL_NO_RWG, i64, f64, ptr)
303
+DEF_HELPER_FLAGS_2(fjcvtzs, TCG_CALL_NO_RWG, i64, f64, fpst)
304
305
DEF_HELPER_FLAGS_3(check_hcr_el2_trap, TCG_CALL_NO_WG, void, env, i32, i32)
306
307
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(gvec_fmlal_idx_a32, TCG_CALL_NO_RWG,
308
DEF_HELPER_FLAGS_5(gvec_fmlal_idx_a64, TCG_CALL_NO_RWG,
309
void, ptr, ptr, ptr, ptr, i32)
310
311
-DEF_HELPER_FLAGS_2(frint32_s, TCG_CALL_NO_RWG, f32, f32, ptr)
312
-DEF_HELPER_FLAGS_2(frint64_s, TCG_CALL_NO_RWG, f32, f32, ptr)
313
-DEF_HELPER_FLAGS_2(frint32_d, TCG_CALL_NO_RWG, f64, f64, ptr)
314
-DEF_HELPER_FLAGS_2(frint64_d, TCG_CALL_NO_RWG, f64, f64, ptr)
315
+DEF_HELPER_FLAGS_2(frint32_s, TCG_CALL_NO_RWG, f32, f32, fpst)
316
+DEF_HELPER_FLAGS_2(frint64_s, TCG_CALL_NO_RWG, f32, f32, fpst)
317
+DEF_HELPER_FLAGS_2(frint32_d, TCG_CALL_NO_RWG, f64, f64, fpst)
318
+DEF_HELPER_FLAGS_2(frint64_d, TCG_CALL_NO_RWG, f64, f64, fpst)
319
320
DEF_HELPER_FLAGS_3(gvec_ceq0_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
321
DEF_HELPER_FLAGS_3(gvec_ceq0_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
322
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
323
index XXXXXXX..XXXXXXX 100644
324
--- a/target/arm/vfp_helper.c
325
+++ b/target/arm/vfp_helper.c
326
@@ -XXX,XX +XXX,XX @@ void vfp_set_fpscr(CPUARMState *env, uint32_t val)
327
#define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
328
329
#define VFP_BINOP(name) \
330
-dh_ctype_f16 VFP_HELPER(name, h)(dh_ctype_f16 a, dh_ctype_f16 b, void *fpstp) \
331
+dh_ctype_f16 VFP_HELPER(name, h)(dh_ctype_f16 a, dh_ctype_f16 b, float_status *fpst) \
332
{ \
333
- float_status *fpst = fpstp; \
334
return float16_ ## name(a, b, fpst); \
335
} \
336
-float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
337
+float32 VFP_HELPER(name, s)(float32 a, float32 b, float_status *fpst) \
338
{ \
339
- float_status *fpst = fpstp; \
340
return float32_ ## name(a, b, fpst); \
341
} \
342
-float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
343
+float64 VFP_HELPER(name, d)(float64 a, float64 b, float_status *fpst) \
344
{ \
345
- float_status *fpst = fpstp; \
346
return float64_ ## name(a, b, fpst); \
347
}
348
VFP_BINOP(add)
349
@@ -XXX,XX +XXX,XX @@ VFP_BINOP(minnum)
350
VFP_BINOP(maxnum)
351
#undef VFP_BINOP
352
353
-dh_ctype_f16 VFP_HELPER(sqrt, h)(dh_ctype_f16 a, void *fpstp)
354
+dh_ctype_f16 VFP_HELPER(sqrt, h)(dh_ctype_f16 a, float_status *fpst)
355
{
356
- return float16_sqrt(a, fpstp);
357
+ return float16_sqrt(a, fpst);
358
}
359
360
-float32 VFP_HELPER(sqrt, s)(float32 a, void *fpstp)
361
+float32 VFP_HELPER(sqrt, s)(float32 a, float_status *fpst)
362
{
363
- return float32_sqrt(a, fpstp);
364
+ return float32_sqrt(a, fpst);
365
}
366
367
-float64 VFP_HELPER(sqrt, d)(float64 a, void *fpstp)
368
+float64 VFP_HELPER(sqrt, d)(float64 a, float_status *fpst)
369
{
370
- return float64_sqrt(a, fpstp);
371
+ return float64_sqrt(a, fpst);
372
}
373
374
static void softfloat_to_vfp_compare(CPUARMState *env, FloatRelation cmp)
375
@@ -XXX,XX +XXX,XX @@ DO_VFP_cmp(d, float64, float64, fp_status)
376
/* Integer to float and float to integer conversions */
377
378
#define CONV_ITOF(name, ftype, fsz, sign) \
379
-ftype HELPER(name)(uint32_t x, void *fpstp) \
380
+ftype HELPER(name)(uint32_t x, float_status *fpst) \
381
{ \
382
- float_status *fpst = fpstp; \
383
return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
384
}
385
386
#define CONV_FTOI(name, ftype, fsz, sign, round) \
387
-sign##int32_t HELPER(name)(ftype x, void *fpstp) \
388
+sign##int32_t HELPER(name)(ftype x, float_status *fpst) \
389
{ \
390
- float_status *fpst = fpstp; \
391
if (float##fsz##_is_any_nan(x)) { \
392
float_raise(float_flag_invalid, fpst); \
393
return 0; \
394
@@ -XXX,XX +XXX,XX @@ float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
395
return float64_to_float32(x, &env->vfp.fp_status);
396
}
397
398
-uint32_t HELPER(bfcvt)(float32 x, void *status)
399
+uint32_t HELPER(bfcvt)(float32 x, float_status *status)
400
{
401
return float32_to_bfloat16(x, status);
402
}
403
404
-uint32_t HELPER(bfcvt_pair)(uint64_t pair, void *status)
405
+uint32_t HELPER(bfcvt_pair)(uint64_t pair, float_status *status)
406
{
407
bfloat16 lo = float32_to_bfloat16(extract64(pair, 0, 32), status);
408
bfloat16 hi = float32_to_bfloat16(extract64(pair, 32, 32), status);
409
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(bfcvt_pair)(uint64_t pair, void *status)
32
*/
410
*/
33
-static uint64_t vtd_spte_rsvd[5];
411
#define VFP_CONV_FIX_FLOAT(name, p, fsz, ftype, isz, itype) \
34
-static uint64_t vtd_spte_rsvd_large[5];
412
ftype HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \
35
+#define VTD_SPTE_RSVD_LEN 5
413
- void *fpstp) \
36
+static uint64_t vtd_spte_rsvd[VTD_SPTE_RSVD_LEN];
414
-{ return itype##_to_##float##fsz##_scalbn(x, -shift, fpstp); }
37
+static uint64_t vtd_spte_rsvd_large[VTD_SPTE_RSVD_LEN];
415
+ float_status *fpst) \
38
416
+{ return itype##_to_##float##fsz##_scalbn(x, -shift, fpst); }
39
static bool vtd_slpte_nonzero_rsvd(uint64_t slpte, uint32_t level)
417
40
{
418
#define VFP_CONV_FIX_FLOAT_ROUND(name, p, fsz, ftype, isz, itype) \
41
- uint64_t rsvd_mask = vtd_spte_rsvd[level];
419
ftype HELPER(vfp_##name##to##p##_round_to_nearest)(uint##isz##_t x, \
42
+ uint64_t rsvd_mask;
420
uint32_t shift, \
43
+
421
- void *fpstp) \
44
+ /*
422
+ float_status *fpst) \
45
+ * We should have caught a guest-mis-programmed level earlier,
423
{ \
46
+ * via vtd_is_level_supported.
424
ftype ret; \
47
+ */
425
- float_status *fpst = fpstp; \
48
+ assert(level < VTD_SPTE_RSVD_LEN);
426
FloatRoundMode oldmode = fpst->float_rounding_mode; \
49
+ /*
427
fpst->float_rounding_mode = float_round_nearest_even; \
50
+ * Zero level doesn't exist. The smallest level is VTD_SL_PT_LEVEL=1 and
428
- ret = itype##_to_##float##fsz##_scalbn(x, -shift, fpstp); \
51
+ * checked by vtd_is_last_slpte().
429
+ ret = itype##_to_##float##fsz##_scalbn(x, -shift, fpst); \
52
+ */
430
fpst->float_rounding_mode = oldmode; \
53
+ assert(level);
431
return ret; \
54
55
if ((level == VTD_SL_PD_LEVEL || level == VTD_SL_PDP_LEVEL) &&
56
(slpte & VTD_SL_PT_PAGE_SIZE_MASK)) {
57
/* large page */
58
rsvd_mask = vtd_spte_rsvd_large[level];
59
+ } else {
60
+ rsvd_mask = vtd_spte_rsvd[level];
61
}
432
}
62
433
63
return slpte & rsvd_mask;
434
#define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, ftype, isz, itype, ROUND, suff) \
435
uint##isz##_t HELPER(vfp_to##name##p##suff)(ftype x, uint32_t shift, \
436
- void *fpst) \
437
+ float_status *fpst) \
438
{ \
439
if (unlikely(float##fsz##_is_any_nan(x))) { \
440
float_raise(float_flag_invalid, fpst); \
441
@@ -XXX,XX +XXX,XX @@ VFP_CONV_FLOAT_FIX_ROUND(uq, d, 64, float64, 64, uint64,
442
/* Set the current fp rounding mode and return the old one.
443
* The argument is a softfloat float_round_ value.
444
*/
445
-uint32_t HELPER(set_rmode)(uint32_t rmode, void *fpstp)
446
+uint32_t HELPER(set_rmode)(uint32_t rmode, float_status *fp_status)
447
{
448
- float_status *fp_status = fpstp;
449
-
450
uint32_t prev_rmode = get_float_rounding_mode(fp_status);
451
set_float_rounding_mode(rmode, fp_status);
452
453
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(set_rmode)(uint32_t rmode, void *fpstp)
454
}
455
456
/* Half precision conversions. */
457
-float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, void *fpstp, uint32_t ahp_mode)
458
+float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, float_status *fpst,
459
+ uint32_t ahp_mode)
460
{
461
/* Squash FZ16 to 0 for the duration of conversion. In this case,
462
* it would affect flushing input denormals.
463
*/
464
- float_status *fpst = fpstp;
465
bool save = get_flush_inputs_to_zero(fpst);
466
set_flush_inputs_to_zero(false, fpst);
467
float32 r = float16_to_float32(a, !ahp_mode, fpst);
468
@@ -XXX,XX +XXX,XX @@ float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, void *fpstp, uint32_t ahp_mode)
469
return r;
470
}
471
472
-uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode)
473
+uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, float_status *fpst,
474
+ uint32_t ahp_mode)
475
{
476
/* Squash FZ16 to 0 for the duration of conversion. In this case,
477
* it would affect flushing output denormals.
478
*/
479
- float_status *fpst = fpstp;
480
bool save = get_flush_to_zero(fpst);
481
set_flush_to_zero(false, fpst);
482
float16 r = float32_to_float16(a, !ahp_mode, fpst);
483
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode)
484
return r;
485
}
486
487
-float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, void *fpstp, uint32_t ahp_mode)
488
+float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, float_status *fpst,
489
+ uint32_t ahp_mode)
490
{
491
/* Squash FZ16 to 0 for the duration of conversion. In this case,
492
* it would affect flushing input denormals.
493
*/
494
- float_status *fpst = fpstp;
495
bool save = get_flush_inputs_to_zero(fpst);
496
set_flush_inputs_to_zero(false, fpst);
497
float64 r = float16_to_float64(a, !ahp_mode, fpst);
498
@@ -XXX,XX +XXX,XX @@ float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, void *fpstp, uint32_t ahp_mode)
499
return r;
500
}
501
502
-uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, void *fpstp, uint32_t ahp_mode)
503
+uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, float_status *fpst,
504
+ uint32_t ahp_mode)
505
{
506
/* Squash FZ16 to 0 for the duration of conversion. In this case,
507
* it would affect flushing output denormals.
508
*/
509
- float_status *fpst = fpstp;
510
bool save = get_flush_to_zero(fpst);
511
set_flush_to_zero(false, fpst);
512
float16 r = float64_to_float16(a, !ahp_mode, fpst);
513
@@ -XXX,XX +XXX,XX @@ static bool round_to_inf(float_status *fpst, bool sign_bit)
514
}
515
}
516
517
-uint32_t HELPER(recpe_f16)(uint32_t input, void *fpstp)
518
+uint32_t HELPER(recpe_f16)(uint32_t input, float_status *fpst)
519
{
520
- float_status *fpst = fpstp;
521
float16 f16 = float16_squash_input_denormal(input, fpst);
522
uint32_t f16_val = float16_val(f16);
523
uint32_t f16_sign = float16_is_neg(f16);
524
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(recpe_f16)(uint32_t input, void *fpstp)
525
return make_float16(f16_val);
526
}
527
528
-float32 HELPER(recpe_f32)(float32 input, void *fpstp)
529
+float32 HELPER(recpe_f32)(float32 input, float_status *fpst)
530
{
531
- float_status *fpst = fpstp;
532
float32 f32 = float32_squash_input_denormal(input, fpst);
533
uint32_t f32_val = float32_val(f32);
534
bool f32_sign = float32_is_neg(f32);
535
@@ -XXX,XX +XXX,XX @@ float32 HELPER(recpe_f32)(float32 input, void *fpstp)
536
return make_float32(f32_val);
537
}
538
539
-float64 HELPER(recpe_f64)(float64 input, void *fpstp)
540
+float64 HELPER(recpe_f64)(float64 input, float_status *fpst)
541
{
542
- float_status *fpst = fpstp;
543
float64 f64 = float64_squash_input_denormal(input, fpst);
544
uint64_t f64_val = float64_val(f64);
545
bool f64_sign = float64_is_neg(f64);
546
@@ -XXX,XX +XXX,XX @@ static uint64_t recip_sqrt_estimate(int *exp , int exp_off, uint64_t frac)
547
return extract64(estimate, 0, 8) << 44;
548
}
549
550
-uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp)
551
+uint32_t HELPER(rsqrte_f16)(uint32_t input, float_status *s)
552
{
553
- float_status *s = fpstp;
554
float16 f16 = float16_squash_input_denormal(input, s);
555
uint16_t val = float16_val(f16);
556
bool f16_sign = float16_is_neg(f16);
557
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp)
558
if (float16_is_signaling_nan(f16, s)) {
559
float_raise(float_flag_invalid, s);
560
if (!s->default_nan_mode) {
561
- nan = float16_silence_nan(f16, fpstp);
562
+ nan = float16_silence_nan(f16, s);
563
}
564
}
565
if (s->default_nan_mode) {
566
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp)
567
return make_float16(val);
568
}
569
570
-float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
571
+float32 HELPER(rsqrte_f32)(float32 input, float_status *s)
572
{
573
- float_status *s = fpstp;
574
float32 f32 = float32_squash_input_denormal(input, s);
575
uint32_t val = float32_val(f32);
576
uint32_t f32_sign = float32_is_neg(f32);
577
@@ -XXX,XX +XXX,XX @@ float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
578
if (float32_is_signaling_nan(f32, s)) {
579
float_raise(float_flag_invalid, s);
580
if (!s->default_nan_mode) {
581
- nan = float32_silence_nan(f32, fpstp);
582
+ nan = float32_silence_nan(f32, s);
583
}
584
}
585
if (s->default_nan_mode) {
586
@@ -XXX,XX +XXX,XX @@ float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
587
return make_float32(val);
588
}
589
590
-float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
591
+float64 HELPER(rsqrte_f64)(float64 input, float_status *s)
592
{
593
- float_status *s = fpstp;
594
float64 f64 = float64_squash_input_denormal(input, s);
595
uint64_t val = float64_val(f64);
596
bool f64_sign = float64_is_neg(f64);
597
@@ -XXX,XX +XXX,XX @@ float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
598
if (float64_is_signaling_nan(f64, s)) {
599
float_raise(float_flag_invalid, s);
600
if (!s->default_nan_mode) {
601
- nan = float64_silence_nan(f64, fpstp);
602
+ nan = float64_silence_nan(f64, s);
603
}
604
}
605
if (s->default_nan_mode) {
606
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(rsqrte_u32)(uint32_t a)
607
608
/* VFPv4 fused multiply-accumulate */
609
dh_ctype_f16 VFP_HELPER(muladd, h)(dh_ctype_f16 a, dh_ctype_f16 b,
610
- dh_ctype_f16 c, void *fpstp)
611
+ dh_ctype_f16 c, float_status *fpst)
612
{
613
- float_status *fpst = fpstp;
614
return float16_muladd(a, b, c, 0, fpst);
615
}
616
617
-float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp)
618
+float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c,
619
+ float_status *fpst)
620
{
621
- float_status *fpst = fpstp;
622
return float32_muladd(a, b, c, 0, fpst);
623
}
624
625
-float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
626
+float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c,
627
+ float_status *fpst)
628
{
629
- float_status *fpst = fpstp;
630
return float64_muladd(a, b, c, 0, fpst);
631
}
632
633
/* ARMv8 round to integral */
634
-dh_ctype_f16 HELPER(rinth_exact)(dh_ctype_f16 x, void *fp_status)
635
+dh_ctype_f16 HELPER(rinth_exact)(dh_ctype_f16 x, float_status *fp_status)
636
{
637
return float16_round_to_int(x, fp_status);
638
}
639
640
-float32 HELPER(rints_exact)(float32 x, void *fp_status)
641
+float32 HELPER(rints_exact)(float32 x, float_status *fp_status)
642
{
643
return float32_round_to_int(x, fp_status);
644
}
645
646
-float64 HELPER(rintd_exact)(float64 x, void *fp_status)
647
+float64 HELPER(rintd_exact)(float64 x, float_status *fp_status)
648
{
649
return float64_round_to_int(x, fp_status);
650
}
651
652
-dh_ctype_f16 HELPER(rinth)(dh_ctype_f16 x, void *fp_status)
653
+dh_ctype_f16 HELPER(rinth)(dh_ctype_f16 x, float_status *fp_status)
654
{
655
int old_flags = get_float_exception_flags(fp_status), new_flags;
656
float16 ret;
657
@@ -XXX,XX +XXX,XX @@ dh_ctype_f16 HELPER(rinth)(dh_ctype_f16 x, void *fp_status)
658
return ret;
659
}
660
661
-float32 HELPER(rints)(float32 x, void *fp_status)
662
+float32 HELPER(rints)(float32 x, float_status *fp_status)
663
{
664
int old_flags = get_float_exception_flags(fp_status), new_flags;
665
float32 ret;
666
@@ -XXX,XX +XXX,XX @@ float32 HELPER(rints)(float32 x, void *fp_status)
667
return ret;
668
}
669
670
-float64 HELPER(rintd)(float64 x, void *fp_status)
671
+float64 HELPER(rintd)(float64 x, float_status *fp_status)
672
{
673
int old_flags = get_float_exception_flags(fp_status), new_flags;
674
float64 ret;
675
@@ -XXX,XX +XXX,XX @@ const FloatRoundMode arm_rmode_to_sf_map[] = {
676
* Implement float64 to int32_t conversion without saturation;
677
* the result is supplied modulo 2^32.
678
*/
679
-uint64_t HELPER(fjcvtzs)(float64 value, void *vstatus)
680
+uint64_t HELPER(fjcvtzs)(float64 value, float_status *status)
681
{
682
- float_status *status = vstatus;
683
uint32_t frac, e_old, e_new;
684
bool inexact;
685
686
@@ -XXX,XX +XXX,XX @@ static float32 frint_s(float32 f, float_status *fpst, int intsize)
687
return (0x100u + 126u + intsize) << 23;
688
}
689
690
-float32 HELPER(frint32_s)(float32 f, void *fpst)
691
+float32 HELPER(frint32_s)(float32 f, float_status *fpst)
692
{
693
return frint_s(f, fpst, 32);
694
}
695
696
-float32 HELPER(frint64_s)(float32 f, void *fpst)
697
+float32 HELPER(frint64_s)(float32 f, float_status *fpst)
698
{
699
return frint_s(f, fpst, 64);
700
}
701
@@ -XXX,XX +XXX,XX @@ static float64 frint_d(float64 f, float_status *fpst, int intsize)
702
return (uint64_t)(0x800 + 1022 + intsize) << 52;
703
}
704
705
-float64 HELPER(frint32_d)(float64 f, void *fpst)
706
+float64 HELPER(frint32_d)(float64 f, float_status *fpst)
707
{
708
return frint_d(f, fpst, 32);
709
}
710
711
-float64 HELPER(frint64_d)(float64 f, void *fpst)
712
+float64 HELPER(frint64_d)(float64 f, float_status *fpst)
713
{
714
return frint_d(f, fpst, 64);
715
}
64
--
716
--
65
2.34.1
717
2.34.1
718
719
diff view generated by jsdifflib
New patch
[PULL 03/19] target/arm: Convert helper-a64.c to fpst alias
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
Message-id: 20241206031224.78525-4-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/tcg/helper-a64.h | 94 +++++++++++++++++------------------
9
target/arm/tcg/helper-a64.c | 98 +++++++++++++------------------------
10
2 files changed, 80 insertions(+), 112 deletions(-)
11
12
diff --git a/target/arm/tcg/helper-a64.h b/target/arm/tcg/helper-a64.h
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/tcg/helper-a64.h
15
+++ b/target/arm/tcg/helper-a64.h
16
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_2(msr_i_spsel, void, env, i32)
17
DEF_HELPER_2(msr_i_daifset, void, env, i32)
18
DEF_HELPER_2(msr_i_daifclear, void, env, i32)
19
DEF_HELPER_1(msr_set_allint_el1, void, env)
20
-DEF_HELPER_3(vfp_cmph_a64, i64, f16, f16, ptr)
21
-DEF_HELPER_3(vfp_cmpeh_a64, i64, f16, f16, ptr)
22
-DEF_HELPER_3(vfp_cmps_a64, i64, f32, f32, ptr)
23
-DEF_HELPER_3(vfp_cmpes_a64, i64, f32, f32, ptr)
24
-DEF_HELPER_3(vfp_cmpd_a64, i64, f64, f64, ptr)
25
-DEF_HELPER_3(vfp_cmped_a64, i64, f64, f64, ptr)
26
+DEF_HELPER_3(vfp_cmph_a64, i64, f16, f16, fpst)
27
+DEF_HELPER_3(vfp_cmpeh_a64, i64, f16, f16, fpst)
28
+DEF_HELPER_3(vfp_cmps_a64, i64, f32, f32, fpst)
29
+DEF_HELPER_3(vfp_cmpes_a64, i64, f32, f32, fpst)
30
+DEF_HELPER_3(vfp_cmpd_a64, i64, f64, f64, fpst)
31
+DEF_HELPER_3(vfp_cmped_a64, i64, f64, f64, fpst)
32
DEF_HELPER_FLAGS_4(simd_tblx, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
33
-DEF_HELPER_FLAGS_3(vfp_mulxs, TCG_CALL_NO_RWG, f32, f32, f32, ptr)
34
-DEF_HELPER_FLAGS_3(vfp_mulxd, TCG_CALL_NO_RWG, f64, f64, f64, ptr)
35
-DEF_HELPER_FLAGS_3(neon_ceq_f64, TCG_CALL_NO_RWG, i64, i64, i64, ptr)
36
-DEF_HELPER_FLAGS_3(neon_cge_f64, TCG_CALL_NO_RWG, i64, i64, i64, ptr)
37
-DEF_HELPER_FLAGS_3(neon_cgt_f64, TCG_CALL_NO_RWG, i64, i64, i64, ptr)
38
-DEF_HELPER_FLAGS_3(recpsf_f16, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
39
-DEF_HELPER_FLAGS_3(recpsf_f32, TCG_CALL_NO_RWG, f32, f32, f32, ptr)
40
-DEF_HELPER_FLAGS_3(recpsf_f64, TCG_CALL_NO_RWG, f64, f64, f64, ptr)
41
-DEF_HELPER_FLAGS_3(rsqrtsf_f16, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
42
-DEF_HELPER_FLAGS_3(rsqrtsf_f32, TCG_CALL_NO_RWG, f32, f32, f32, ptr)
43
-DEF_HELPER_FLAGS_3(rsqrtsf_f64, TCG_CALL_NO_RWG, f64, f64, f64, ptr)
44
-DEF_HELPER_FLAGS_2(frecpx_f64, TCG_CALL_NO_RWG, f64, f64, ptr)
45
-DEF_HELPER_FLAGS_2(frecpx_f32, TCG_CALL_NO_RWG, f32, f32, ptr)
46
-DEF_HELPER_FLAGS_2(frecpx_f16, TCG_CALL_NO_RWG, f16, f16, ptr)
47
+DEF_HELPER_FLAGS_3(vfp_mulxs, TCG_CALL_NO_RWG, f32, f32, f32, fpst)
48
+DEF_HELPER_FLAGS_3(vfp_mulxd, TCG_CALL_NO_RWG, f64, f64, f64, fpst)
49
+DEF_HELPER_FLAGS_3(neon_ceq_f64, TCG_CALL_NO_RWG, i64, i64, i64, fpst)
50
+DEF_HELPER_FLAGS_3(neon_cge_f64, TCG_CALL_NO_RWG, i64, i64, i64, fpst)
51
+DEF_HELPER_FLAGS_3(neon_cgt_f64, TCG_CALL_NO_RWG, i64, i64, i64, fpst)
52
+DEF_HELPER_FLAGS_3(recpsf_f16, TCG_CALL_NO_RWG, f16, f16, f16, fpst)
53
+DEF_HELPER_FLAGS_3(recpsf_f32, TCG_CALL_NO_RWG, f32, f32, f32, fpst)
54
+DEF_HELPER_FLAGS_3(recpsf_f64, TCG_CALL_NO_RWG, f64, f64, f64, fpst)
55
+DEF_HELPER_FLAGS_3(rsqrtsf_f16, TCG_CALL_NO_RWG, f16, f16, f16, fpst)
56
+DEF_HELPER_FLAGS_3(rsqrtsf_f32, TCG_CALL_NO_RWG, f32, f32, f32, fpst)
57
+DEF_HELPER_FLAGS_3(rsqrtsf_f64, TCG_CALL_NO_RWG, f64, f64, f64, fpst)
58
+DEF_HELPER_FLAGS_2(frecpx_f64, TCG_CALL_NO_RWG, f64, f64, fpst)
59
+DEF_HELPER_FLAGS_2(frecpx_f32, TCG_CALL_NO_RWG, f32, f32, fpst)
60
+DEF_HELPER_FLAGS_2(frecpx_f16, TCG_CALL_NO_RWG, f16, f16, fpst)
61
DEF_HELPER_FLAGS_2(fcvtx_f64_to_f32, TCG_CALL_NO_RWG, f32, f64, env)
62
DEF_HELPER_FLAGS_3(crc32_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32)
63
DEF_HELPER_FLAGS_3(crc32c_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32)
64
-DEF_HELPER_FLAGS_3(advsimd_maxh, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
65
-DEF_HELPER_FLAGS_3(advsimd_minh, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
66
-DEF_HELPER_FLAGS_3(advsimd_maxnumh, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
67
-DEF_HELPER_FLAGS_3(advsimd_minnumh, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
68
-DEF_HELPER_3(advsimd_addh, f16, f16, f16, ptr)
69
-DEF_HELPER_3(advsimd_subh, f16, f16, f16, ptr)
70
-DEF_HELPER_3(advsimd_mulh, f16, f16, f16, ptr)
71
-DEF_HELPER_3(advsimd_divh, f16, f16, f16, ptr)
72
-DEF_HELPER_3(advsimd_ceq_f16, i32, f16, f16, ptr)
73
-DEF_HELPER_3(advsimd_cge_f16, i32, f16, f16, ptr)
74
-DEF_HELPER_3(advsimd_cgt_f16, i32, f16, f16, ptr)
75
-DEF_HELPER_3(advsimd_acge_f16, i32, f16, f16, ptr)
76
-DEF_HELPER_3(advsimd_acgt_f16, i32, f16, f16, ptr)
77
-DEF_HELPER_3(advsimd_mulxh, f16, f16, f16, ptr)
78
-DEF_HELPER_4(advsimd_muladdh, f16, f16, f16, f16, ptr)
79
-DEF_HELPER_3(advsimd_add2h, i32, i32, i32, ptr)
80
-DEF_HELPER_3(advsimd_sub2h, i32, i32, i32, ptr)
81
-DEF_HELPER_3(advsimd_mul2h, i32, i32, i32, ptr)
82
-DEF_HELPER_3(advsimd_div2h, i32, i32, i32, ptr)
83
-DEF_HELPER_3(advsimd_max2h, i32, i32, i32, ptr)
84
-DEF_HELPER_3(advsimd_min2h, i32, i32, i32, ptr)
85
-DEF_HELPER_3(advsimd_maxnum2h, i32, i32, i32, ptr)
86
-DEF_HELPER_3(advsimd_minnum2h, i32, i32, i32, ptr)
87
-DEF_HELPER_3(advsimd_mulx2h, i32, i32, i32, ptr)
88
-DEF_HELPER_4(advsimd_muladd2h, i32, i32, i32, i32, ptr)
89
-DEF_HELPER_2(advsimd_rinth_exact, f16, f16, ptr)
90
-DEF_HELPER_2(advsimd_rinth, f16, f16, ptr)
91
+DEF_HELPER_FLAGS_3(advsimd_maxh, TCG_CALL_NO_RWG, f16, f16, f16, fpst)
92
+DEF_HELPER_FLAGS_3(advsimd_minh, TCG_CALL_NO_RWG, f16, f16, f16, fpst)
93
+DEF_HELPER_FLAGS_3(advsimd_maxnumh, TCG_CALL_NO_RWG, f16, f16, f16, fpst)
94
+DEF_HELPER_FLAGS_3(advsimd_minnumh, TCG_CALL_NO_RWG, f16, f16, f16, fpst)
95
+DEF_HELPER_3(advsimd_addh, f16, f16, f16, fpst)
96
+DEF_HELPER_3(advsimd_subh, f16, f16, f16, fpst)
97
+DEF_HELPER_3(advsimd_mulh, f16, f16, f16, fpst)
98
+DEF_HELPER_3(advsimd_divh, f16, f16, f16, fpst)
99
+DEF_HELPER_3(advsimd_ceq_f16, i32, f16, f16, fpst)
100
+DEF_HELPER_3(advsimd_cge_f16, i32, f16, f16, fpst)
101
+DEF_HELPER_3(advsimd_cgt_f16, i32, f16, f16, fpst)
102
+DEF_HELPER_3(advsimd_acge_f16, i32, f16, f16, fpst)
103
+DEF_HELPER_3(advsimd_acgt_f16, i32, f16, f16, fpst)
104
+DEF_HELPER_3(advsimd_mulxh, f16, f16, f16, fpst)
105
+DEF_HELPER_4(advsimd_muladdh, f16, f16, f16, f16, fpst)
106
+DEF_HELPER_3(advsimd_add2h, i32, i32, i32, fpst)
107
+DEF_HELPER_3(advsimd_sub2h, i32, i32, i32, fpst)
108
+DEF_HELPER_3(advsimd_mul2h, i32, i32, i32, fpst)
109
+DEF_HELPER_3(advsimd_div2h, i32, i32, i32, fpst)
110
+DEF_HELPER_3(advsimd_max2h, i32, i32, i32, fpst)
111
+DEF_HELPER_3(advsimd_min2h, i32, i32, i32, fpst)
112
+DEF_HELPER_3(advsimd_maxnum2h, i32, i32, i32, fpst)
113
+DEF_HELPER_3(advsimd_minnum2h, i32, i32, i32, fpst)
114
+DEF_HELPER_3(advsimd_mulx2h, i32, i32, i32, fpst)
115
+DEF_HELPER_4(advsimd_muladd2h, i32, i32, i32, i32, fpst)
116
+DEF_HELPER_2(advsimd_rinth_exact, f16, f16, fpst)
117
+DEF_HELPER_2(advsimd_rinth, f16, f16, fpst)
118
119
DEF_HELPER_2(exception_return, void, env, i64)
120
DEF_HELPER_FLAGS_2(dc_zva, TCG_CALL_NO_WG, void, env, i64)
121
diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c
122
index XXXXXXX..XXXXXXX 100644
123
--- a/target/arm/tcg/helper-a64.c
124
+++ b/target/arm/tcg/helper-a64.c
125
@@ -XXX,XX +XXX,XX @@ static inline uint32_t float_rel_to_flags(int res)
126
return flags;
127
}
128
129
-uint64_t HELPER(vfp_cmph_a64)(uint32_t x, uint32_t y, void *fp_status)
130
+uint64_t HELPER(vfp_cmph_a64)(uint32_t x, uint32_t y, float_status *fp_status)
131
{
132
return float_rel_to_flags(float16_compare_quiet(x, y, fp_status));
133
}
134
135
-uint64_t HELPER(vfp_cmpeh_a64)(uint32_t x, uint32_t y, void *fp_status)
136
+uint64_t HELPER(vfp_cmpeh_a64)(uint32_t x, uint32_t y, float_status *fp_status)
137
{
138
return float_rel_to_flags(float16_compare(x, y, fp_status));
139
}
140
141
-uint64_t HELPER(vfp_cmps_a64)(float32 x, float32 y, void *fp_status)
142
+uint64_t HELPER(vfp_cmps_a64)(float32 x, float32 y, float_status *fp_status)
143
{
144
return float_rel_to_flags(float32_compare_quiet(x, y, fp_status));
145
}
146
147
-uint64_t HELPER(vfp_cmpes_a64)(float32 x, float32 y, void *fp_status)
148
+uint64_t HELPER(vfp_cmpes_a64)(float32 x, float32 y, float_status *fp_status)
149
{
150
return float_rel_to_flags(float32_compare(x, y, fp_status));
151
}
152
153
-uint64_t HELPER(vfp_cmpd_a64)(float64 x, float64 y, void *fp_status)
154
+uint64_t HELPER(vfp_cmpd_a64)(float64 x, float64 y, float_status *fp_status)
155
{
156
return float_rel_to_flags(float64_compare_quiet(x, y, fp_status));
157
}
158
159
-uint64_t HELPER(vfp_cmped_a64)(float64 x, float64 y, void *fp_status)
160
+uint64_t HELPER(vfp_cmped_a64)(float64 x, float64 y, float_status *fp_status)
161
{
162
return float_rel_to_flags(float64_compare(x, y, fp_status));
163
}
164
165
-float32 HELPER(vfp_mulxs)(float32 a, float32 b, void *fpstp)
166
+float32 HELPER(vfp_mulxs)(float32 a, float32 b, float_status *fpst)
167
{
168
- float_status *fpst = fpstp;
169
-
170
a = float32_squash_input_denormal(a, fpst);
171
b = float32_squash_input_denormal(b, fpst);
172
173
@@ -XXX,XX +XXX,XX @@ float32 HELPER(vfp_mulxs)(float32 a, float32 b, void *fpstp)
174
return float32_mul(a, b, fpst);
175
}
176
177
-float64 HELPER(vfp_mulxd)(float64 a, float64 b, void *fpstp)
178
+float64 HELPER(vfp_mulxd)(float64 a, float64 b, float_status *fpst)
179
{
180
- float_status *fpst = fpstp;
181
-
182
a = float64_squash_input_denormal(a, fpst);
183
b = float64_squash_input_denormal(b, fpst);
184
185
@@ -XXX,XX +XXX,XX @@ float64 HELPER(vfp_mulxd)(float64 a, float64 b, void *fpstp)
186
}
187
188
/* 64bit/double versions of the neon float compare functions */
189
-uint64_t HELPER(neon_ceq_f64)(float64 a, float64 b, void *fpstp)
190
+uint64_t HELPER(neon_ceq_f64)(float64 a, float64 b, float_status *fpst)
191
{
192
- float_status *fpst = fpstp;
193
return -float64_eq_quiet(a, b, fpst);
194
}
195
196
-uint64_t HELPER(neon_cge_f64)(float64 a, float64 b, void *fpstp)
197
+uint64_t HELPER(neon_cge_f64)(float64 a, float64 b, float_status *fpst)
198
{
199
- float_status *fpst = fpstp;
200
return -float64_le(b, a, fpst);
201
}
202
203
-uint64_t HELPER(neon_cgt_f64)(float64 a, float64 b, void *fpstp)
204
+uint64_t HELPER(neon_cgt_f64)(float64 a, float64 b, float_status *fpst)
205
{
206
- float_status *fpst = fpstp;
207
return -float64_lt(b, a, fpst);
208
}
209
210
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(neon_cgt_f64)(float64 a, float64 b, void *fpstp)
211
* multiply-add-and-halve.
212
*/
213
214
-uint32_t HELPER(recpsf_f16)(uint32_t a, uint32_t b, void *fpstp)
215
+uint32_t HELPER(recpsf_f16)(uint32_t a, uint32_t b, float_status *fpst)
216
{
217
- float_status *fpst = fpstp;
218
-
219
a = float16_squash_input_denormal(a, fpst);
220
b = float16_squash_input_denormal(b, fpst);
221
222
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(recpsf_f16)(uint32_t a, uint32_t b, void *fpstp)
223
return float16_muladd(a, b, float16_two, 0, fpst);
224
}
225
226
-float32 HELPER(recpsf_f32)(float32 a, float32 b, void *fpstp)
227
+float32 HELPER(recpsf_f32)(float32 a, float32 b, float_status *fpst)
228
{
229
- float_status *fpst = fpstp;
230
-
231
a = float32_squash_input_denormal(a, fpst);
232
b = float32_squash_input_denormal(b, fpst);
233
234
@@ -XXX,XX +XXX,XX @@ float32 HELPER(recpsf_f32)(float32 a, float32 b, void *fpstp)
235
return float32_muladd(a, b, float32_two, 0, fpst);
236
}
237
238
-float64 HELPER(recpsf_f64)(float64 a, float64 b, void *fpstp)
239
+float64 HELPER(recpsf_f64)(float64 a, float64 b, float_status *fpst)
240
{
241
- float_status *fpst = fpstp;
242
-
243
a = float64_squash_input_denormal(a, fpst);
244
b = float64_squash_input_denormal(b, fpst);
245
246
@@ -XXX,XX +XXX,XX @@ float64 HELPER(recpsf_f64)(float64 a, float64 b, void *fpstp)
247
return float64_muladd(a, b, float64_two, 0, fpst);
248
}
249
250
-uint32_t HELPER(rsqrtsf_f16)(uint32_t a, uint32_t b, void *fpstp)
251
+uint32_t HELPER(rsqrtsf_f16)(uint32_t a, uint32_t b, float_status *fpst)
252
{
253
- float_status *fpst = fpstp;
254
-
255
a = float16_squash_input_denormal(a, fpst);
256
b = float16_squash_input_denormal(b, fpst);
257
258
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(rsqrtsf_f16)(uint32_t a, uint32_t b, void *fpstp)
259
return float16_muladd(a, b, float16_three, float_muladd_halve_result, fpst);
260
}
261
262
-float32 HELPER(rsqrtsf_f32)(float32 a, float32 b, void *fpstp)
263
+float32 HELPER(rsqrtsf_f32)(float32 a, float32 b, float_status *fpst)
264
{
265
- float_status *fpst = fpstp;
266
-
267
a = float32_squash_input_denormal(a, fpst);
268
b = float32_squash_input_denormal(b, fpst);
269
270
@@ -XXX,XX +XXX,XX @@ float32 HELPER(rsqrtsf_f32)(float32 a, float32 b, void *fpstp)
271
return float32_muladd(a, b, float32_three, float_muladd_halve_result, fpst);
272
}
273
274
-float64 HELPER(rsqrtsf_f64)(float64 a, float64 b, void *fpstp)
275
+float64 HELPER(rsqrtsf_f64)(float64 a, float64 b, float_status *fpst)
276
{
277
- float_status *fpst = fpstp;
278
-
279
a = float64_squash_input_denormal(a, fpst);
280
b = float64_squash_input_denormal(b, fpst);
281
282
@@ -XXX,XX +XXX,XX @@ float64 HELPER(rsqrtsf_f64)(float64 a, float64 b, void *fpstp)
283
}
284
285
/* Floating-point reciprocal exponent - see FPRecpX in ARM ARM */
286
-uint32_t HELPER(frecpx_f16)(uint32_t a, void *fpstp)
287
+uint32_t HELPER(frecpx_f16)(uint32_t a, float_status *fpst)
288
{
289
- float_status *fpst = fpstp;
290
uint16_t val16, sbit;
291
int16_t exp;
292
293
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(frecpx_f16)(uint32_t a, void *fpstp)
294
}
295
}
296
297
-float32 HELPER(frecpx_f32)(float32 a, void *fpstp)
298
+float32 HELPER(frecpx_f32)(float32 a, float_status *fpst)
299
{
300
- float_status *fpst = fpstp;
301
uint32_t val32, sbit;
302
int32_t exp;
303
304
@@ -XXX,XX +XXX,XX @@ float32 HELPER(frecpx_f32)(float32 a, void *fpstp)
305
}
306
}
307
308
-float64 HELPER(frecpx_f64)(float64 a, void *fpstp)
309
+float64 HELPER(frecpx_f64)(float64 a, float_status *fpst)
310
{
311
- float_status *fpst = fpstp;
312
uint64_t val64, sbit;
313
int64_t exp;
314
315
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(crc32c_64)(uint64_t acc, uint64_t val, uint32_t bytes)
316
#define ADVSIMD_HELPER(name, suffix) HELPER(glue(glue(advsimd_, name), suffix))
317
318
#define ADVSIMD_HALFOP(name) \
319
-uint32_t ADVSIMD_HELPER(name, h)(uint32_t a, uint32_t b, void *fpstp) \
320
+uint32_t ADVSIMD_HELPER(name, h)(uint32_t a, uint32_t b, float_status *fpst) \
321
{ \
322
- float_status *fpst = fpstp; \
323
return float16_ ## name(a, b, fpst); \
324
}
325
326
@@ -XXX,XX +XXX,XX @@ ADVSIMD_HALFOP(minnum)
327
ADVSIMD_HALFOP(maxnum)
328
329
#define ADVSIMD_TWOHALFOP(name) \
330
-uint32_t ADVSIMD_HELPER(name, 2h)(uint32_t two_a, uint32_t two_b, void *fpstp) \
331
+uint32_t ADVSIMD_HELPER(name, 2h)(uint32_t two_a, uint32_t two_b, \
332
+ float_status *fpst) \
333
{ \
334
float16 a1, a2, b1, b2; \
335
uint32_t r1, r2; \
336
- float_status *fpst = fpstp; \
337
a1 = extract32(two_a, 0, 16); \
338
a2 = extract32(two_a, 16, 16); \
339
b1 = extract32(two_b, 0, 16); \
340
@@ -XXX,XX +XXX,XX @@ ADVSIMD_TWOHALFOP(minnum)
341
ADVSIMD_TWOHALFOP(maxnum)
342
343
/* Data processing - scalar floating-point and advanced SIMD */
344
-static float16 float16_mulx(float16 a, float16 b, void *fpstp)
345
+static float16 float16_mulx(float16 a, float16 b, float_status *fpst)
346
{
347
- float_status *fpst = fpstp;
348
-
349
a = float16_squash_input_denormal(a, fpst);
350
b = float16_squash_input_denormal(b, fpst);
351
352
@@ -XXX,XX +XXX,XX @@ ADVSIMD_TWOHALFOP(mulx)
353
354
/* fused multiply-accumulate */
355
uint32_t HELPER(advsimd_muladdh)(uint32_t a, uint32_t b, uint32_t c,
356
- void *fpstp)
357
+ float_status *fpst)
358
{
359
- float_status *fpst = fpstp;
360
return float16_muladd(a, b, c, 0, fpst);
361
}
362
363
uint32_t HELPER(advsimd_muladd2h)(uint32_t two_a, uint32_t two_b,
364
- uint32_t two_c, void *fpstp)
365
+ uint32_t two_c, float_status *fpst)
366
{
367
- float_status *fpst = fpstp;
368
float16 a1, a2, b1, b2, c1, c2;
369
uint32_t r1, r2;
370
a1 = extract32(two_a, 0, 16);
371
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_muladd2h)(uint32_t two_a, uint32_t two_b,
372
373
#define ADVSIMD_CMPRES(test) (test) ? 0xffff : 0
374
375
-uint32_t HELPER(advsimd_ceq_f16)(uint32_t a, uint32_t b, void *fpstp)
376
+uint32_t HELPER(advsimd_ceq_f16)(uint32_t a, uint32_t b, float_status *fpst)
377
{
378
- float_status *fpst = fpstp;
379
int compare = float16_compare_quiet(a, b, fpst);
380
return ADVSIMD_CMPRES(compare == float_relation_equal);
381
}
382
383
-uint32_t HELPER(advsimd_cge_f16)(uint32_t a, uint32_t b, void *fpstp)
384
+uint32_t HELPER(advsimd_cge_f16)(uint32_t a, uint32_t b, float_status *fpst)
385
{
386
- float_status *fpst = fpstp;
387
int compare = float16_compare(a, b, fpst);
388
return ADVSIMD_CMPRES(compare == float_relation_greater ||
389
compare == float_relation_equal);
390
}
391
392
-uint32_t HELPER(advsimd_cgt_f16)(uint32_t a, uint32_t b, void *fpstp)
393
+uint32_t HELPER(advsimd_cgt_f16)(uint32_t a, uint32_t b, float_status *fpst)
394
{
395
- float_status *fpst = fpstp;
396
int compare = float16_compare(a, b, fpst);
397
return ADVSIMD_CMPRES(compare == float_relation_greater);
398
}
399
400
-uint32_t HELPER(advsimd_acge_f16)(uint32_t a, uint32_t b, void *fpstp)
401
+uint32_t HELPER(advsimd_acge_f16)(uint32_t a, uint32_t b, float_status *fpst)
402
{
403
- float_status *fpst = fpstp;
404
float16 f0 = float16_abs(a);
405
float16 f1 = float16_abs(b);
406
int compare = float16_compare(f0, f1, fpst);
407
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_acge_f16)(uint32_t a, uint32_t b, void *fpstp)
408
compare == float_relation_equal);
409
}
410
411
-uint32_t HELPER(advsimd_acgt_f16)(uint32_t a, uint32_t b, void *fpstp)
412
+uint32_t HELPER(advsimd_acgt_f16)(uint32_t a, uint32_t b, float_status *fpst)
413
{
414
- float_status *fpst = fpstp;
415
float16 f0 = float16_abs(a);
416
float16 f1 = float16_abs(b);
417
int compare = float16_compare(f0, f1, fpst);
418
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_acgt_f16)(uint32_t a, uint32_t b, void *fpstp)
419
}
420
421
/* round to integral */
422
-uint32_t HELPER(advsimd_rinth_exact)(uint32_t x, void *fp_status)
423
+uint32_t HELPER(advsimd_rinth_exact)(uint32_t x, float_status *fp_status)
424
{
425
return float16_round_to_int(x, fp_status);
426
}
427
428
-uint32_t HELPER(advsimd_rinth)(uint32_t x, void *fp_status)
429
+uint32_t HELPER(advsimd_rinth)(uint32_t x, float_status *fp_status)
430
{
431
int old_flags = get_float_exception_flags(fp_status), new_flags;
432
float16 ret;
433
--
434
2.34.1
435
436
diff view generated by jsdifflib
New patch
[PULL 04/19] target/arm: Convert vec_helper.c to fpst alias
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
Message-id: 20241206031224.78525-5-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/helper.h | 284 ++++++++++++++++++------------------
9
target/arm/tcg/helper-a64.h | 18 +--
10
target/arm/tcg/helper-sve.h | 12 +-
11
target/arm/tcg/vec_helper.c | 60 ++++----
12
4 files changed, 183 insertions(+), 191 deletions(-)
13
14
diff --git a/target/arm/helper.h b/target/arm/helper.h
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/helper.h
17
+++ b/target/arm/helper.h
18
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(gvec_usdot_idx_b, TCG_CALL_NO_RWG,
19
void, ptr, ptr, ptr, ptr, i32)
20
21
DEF_HELPER_FLAGS_5(gvec_fcaddh, TCG_CALL_NO_RWG,
22
- void, ptr, ptr, ptr, ptr, i32)
23
+ void, ptr, ptr, ptr, fpst, i32)
24
DEF_HELPER_FLAGS_5(gvec_fcadds, TCG_CALL_NO_RWG,
25
- void, ptr, ptr, ptr, ptr, i32)
26
+ void, ptr, ptr, ptr, fpst, i32)
27
DEF_HELPER_FLAGS_5(gvec_fcaddd, TCG_CALL_NO_RWG,
28
- void, ptr, ptr, ptr, ptr, i32)
29
+ void, ptr, ptr, ptr, fpst, i32)
30
31
DEF_HELPER_FLAGS_6(gvec_fcmlah, TCG_CALL_NO_RWG,
32
- void, ptr, ptr, ptr, ptr, ptr, i32)
33
+ void, ptr, ptr, ptr, ptr, fpst, i32)
34
DEF_HELPER_FLAGS_6(gvec_fcmlah_idx, TCG_CALL_NO_RWG,
35
- void, ptr, ptr, ptr, ptr, ptr, i32)
36
+ void, ptr, ptr, ptr, ptr, fpst, i32)
37
DEF_HELPER_FLAGS_6(gvec_fcmlas, TCG_CALL_NO_RWG,
38
- void, ptr, ptr, ptr, ptr, ptr, i32)
39
+ void, ptr, ptr, ptr, ptr, fpst, i32)
40
DEF_HELPER_FLAGS_6(gvec_fcmlas_idx, TCG_CALL_NO_RWG,
41
- void, ptr, ptr, ptr, ptr, ptr, i32)
42
+ void, ptr, ptr, ptr, ptr, fpst, i32)
43
DEF_HELPER_FLAGS_6(gvec_fcmlad, TCG_CALL_NO_RWG,
44
- void, ptr, ptr, ptr, ptr, ptr, i32)
45
+ void, ptr, ptr, ptr, ptr, fpst, i32)
46
47
-DEF_HELPER_FLAGS_4(gvec_sstoh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
48
-DEF_HELPER_FLAGS_4(gvec_sitos, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
49
-DEF_HELPER_FLAGS_4(gvec_ustoh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
50
-DEF_HELPER_FLAGS_4(gvec_uitos, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
51
-DEF_HELPER_FLAGS_4(gvec_tosszh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
52
-DEF_HELPER_FLAGS_4(gvec_tosizs, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
53
-DEF_HELPER_FLAGS_4(gvec_touszh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
54
-DEF_HELPER_FLAGS_4(gvec_touizs, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
55
+DEF_HELPER_FLAGS_4(gvec_sstoh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
56
+DEF_HELPER_FLAGS_4(gvec_sitos, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
57
+DEF_HELPER_FLAGS_4(gvec_ustoh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
58
+DEF_HELPER_FLAGS_4(gvec_uitos, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
59
+DEF_HELPER_FLAGS_4(gvec_tosszh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
60
+DEF_HELPER_FLAGS_4(gvec_tosizs, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
61
+DEF_HELPER_FLAGS_4(gvec_touszh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
62
+DEF_HELPER_FLAGS_4(gvec_touizs, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
63
64
-DEF_HELPER_FLAGS_4(gvec_vcvt_sf, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
65
-DEF_HELPER_FLAGS_4(gvec_vcvt_uf, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
66
-DEF_HELPER_FLAGS_4(gvec_vcvt_rz_fs, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
67
-DEF_HELPER_FLAGS_4(gvec_vcvt_rz_fu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
68
+DEF_HELPER_FLAGS_4(gvec_vcvt_sf, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
69
+DEF_HELPER_FLAGS_4(gvec_vcvt_uf, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
70
+DEF_HELPER_FLAGS_4(gvec_vcvt_rz_fs, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
71
+DEF_HELPER_FLAGS_4(gvec_vcvt_rz_fu, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
72
73
-DEF_HELPER_FLAGS_4(gvec_vcvt_sh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
74
-DEF_HELPER_FLAGS_4(gvec_vcvt_uh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
75
-DEF_HELPER_FLAGS_4(gvec_vcvt_rz_hs, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
76
-DEF_HELPER_FLAGS_4(gvec_vcvt_rz_hu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
77
+DEF_HELPER_FLAGS_4(gvec_vcvt_sh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
78
+DEF_HELPER_FLAGS_4(gvec_vcvt_uh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
79
+DEF_HELPER_FLAGS_4(gvec_vcvt_rz_hs, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
80
+DEF_HELPER_FLAGS_4(gvec_vcvt_rz_hu, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
81
82
-DEF_HELPER_FLAGS_4(gvec_vcvt_sd, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
83
-DEF_HELPER_FLAGS_4(gvec_vcvt_ud, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
84
-DEF_HELPER_FLAGS_4(gvec_vcvt_rz_ds, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
85
-DEF_HELPER_FLAGS_4(gvec_vcvt_rz_du, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
86
+DEF_HELPER_FLAGS_4(gvec_vcvt_sd, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
87
+DEF_HELPER_FLAGS_4(gvec_vcvt_ud, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
88
+DEF_HELPER_FLAGS_4(gvec_vcvt_rz_ds, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
89
+DEF_HELPER_FLAGS_4(gvec_vcvt_rz_du, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
90
91
-DEF_HELPER_FLAGS_4(gvec_vcvt_rm_sd, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
92
-DEF_HELPER_FLAGS_4(gvec_vcvt_rm_ud, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
93
-DEF_HELPER_FLAGS_4(gvec_vcvt_rm_ss, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
94
-DEF_HELPER_FLAGS_4(gvec_vcvt_rm_us, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
95
-DEF_HELPER_FLAGS_4(gvec_vcvt_rm_sh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
96
-DEF_HELPER_FLAGS_4(gvec_vcvt_rm_uh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
97
+DEF_HELPER_FLAGS_4(gvec_vcvt_rm_sd, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
98
+DEF_HELPER_FLAGS_4(gvec_vcvt_rm_ud, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
99
+DEF_HELPER_FLAGS_4(gvec_vcvt_rm_ss, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
100
+DEF_HELPER_FLAGS_4(gvec_vcvt_rm_us, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
101
+DEF_HELPER_FLAGS_4(gvec_vcvt_rm_sh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
102
+DEF_HELPER_FLAGS_4(gvec_vcvt_rm_uh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
103
104
-DEF_HELPER_FLAGS_4(gvec_vrint_rm_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
105
-DEF_HELPER_FLAGS_4(gvec_vrint_rm_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
106
+DEF_HELPER_FLAGS_4(gvec_vrint_rm_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
107
+DEF_HELPER_FLAGS_4(gvec_vrint_rm_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
108
109
-DEF_HELPER_FLAGS_4(gvec_vrintx_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
110
-DEF_HELPER_FLAGS_4(gvec_vrintx_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
111
+DEF_HELPER_FLAGS_4(gvec_vrintx_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
112
+DEF_HELPER_FLAGS_4(gvec_vrintx_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
113
114
-DEF_HELPER_FLAGS_4(gvec_frecpe_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
115
-DEF_HELPER_FLAGS_4(gvec_frecpe_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
116
-DEF_HELPER_FLAGS_4(gvec_frecpe_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
117
+DEF_HELPER_FLAGS_4(gvec_frecpe_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
118
+DEF_HELPER_FLAGS_4(gvec_frecpe_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
119
+DEF_HELPER_FLAGS_4(gvec_frecpe_d, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
120
121
-DEF_HELPER_FLAGS_4(gvec_frsqrte_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
122
-DEF_HELPER_FLAGS_4(gvec_frsqrte_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
123
-DEF_HELPER_FLAGS_4(gvec_frsqrte_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
124
+DEF_HELPER_FLAGS_4(gvec_frsqrte_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
125
+DEF_HELPER_FLAGS_4(gvec_frsqrte_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
126
+DEF_HELPER_FLAGS_4(gvec_frsqrte_d, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
127
128
-DEF_HELPER_FLAGS_4(gvec_fcgt0_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
129
-DEF_HELPER_FLAGS_4(gvec_fcgt0_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
130
-DEF_HELPER_FLAGS_4(gvec_fcgt0_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
131
+DEF_HELPER_FLAGS_4(gvec_fcgt0_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
132
+DEF_HELPER_FLAGS_4(gvec_fcgt0_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
133
+DEF_HELPER_FLAGS_4(gvec_fcgt0_d, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
134
135
-DEF_HELPER_FLAGS_4(gvec_fcge0_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
136
-DEF_HELPER_FLAGS_4(gvec_fcge0_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
137
-DEF_HELPER_FLAGS_4(gvec_fcge0_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
138
+DEF_HELPER_FLAGS_4(gvec_fcge0_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
139
+DEF_HELPER_FLAGS_4(gvec_fcge0_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
140
+DEF_HELPER_FLAGS_4(gvec_fcge0_d, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
141
142
-DEF_HELPER_FLAGS_4(gvec_fceq0_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
143
-DEF_HELPER_FLAGS_4(gvec_fceq0_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
144
-DEF_HELPER_FLAGS_4(gvec_fceq0_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
145
+DEF_HELPER_FLAGS_4(gvec_fceq0_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
146
+DEF_HELPER_FLAGS_4(gvec_fceq0_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
147
+DEF_HELPER_FLAGS_4(gvec_fceq0_d, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
148
149
-DEF_HELPER_FLAGS_4(gvec_fcle0_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
150
-DEF_HELPER_FLAGS_4(gvec_fcle0_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
151
-DEF_HELPER_FLAGS_4(gvec_fcle0_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
152
+DEF_HELPER_FLAGS_4(gvec_fcle0_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
153
+DEF_HELPER_FLAGS_4(gvec_fcle0_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
154
+DEF_HELPER_FLAGS_4(gvec_fcle0_d, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
155
156
-DEF_HELPER_FLAGS_4(gvec_fclt0_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
157
-DEF_HELPER_FLAGS_4(gvec_fclt0_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
158
-DEF_HELPER_FLAGS_4(gvec_fclt0_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
159
+DEF_HELPER_FLAGS_4(gvec_fclt0_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
160
+DEF_HELPER_FLAGS_4(gvec_fclt0_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
161
+DEF_HELPER_FLAGS_4(gvec_fclt0_d, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
162
163
-DEF_HELPER_FLAGS_5(gvec_fadd_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
164
-DEF_HELPER_FLAGS_5(gvec_fadd_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
165
-DEF_HELPER_FLAGS_5(gvec_fadd_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
166
+DEF_HELPER_FLAGS_5(gvec_fadd_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
167
+DEF_HELPER_FLAGS_5(gvec_fadd_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
168
+DEF_HELPER_FLAGS_5(gvec_fadd_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
169
170
-DEF_HELPER_FLAGS_5(gvec_fsub_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
171
-DEF_HELPER_FLAGS_5(gvec_fsub_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
172
-DEF_HELPER_FLAGS_5(gvec_fsub_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
173
+DEF_HELPER_FLAGS_5(gvec_fsub_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
174
+DEF_HELPER_FLAGS_5(gvec_fsub_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
175
+DEF_HELPER_FLAGS_5(gvec_fsub_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
176
177
-DEF_HELPER_FLAGS_5(gvec_fmul_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
178
-DEF_HELPER_FLAGS_5(gvec_fmul_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
179
-DEF_HELPER_FLAGS_5(gvec_fmul_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
180
+DEF_HELPER_FLAGS_5(gvec_fmul_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
181
+DEF_HELPER_FLAGS_5(gvec_fmul_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
182
+DEF_HELPER_FLAGS_5(gvec_fmul_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
183
184
-DEF_HELPER_FLAGS_5(gvec_fabd_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
185
-DEF_HELPER_FLAGS_5(gvec_fabd_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
186
-DEF_HELPER_FLAGS_5(gvec_fabd_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
187
+DEF_HELPER_FLAGS_5(gvec_fabd_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
188
+DEF_HELPER_FLAGS_5(gvec_fabd_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
189
+DEF_HELPER_FLAGS_5(gvec_fabd_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
190
191
-DEF_HELPER_FLAGS_5(gvec_fceq_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
192
-DEF_HELPER_FLAGS_5(gvec_fceq_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
193
-DEF_HELPER_FLAGS_5(gvec_fceq_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
194
+DEF_HELPER_FLAGS_5(gvec_fceq_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
195
+DEF_HELPER_FLAGS_5(gvec_fceq_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
196
+DEF_HELPER_FLAGS_5(gvec_fceq_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
197
198
-DEF_HELPER_FLAGS_5(gvec_fcge_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
199
-DEF_HELPER_FLAGS_5(gvec_fcge_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
200
-DEF_HELPER_FLAGS_5(gvec_fcge_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
201
+DEF_HELPER_FLAGS_5(gvec_fcge_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
202
+DEF_HELPER_FLAGS_5(gvec_fcge_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
203
+DEF_HELPER_FLAGS_5(gvec_fcge_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
204
205
-DEF_HELPER_FLAGS_5(gvec_fcgt_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
206
-DEF_HELPER_FLAGS_5(gvec_fcgt_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
207
-DEF_HELPER_FLAGS_5(gvec_fcgt_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
208
+DEF_HELPER_FLAGS_5(gvec_fcgt_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
209
+DEF_HELPER_FLAGS_5(gvec_fcgt_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
210
+DEF_HELPER_FLAGS_5(gvec_fcgt_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
211
212
-DEF_HELPER_FLAGS_5(gvec_facge_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
213
-DEF_HELPER_FLAGS_5(gvec_facge_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
214
-DEF_HELPER_FLAGS_5(gvec_facge_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
215
+DEF_HELPER_FLAGS_5(gvec_facge_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
216
+DEF_HELPER_FLAGS_5(gvec_facge_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
217
+DEF_HELPER_FLAGS_5(gvec_facge_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
218
219
-DEF_HELPER_FLAGS_5(gvec_facgt_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
220
-DEF_HELPER_FLAGS_5(gvec_facgt_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
221
-DEF_HELPER_FLAGS_5(gvec_facgt_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
222
+DEF_HELPER_FLAGS_5(gvec_facgt_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
223
+DEF_HELPER_FLAGS_5(gvec_facgt_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
224
+DEF_HELPER_FLAGS_5(gvec_facgt_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
225
226
-DEF_HELPER_FLAGS_5(gvec_fmax_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
227
-DEF_HELPER_FLAGS_5(gvec_fmax_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
228
-DEF_HELPER_FLAGS_5(gvec_fmax_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
229
+DEF_HELPER_FLAGS_5(gvec_fmax_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
230
+DEF_HELPER_FLAGS_5(gvec_fmax_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
231
+DEF_HELPER_FLAGS_5(gvec_fmax_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
232
233
-DEF_HELPER_FLAGS_5(gvec_fmin_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
234
-DEF_HELPER_FLAGS_5(gvec_fmin_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
235
-DEF_HELPER_FLAGS_5(gvec_fmin_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
236
+DEF_HELPER_FLAGS_5(gvec_fmin_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
237
+DEF_HELPER_FLAGS_5(gvec_fmin_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
238
+DEF_HELPER_FLAGS_5(gvec_fmin_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
239
240
-DEF_HELPER_FLAGS_5(gvec_fmaxnum_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
241
-DEF_HELPER_FLAGS_5(gvec_fmaxnum_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
242
-DEF_HELPER_FLAGS_5(gvec_fmaxnum_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
243
+DEF_HELPER_FLAGS_5(gvec_fmaxnum_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
244
+DEF_HELPER_FLAGS_5(gvec_fmaxnum_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
245
+DEF_HELPER_FLAGS_5(gvec_fmaxnum_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
246
247
-DEF_HELPER_FLAGS_5(gvec_fminnum_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
248
-DEF_HELPER_FLAGS_5(gvec_fminnum_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
249
-DEF_HELPER_FLAGS_5(gvec_fminnum_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
250
+DEF_HELPER_FLAGS_5(gvec_fminnum_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
251
+DEF_HELPER_FLAGS_5(gvec_fminnum_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
252
+DEF_HELPER_FLAGS_5(gvec_fminnum_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
253
254
-DEF_HELPER_FLAGS_5(gvec_recps_nf_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
255
-DEF_HELPER_FLAGS_5(gvec_recps_nf_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
256
+DEF_HELPER_FLAGS_5(gvec_recps_nf_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
257
+DEF_HELPER_FLAGS_5(gvec_recps_nf_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
258
259
-DEF_HELPER_FLAGS_5(gvec_rsqrts_nf_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
260
-DEF_HELPER_FLAGS_5(gvec_rsqrts_nf_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
261
+DEF_HELPER_FLAGS_5(gvec_rsqrts_nf_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
262
+DEF_HELPER_FLAGS_5(gvec_rsqrts_nf_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
263
264
-DEF_HELPER_FLAGS_5(gvec_fmla_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
265
-DEF_HELPER_FLAGS_5(gvec_fmla_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
266
+DEF_HELPER_FLAGS_5(gvec_fmla_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
267
+DEF_HELPER_FLAGS_5(gvec_fmla_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
268
269
-DEF_HELPER_FLAGS_5(gvec_fmls_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
270
-DEF_HELPER_FLAGS_5(gvec_fmls_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
271
+DEF_HELPER_FLAGS_5(gvec_fmls_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
272
+DEF_HELPER_FLAGS_5(gvec_fmls_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
273
274
-DEF_HELPER_FLAGS_5(gvec_vfma_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
275
-DEF_HELPER_FLAGS_5(gvec_vfma_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
276
-DEF_HELPER_FLAGS_5(gvec_vfma_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
277
+DEF_HELPER_FLAGS_5(gvec_vfma_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
278
+DEF_HELPER_FLAGS_5(gvec_vfma_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
279
+DEF_HELPER_FLAGS_5(gvec_vfma_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
280
281
-DEF_HELPER_FLAGS_5(gvec_vfms_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
282
-DEF_HELPER_FLAGS_5(gvec_vfms_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
283
-DEF_HELPER_FLAGS_5(gvec_vfms_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
284
+DEF_HELPER_FLAGS_5(gvec_vfms_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
285
+DEF_HELPER_FLAGS_5(gvec_vfms_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
286
+DEF_HELPER_FLAGS_5(gvec_vfms_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
287
288
DEF_HELPER_FLAGS_5(gvec_ftsmul_h, TCG_CALL_NO_RWG,
289
- void, ptr, ptr, ptr, ptr, i32)
290
+ void, ptr, ptr, ptr, fpst, i32)
291
DEF_HELPER_FLAGS_5(gvec_ftsmul_s, TCG_CALL_NO_RWG,
292
- void, ptr, ptr, ptr, ptr, i32)
293
+ void, ptr, ptr, ptr, fpst, i32)
294
DEF_HELPER_FLAGS_5(gvec_ftsmul_d, TCG_CALL_NO_RWG,
295
- void, ptr, ptr, ptr, ptr, i32)
296
+ void, ptr, ptr, ptr, fpst, i32)
297
298
DEF_HELPER_FLAGS_5(gvec_fmul_idx_h, TCG_CALL_NO_RWG,
299
- void, ptr, ptr, ptr, ptr, i32)
300
+ void, ptr, ptr, ptr, fpst, i32)
301
DEF_HELPER_FLAGS_5(gvec_fmul_idx_s, TCG_CALL_NO_RWG,
302
- void, ptr, ptr, ptr, ptr, i32)
303
+ void, ptr, ptr, ptr, fpst, i32)
304
DEF_HELPER_FLAGS_5(gvec_fmul_idx_d, TCG_CALL_NO_RWG,
305
- void, ptr, ptr, ptr, ptr, i32)
306
+ void, ptr, ptr, ptr, fpst, i32)
307
308
DEF_HELPER_FLAGS_5(gvec_fmla_nf_idx_h, TCG_CALL_NO_RWG,
309
- void, ptr, ptr, ptr, ptr, i32)
310
+ void, ptr, ptr, ptr, fpst, i32)
311
DEF_HELPER_FLAGS_5(gvec_fmla_nf_idx_s, TCG_CALL_NO_RWG,
312
- void, ptr, ptr, ptr, ptr, i32)
313
+ void, ptr, ptr, ptr, fpst, i32)
314
315
DEF_HELPER_FLAGS_5(gvec_fmls_nf_idx_h, TCG_CALL_NO_RWG,
316
- void, ptr, ptr, ptr, ptr, i32)
317
+ void, ptr, ptr, ptr, fpst, i32)
318
DEF_HELPER_FLAGS_5(gvec_fmls_nf_idx_s, TCG_CALL_NO_RWG,
319
- void, ptr, ptr, ptr, ptr, i32)
320
+ void, ptr, ptr, ptr, fpst, i32)
321
322
DEF_HELPER_FLAGS_6(gvec_fmla_idx_h, TCG_CALL_NO_RWG,
323
- void, ptr, ptr, ptr, ptr, ptr, i32)
324
+ void, ptr, ptr, ptr, ptr, fpst, i32)
325
DEF_HELPER_FLAGS_6(gvec_fmla_idx_s, TCG_CALL_NO_RWG,
326
- void, ptr, ptr, ptr, ptr, ptr, i32)
327
+ void, ptr, ptr, ptr, ptr, fpst, i32)
328
DEF_HELPER_FLAGS_6(gvec_fmla_idx_d, TCG_CALL_NO_RWG,
329
- void, ptr, ptr, ptr, ptr, ptr, i32)
330
+ void, ptr, ptr, ptr, ptr, fpst, i32)
331
332
DEF_HELPER_FLAGS_5(gvec_uqadd_b, TCG_CALL_NO_RWG,
333
void, ptr, ptr, ptr, ptr, i32)
334
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_6(gvec_bfmmla, TCG_CALL_NO_RWG,
335
void, ptr, ptr, ptr, ptr, env, i32)
336
337
DEF_HELPER_FLAGS_6(gvec_bfmlal, TCG_CALL_NO_RWG,
338
- void, ptr, ptr, ptr, ptr, ptr, i32)
339
+ void, ptr, ptr, ptr, ptr, fpst, i32)
340
DEF_HELPER_FLAGS_6(gvec_bfmlal_idx, TCG_CALL_NO_RWG,
341
- void, ptr, ptr, ptr, ptr, ptr, i32)
342
+ void, ptr, ptr, ptr, ptr, fpst, i32)
343
344
DEF_HELPER_FLAGS_5(gvec_sclamp_b, TCG_CALL_NO_RWG,
345
void, ptr, ptr, ptr, ptr, i32)
346
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(gvec_uclamp_s, TCG_CALL_NO_RWG,
347
DEF_HELPER_FLAGS_5(gvec_uclamp_d, TCG_CALL_NO_RWG,
348
void, ptr, ptr, ptr, ptr, i32)
349
350
-DEF_HELPER_FLAGS_5(gvec_faddp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
351
-DEF_HELPER_FLAGS_5(gvec_faddp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
352
-DEF_HELPER_FLAGS_5(gvec_faddp_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
353
+DEF_HELPER_FLAGS_5(gvec_faddp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
354
+DEF_HELPER_FLAGS_5(gvec_faddp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
355
+DEF_HELPER_FLAGS_5(gvec_faddp_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
356
357
-DEF_HELPER_FLAGS_5(gvec_fmaxp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
358
-DEF_HELPER_FLAGS_5(gvec_fmaxp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
359
-DEF_HELPER_FLAGS_5(gvec_fmaxp_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
360
+DEF_HELPER_FLAGS_5(gvec_fmaxp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
361
+DEF_HELPER_FLAGS_5(gvec_fmaxp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
362
+DEF_HELPER_FLAGS_5(gvec_fmaxp_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
363
364
-DEF_HELPER_FLAGS_5(gvec_fminp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
365
-DEF_HELPER_FLAGS_5(gvec_fminp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
366
-DEF_HELPER_FLAGS_5(gvec_fminp_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
367
+DEF_HELPER_FLAGS_5(gvec_fminp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
368
+DEF_HELPER_FLAGS_5(gvec_fminp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
369
+DEF_HELPER_FLAGS_5(gvec_fminp_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
370
371
-DEF_HELPER_FLAGS_5(gvec_fmaxnump_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
372
-DEF_HELPER_FLAGS_5(gvec_fmaxnump_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
373
-DEF_HELPER_FLAGS_5(gvec_fmaxnump_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
374
+DEF_HELPER_FLAGS_5(gvec_fmaxnump_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
375
+DEF_HELPER_FLAGS_5(gvec_fmaxnump_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
376
+DEF_HELPER_FLAGS_5(gvec_fmaxnump_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
377
378
-DEF_HELPER_FLAGS_5(gvec_fminnump_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
379
-DEF_HELPER_FLAGS_5(gvec_fminnump_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
380
-DEF_HELPER_FLAGS_5(gvec_fminnump_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
381
+DEF_HELPER_FLAGS_5(gvec_fminnump_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
382
+DEF_HELPER_FLAGS_5(gvec_fminnump_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
383
+DEF_HELPER_FLAGS_5(gvec_fminnump_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
384
385
DEF_HELPER_FLAGS_4(gvec_addp_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
386
DEF_HELPER_FLAGS_4(gvec_addp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
387
diff --git a/target/arm/tcg/helper-a64.h b/target/arm/tcg/helper-a64.h
388
index XXXXXXX..XXXXXXX 100644
389
--- a/target/arm/tcg/helper-a64.h
390
+++ b/target/arm/tcg/helper-a64.h
391
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_4(cpyfe, void, env, i32, i32, i32)
392
DEF_HELPER_FLAGS_1(guarded_page_check, TCG_CALL_NO_WG, void, env)
393
DEF_HELPER_FLAGS_2(guarded_page_br, TCG_CALL_NO_RWG, void, env, tl)
394
395
-DEF_HELPER_FLAGS_5(gvec_fdiv_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
396
-DEF_HELPER_FLAGS_5(gvec_fdiv_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
397
-DEF_HELPER_FLAGS_5(gvec_fdiv_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
398
+DEF_HELPER_FLAGS_5(gvec_fdiv_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
399
+DEF_HELPER_FLAGS_5(gvec_fdiv_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
400
+DEF_HELPER_FLAGS_5(gvec_fdiv_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
401
402
-DEF_HELPER_FLAGS_5(gvec_fmulx_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
403
-DEF_HELPER_FLAGS_5(gvec_fmulx_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
404
-DEF_HELPER_FLAGS_5(gvec_fmulx_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
405
+DEF_HELPER_FLAGS_5(gvec_fmulx_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
406
+DEF_HELPER_FLAGS_5(gvec_fmulx_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
407
+DEF_HELPER_FLAGS_5(gvec_fmulx_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
408
409
-DEF_HELPER_FLAGS_5(gvec_fmulx_idx_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
410
-DEF_HELPER_FLAGS_5(gvec_fmulx_idx_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
411
-DEF_HELPER_FLAGS_5(gvec_fmulx_idx_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
412
+DEF_HELPER_FLAGS_5(gvec_fmulx_idx_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
413
+DEF_HELPER_FLAGS_5(gvec_fmulx_idx_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
414
+DEF_HELPER_FLAGS_5(gvec_fmulx_idx_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
415
diff --git a/target/arm/tcg/helper-sve.h b/target/arm/tcg/helper-sve.h
416
index XXXXXXX..XXXXXXX 100644
417
--- a/target/arm/tcg/helper-sve.h
418
+++ b/target/arm/tcg/helper-sve.h
419
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(sve_umini_s, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
420
DEF_HELPER_FLAGS_4(sve_umini_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
421
422
DEF_HELPER_FLAGS_5(gvec_recps_h, TCG_CALL_NO_RWG,
423
- void, ptr, ptr, ptr, ptr, i32)
424
+ void, ptr, ptr, ptr, fpst, i32)
425
DEF_HELPER_FLAGS_5(gvec_recps_s, TCG_CALL_NO_RWG,
426
- void, ptr, ptr, ptr, ptr, i32)
427
+ void, ptr, ptr, ptr, fpst, i32)
428
DEF_HELPER_FLAGS_5(gvec_recps_d, TCG_CALL_NO_RWG,
429
- void, ptr, ptr, ptr, ptr, i32)
430
+ void, ptr, ptr, ptr, fpst, i32)
431
432
DEF_HELPER_FLAGS_5(gvec_rsqrts_h, TCG_CALL_NO_RWG,
433
- void, ptr, ptr, ptr, ptr, i32)
434
+ void, ptr, ptr, ptr, fpst, i32)
435
DEF_HELPER_FLAGS_5(gvec_rsqrts_s, TCG_CALL_NO_RWG,
436
- void, ptr, ptr, ptr, ptr, i32)
437
+ void, ptr, ptr, ptr, fpst, i32)
438
DEF_HELPER_FLAGS_5(gvec_rsqrts_d, TCG_CALL_NO_RWG,
439
- void, ptr, ptr, ptr, ptr, i32)
440
+ void, ptr, ptr, ptr, fpst, i32)
441
442
DEF_HELPER_FLAGS_4(sve_faddv_h, TCG_CALL_NO_RWG,
443
i64, ptr, ptr, ptr, i32)
444
diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c
445
index XXXXXXX..XXXXXXX 100644
446
--- a/target/arm/tcg/vec_helper.c
447
+++ b/target/arm/tcg/vec_helper.c
448
@@ -XXX,XX +XXX,XX @@ DO_DOT_IDX(gvec_sdot_idx_h, int64_t, int16_t, int16_t, H8)
449
DO_DOT_IDX(gvec_udot_idx_h, uint64_t, uint16_t, uint16_t, H8)
450
451
void HELPER(gvec_fcaddh)(void *vd, void *vn, void *vm,
452
- void *vfpst, uint32_t desc)
453
+ float_status *fpst, uint32_t desc)
454
{
455
uintptr_t opr_sz = simd_oprsz(desc);
456
float16 *d = vd;
457
float16 *n = vn;
458
float16 *m = vm;
459
- float_status *fpst = vfpst;
460
uint32_t neg_real = extract32(desc, SIMD_DATA_SHIFT, 1);
461
uint32_t neg_imag = neg_real ^ 1;
462
uintptr_t i;
463
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_fcaddh)(void *vd, void *vn, void *vm,
464
}
465
466
void HELPER(gvec_fcadds)(void *vd, void *vn, void *vm,
467
- void *vfpst, uint32_t desc)
468
+ float_status *fpst, uint32_t desc)
469
{
470
uintptr_t opr_sz = simd_oprsz(desc);
471
float32 *d = vd;
472
float32 *n = vn;
473
float32 *m = vm;
474
- float_status *fpst = vfpst;
475
uint32_t neg_real = extract32(desc, SIMD_DATA_SHIFT, 1);
476
uint32_t neg_imag = neg_real ^ 1;
477
uintptr_t i;
478
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_fcadds)(void *vd, void *vn, void *vm,
479
}
480
481
void HELPER(gvec_fcaddd)(void *vd, void *vn, void *vm,
482
- void *vfpst, uint32_t desc)
483
+ float_status *fpst, uint32_t desc)
484
{
485
uintptr_t opr_sz = simd_oprsz(desc);
486
float64 *d = vd;
487
float64 *n = vn;
488
float64 *m = vm;
489
- float_status *fpst = vfpst;
490
uint64_t neg_real = extract64(desc, SIMD_DATA_SHIFT, 1);
491
uint64_t neg_imag = neg_real ^ 1;
492
uintptr_t i;
493
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_fcaddd)(void *vd, void *vn, void *vm,
494
}
495
496
void HELPER(gvec_fcmlah)(void *vd, void *vn, void *vm, void *va,
497
- void *vfpst, uint32_t desc)
498
+ float_status *fpst, uint32_t desc)
499
{
500
uintptr_t opr_sz = simd_oprsz(desc);
501
float16 *d = vd, *n = vn, *m = vm, *a = va;
502
- float_status *fpst = vfpst;
503
intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1);
504
uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
505
uint32_t neg_real = flip ^ neg_imag;
506
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_fcmlah)(void *vd, void *vn, void *vm, void *va,
507
}
508
509
void HELPER(gvec_fcmlah_idx)(void *vd, void *vn, void *vm, void *va,
510
- void *vfpst, uint32_t desc)
511
+ float_status *fpst, uint32_t desc)
512
{
513
uintptr_t opr_sz = simd_oprsz(desc);
514
float16 *d = vd, *n = vn, *m = vm, *a = va;
515
- float_status *fpst = vfpst;
516
intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1);
517
uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
518
intptr_t index = extract32(desc, SIMD_DATA_SHIFT + 2, 2);
519
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_fcmlah_idx)(void *vd, void *vn, void *vm, void *va,
520
}
521
522
void HELPER(gvec_fcmlas)(void *vd, void *vn, void *vm, void *va,
523
- void *vfpst, uint32_t desc)
524
+ float_status *fpst, uint32_t desc)
525
{
526
uintptr_t opr_sz = simd_oprsz(desc);
527
float32 *d = vd, *n = vn, *m = vm, *a = va;
528
- float_status *fpst = vfpst;
529
intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1);
530
uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
531
uint32_t neg_real = flip ^ neg_imag;
532
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_fcmlas)(void *vd, void *vn, void *vm, void *va,
533
}
534
535
void HELPER(gvec_fcmlas_idx)(void *vd, void *vn, void *vm, void *va,
536
- void *vfpst, uint32_t desc)
537
+ float_status *fpst, uint32_t desc)
538
{
539
uintptr_t opr_sz = simd_oprsz(desc);
540
float32 *d = vd, *n = vn, *m = vm, *a = va;
541
- float_status *fpst = vfpst;
542
intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1);
543
uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
544
intptr_t index = extract32(desc, SIMD_DATA_SHIFT + 2, 2);
545
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_fcmlas_idx)(void *vd, void *vn, void *vm, void *va,
546
}
547
548
void HELPER(gvec_fcmlad)(void *vd, void *vn, void *vm, void *va,
549
- void *vfpst, uint32_t desc)
550
+ float_status *fpst, uint32_t desc)
551
{
552
uintptr_t opr_sz = simd_oprsz(desc);
553
float64 *d = vd, *n = vn, *m = vm, *a = va;
554
- float_status *fpst = vfpst;
555
intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1);
556
uint64_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
557
uint64_t neg_real = flip ^ neg_imag;
558
@@ -XXX,XX +XXX,XX @@ static uint64_t float64_acgt(float64 op1, float64 op2, float_status *stat)
559
return -float64_lt(float64_abs(op2), float64_abs(op1), stat);
560
}
561
562
-static int16_t vfp_tosszh(float16 x, void *fpstp)
563
+static int16_t vfp_tosszh(float16 x, float_status *fpst)
564
{
565
- float_status *fpst = fpstp;
566
if (float16_is_any_nan(x)) {
567
float_raise(float_flag_invalid, fpst);
568
return 0;
569
@@ -XXX,XX +XXX,XX @@ static int16_t vfp_tosszh(float16 x, void *fpstp)
570
return float16_to_int16_round_to_zero(x, fpst);
571
}
572
573
-static uint16_t vfp_touszh(float16 x, void *fpstp)
574
+static uint16_t vfp_touszh(float16 x, float_status *fpst)
575
{
576
- float_status *fpst = fpstp;
577
if (float16_is_any_nan(x)) {
578
float_raise(float_flag_invalid, fpst);
579
return 0;
580
@@ -XXX,XX +XXX,XX @@ static uint16_t vfp_touszh(float16 x, void *fpstp)
581
}
582
583
#define DO_2OP(NAME, FUNC, TYPE) \
584
-void HELPER(NAME)(void *vd, void *vn, void *stat, uint32_t desc) \
585
+void HELPER(NAME)(void *vd, void *vn, float_status *stat, uint32_t desc) \
586
{ \
587
intptr_t i, oprsz = simd_oprsz(desc); \
588
TYPE *d = vd, *n = vn; \
589
@@ -XXX,XX +XXX,XX @@ static float32 float32_rsqrts_nf(float32 op1, float32 op2, float_status *stat)
590
}
591
592
#define DO_3OP(NAME, FUNC, TYPE) \
593
-void HELPER(NAME)(void *vd, void *vn, void *vm, void *stat, uint32_t desc) \
594
+void HELPER(NAME)(void *vd, void *vn, void *vm, \
595
+ float_status *stat, uint32_t desc) \
596
{ \
597
intptr_t i, oprsz = simd_oprsz(desc); \
598
TYPE *d = vd, *n = vn, *m = vm; \
599
@@ -XXX,XX +XXX,XX @@ static float64 float64_mulsub_f(float64 dest, float64 op1, float64 op2,
600
return float64_muladd(float64_chs(op1), op2, dest, 0, stat);
601
}
602
603
-#define DO_MULADD(NAME, FUNC, TYPE) \
604
-void HELPER(NAME)(void *vd, void *vn, void *vm, void *stat, uint32_t desc) \
605
+#define DO_MULADD(NAME, FUNC, TYPE) \
606
+void HELPER(NAME)(void *vd, void *vn, void *vm, \
607
+ float_status *stat, uint32_t desc) \
608
{ \
609
intptr_t i, oprsz = simd_oprsz(desc); \
610
TYPE *d = vd, *n = vn, *m = vm; \
611
@@ -XXX,XX +XXX,XX @@ DO_MLA_IDX(gvec_mls_idx_d, uint64_t, -, H8)
612
#undef DO_MLA_IDX
613
614
#define DO_FMUL_IDX(NAME, ADD, MUL, TYPE, H) \
615
-void HELPER(NAME)(void *vd, void *vn, void *vm, void *stat, uint32_t desc) \
616
+void HELPER(NAME)(void *vd, void *vn, void *vm, \
617
+ float_status *stat, uint32_t desc) \
618
{ \
619
intptr_t i, j, oprsz = simd_oprsz(desc); \
620
intptr_t segment = MIN(16, oprsz) / sizeof(TYPE); \
621
@@ -XXX,XX +XXX,XX @@ DO_FMUL_IDX(gvec_fmls_nf_idx_s, float32_sub, float32_mul, float32, H4)
622
623
#define DO_FMLA_IDX(NAME, TYPE, H) \
624
void HELPER(NAME)(void *vd, void *vn, void *vm, void *va, \
625
- void *stat, uint32_t desc) \
626
+ float_status *stat, uint32_t desc) \
627
{ \
628
intptr_t i, j, oprsz = simd_oprsz(desc); \
629
intptr_t segment = MIN(16, oprsz) / sizeof(TYPE); \
630
@@ -XXX,XX +XXX,XX @@ DO_ABA(gvec_uaba_d, uint64_t)
631
#undef DO_ABA
632
633
#define DO_3OP_PAIR(NAME, FUNC, TYPE, H) \
634
-void HELPER(NAME)(void *vd, void *vn, void *vm, void *stat, uint32_t desc) \
635
+void HELPER(NAME)(void *vd, void *vn, void *vm, \
636
+ float_status *stat, uint32_t desc) \
637
{ \
638
ARMVectorReg scratch; \
639
intptr_t oprsz = simd_oprsz(desc); \
640
@@ -XXX,XX +XXX,XX @@ DO_3OP_PAIR(gvec_uminp_s, MIN, uint32_t, H4)
641
#undef DO_3OP_PAIR
642
643
#define DO_VCVT_FIXED(NAME, FUNC, TYPE) \
644
- void HELPER(NAME)(void *vd, void *vn, void *stat, uint32_t desc) \
645
+ void HELPER(NAME)(void *vd, void *vn, float_status *stat, uint32_t desc) \
646
{ \
647
intptr_t i, oprsz = simd_oprsz(desc); \
648
int shift = simd_data(desc); \
649
@@ -XXX,XX +XXX,XX @@ DO_VCVT_FIXED(gvec_vcvt_rz_hu, helper_vfp_touhh_round_to_zero, uint16_t)
650
#undef DO_VCVT_FIXED
651
652
#define DO_VCVT_RMODE(NAME, FUNC, TYPE) \
653
- void HELPER(NAME)(void *vd, void *vn, void *stat, uint32_t desc) \
654
+ void HELPER(NAME)(void *vd, void *vn, float_status *fpst, uint32_t desc) \
655
{ \
656
- float_status *fpst = stat; \
657
intptr_t i, oprsz = simd_oprsz(desc); \
658
uint32_t rmode = simd_data(desc); \
659
uint32_t prev_rmode = get_float_rounding_mode(fpst); \
660
@@ -XXX,XX +XXX,XX @@ DO_VCVT_RMODE(gvec_vcvt_rm_uh, helper_vfp_touhh, uint16_t)
661
#undef DO_VCVT_RMODE
662
663
#define DO_VRINT_RMODE(NAME, FUNC, TYPE) \
664
- void HELPER(NAME)(void *vd, void *vn, void *stat, uint32_t desc) \
665
+ void HELPER(NAME)(void *vd, void *vn, float_status *fpst, uint32_t desc) \
666
{ \
667
- float_status *fpst = stat; \
668
intptr_t i, oprsz = simd_oprsz(desc); \
669
uint32_t rmode = simd_data(desc); \
670
uint32_t prev_rmode = get_float_rounding_mode(fpst); \
671
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_bfmmla)(void *vd, void *vn, void *vm, void *va,
672
}
673
674
void HELPER(gvec_bfmlal)(void *vd, void *vn, void *vm, void *va,
675
- void *stat, uint32_t desc)
676
+ float_status *stat, uint32_t desc)
677
{
678
intptr_t i, opr_sz = simd_oprsz(desc);
679
intptr_t sel = simd_data(desc);
680
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_bfmlal)(void *vd, void *vn, void *vm, void *va,
681
}
682
683
void HELPER(gvec_bfmlal_idx)(void *vd, void *vn, void *vm,
684
- void *va, void *stat, uint32_t desc)
685
+ void *va, float_status *stat, uint32_t desc)
686
{
687
intptr_t i, j, opr_sz = simd_oprsz(desc);
688
intptr_t sel = extract32(desc, SIMD_DATA_SHIFT, 1);
689
--
690
2.34.1
691
692
diff view generated by jsdifflib
New patch
[PULL 05/19] target/arm: Convert neon_helper.c to fpst alias
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
Message-id: 20241206031224.78525-6-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/helper.h | 14 +++++++-------
9
target/arm/tcg/neon_helper.c | 21 +++++++--------------
10
2 files changed, 14 insertions(+), 21 deletions(-)
11
12
diff --git a/target/arm/helper.h b/target/arm/helper.h
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/helper.h
15
+++ b/target/arm/helper.h
16
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(neon_qneg_s16, TCG_CALL_NO_RWG, i32, env, i32)
17
DEF_HELPER_FLAGS_2(neon_qneg_s32, TCG_CALL_NO_RWG, i32, env, i32)
18
DEF_HELPER_FLAGS_2(neon_qneg_s64, TCG_CALL_NO_RWG, i64, env, i64)
19
20
-DEF_HELPER_3(neon_ceq_f32, i32, i32, i32, ptr)
21
-DEF_HELPER_3(neon_cge_f32, i32, i32, i32, ptr)
22
-DEF_HELPER_3(neon_cgt_f32, i32, i32, i32, ptr)
23
-DEF_HELPER_3(neon_acge_f32, i32, i32, i32, ptr)
24
-DEF_HELPER_3(neon_acgt_f32, i32, i32, i32, ptr)
25
-DEF_HELPER_3(neon_acge_f64, i64, i64, i64, ptr)
26
-DEF_HELPER_3(neon_acgt_f64, i64, i64, i64, ptr)
27
+DEF_HELPER_3(neon_ceq_f32, i32, i32, i32, fpst)
28
+DEF_HELPER_3(neon_cge_f32, i32, i32, i32, fpst)
29
+DEF_HELPER_3(neon_cgt_f32, i32, i32, i32, fpst)
30
+DEF_HELPER_3(neon_acge_f32, i32, i32, i32, fpst)
31
+DEF_HELPER_3(neon_acgt_f32, i32, i32, i32, fpst)
32
+DEF_HELPER_3(neon_acge_f64, i64, i64, i64, fpst)
33
+DEF_HELPER_3(neon_acgt_f64, i64, i64, i64, fpst)
34
35
/* iwmmxt_helper.c */
36
DEF_HELPER_2(iwmmxt_maddsq, i64, i64, i64)
37
diff --git a/target/arm/tcg/neon_helper.c b/target/arm/tcg/neon_helper.c
38
index XXXXXXX..XXXXXXX 100644
39
--- a/target/arm/tcg/neon_helper.c
40
+++ b/target/arm/tcg/neon_helper.c
41
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(neon_qneg_s64)(CPUARMState *env, uint64_t x)
42
* Note that EQ doesn't signal InvalidOp for QNaNs but GE and GT do.
43
* Softfloat routines return 0/1, which we convert to the 0/-1 Neon requires.
44
*/
45
-uint32_t HELPER(neon_ceq_f32)(uint32_t a, uint32_t b, void *fpstp)
46
+uint32_t HELPER(neon_ceq_f32)(uint32_t a, uint32_t b, float_status *fpst)
47
{
48
- float_status *fpst = fpstp;
49
return -float32_eq_quiet(make_float32(a), make_float32(b), fpst);
50
}
51
52
-uint32_t HELPER(neon_cge_f32)(uint32_t a, uint32_t b, void *fpstp)
53
+uint32_t HELPER(neon_cge_f32)(uint32_t a, uint32_t b, float_status *fpst)
54
{
55
- float_status *fpst = fpstp;
56
return -float32_le(make_float32(b), make_float32(a), fpst);
57
}
58
59
-uint32_t HELPER(neon_cgt_f32)(uint32_t a, uint32_t b, void *fpstp)
60
+uint32_t HELPER(neon_cgt_f32)(uint32_t a, uint32_t b, float_status *fpst)
61
{
62
- float_status *fpst = fpstp;
63
return -float32_lt(make_float32(b), make_float32(a), fpst);
64
}
65
66
-uint32_t HELPER(neon_acge_f32)(uint32_t a, uint32_t b, void *fpstp)
67
+uint32_t HELPER(neon_acge_f32)(uint32_t a, uint32_t b, float_status *fpst)
68
{
69
- float_status *fpst = fpstp;
70
float32 f0 = float32_abs(make_float32(a));
71
float32 f1 = float32_abs(make_float32(b));
72
return -float32_le(f1, f0, fpst);
73
}
74
75
-uint32_t HELPER(neon_acgt_f32)(uint32_t a, uint32_t b, void *fpstp)
76
+uint32_t HELPER(neon_acgt_f32)(uint32_t a, uint32_t b, float_status *fpst)
77
{
78
- float_status *fpst = fpstp;
79
float32 f0 = float32_abs(make_float32(a));
80
float32 f1 = float32_abs(make_float32(b));
81
return -float32_lt(f1, f0, fpst);
82
}
83
84
-uint64_t HELPER(neon_acge_f64)(uint64_t a, uint64_t b, void *fpstp)
85
+uint64_t HELPER(neon_acge_f64)(uint64_t a, uint64_t b, float_status *fpst)
86
{
87
- float_status *fpst = fpstp;
88
float64 f0 = float64_abs(make_float64(a));
89
float64 f1 = float64_abs(make_float64(b));
90
return -float64_le(f1, f0, fpst);
91
}
92
93
-uint64_t HELPER(neon_acgt_f64)(uint64_t a, uint64_t b, void *fpstp)
94
+uint64_t HELPER(neon_acgt_f64)(uint64_t a, uint64_t b, float_status *fpst)
95
{
96
- float_status *fpst = fpstp;
97
float64 f0 = float64_abs(make_float64(a));
98
float64 f1 = float64_abs(make_float64(b));
99
return -float64_lt(f1, f0, fpst);
100
--
101
2.34.1
102
103
diff view generated by jsdifflib
[PULL 01/12] hw/arm/virt: fix PMU IRQ registration
[PULL 06/19] target/arm: Convert sve_helper.c to fpst alias
1
From: Sebastian Ott <sebott@redhat.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Since commit 9036e917f8 ("{include/}hw/arm: refactor virt PPI logic")
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
PMU IRQ registration fails for arm64 guests:
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
5
Message-id: 20241206031224.78525-7-richard.henderson@linaro.org
6
[ 0.563689] hw perfevents: unable to request IRQ14 for ARM PMU counters
7
[ 0.565160] armv8-pmu: probe of pmu failed with error -22
8
9
That commit re-defined VIRTUAL_PMU_IRQ to be a INTID but missed a case
10
where the PMU IRQ is actually referred by its PPI index. Fix that by using
11
INTID_TO_PPI() in that case.
12
13
Fixes: 9036e917f8 ("{include/}hw/arm: refactor virt PPI logic")
14
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1960
15
Signed-off-by: Sebastian Ott <sebott@redhat.com>
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
Message-id: 475d918d-ab0e-f717-7206-57a5beb28c7b@redhat.com
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
---
7
---
20
hw/arm/virt.c | 3 ++-
8
target/arm/tcg/helper-sve.h | 414 ++++++++++++++++++------------------
21
1 file changed, 2 insertions(+), 1 deletion(-)
9
target/arm/tcg/sve_helper.c | 96 +++++----
10
2 files changed, 258 insertions(+), 252 deletions(-)
22
11
23
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
12
diff --git a/target/arm/tcg/helper-sve.h b/target/arm/tcg/helper-sve.h
24
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
25
--- a/hw/arm/virt.c
14
--- a/target/arm/tcg/helper-sve.h
26
+++ b/hw/arm/virt.c
15
+++ b/target/arm/tcg/helper-sve.h
27
@@ -XXX,XX +XXX,XX @@ static void fdt_add_pmu_nodes(const VirtMachineState *vms)
16
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(gvec_rsqrts_d, TCG_CALL_NO_RWG,
28
qemu_fdt_setprop(ms->fdt, "/pmu", "compatible",
17
void, ptr, ptr, ptr, fpst, i32)
29
compat, sizeof(compat));
18
30
qemu_fdt_setprop_cells(ms->fdt, "/pmu", "interrupts",
19
DEF_HELPER_FLAGS_4(sve_faddv_h, TCG_CALL_NO_RWG,
31
- GIC_FDT_IRQ_TYPE_PPI, VIRTUAL_PMU_IRQ, irqflags);
20
- i64, ptr, ptr, ptr, i32)
32
+ GIC_FDT_IRQ_TYPE_PPI,
21
+ i64, ptr, ptr, fpst, i32)
33
+ INTID_TO_PPI(VIRTUAL_PMU_IRQ), irqflags);
22
DEF_HELPER_FLAGS_4(sve_faddv_s, TCG_CALL_NO_RWG,
23
- i64, ptr, ptr, ptr, i32)
24
+ i64, ptr, ptr, fpst, i32)
25
DEF_HELPER_FLAGS_4(sve_faddv_d, TCG_CALL_NO_RWG,
26
- i64, ptr, ptr, ptr, i32)
27
+ i64, ptr, ptr, fpst, i32)
28
29
DEF_HELPER_FLAGS_4(sve_fmaxnmv_h, TCG_CALL_NO_RWG,
30
- i64, ptr, ptr, ptr, i32)
31
+ i64, ptr, ptr, fpst, i32)
32
DEF_HELPER_FLAGS_4(sve_fmaxnmv_s, TCG_CALL_NO_RWG,
33
- i64, ptr, ptr, ptr, i32)
34
+ i64, ptr, ptr, fpst, i32)
35
DEF_HELPER_FLAGS_4(sve_fmaxnmv_d, TCG_CALL_NO_RWG,
36
- i64, ptr, ptr, ptr, i32)
37
+ i64, ptr, ptr, fpst, i32)
38
39
DEF_HELPER_FLAGS_4(sve_fminnmv_h, TCG_CALL_NO_RWG,
40
- i64, ptr, ptr, ptr, i32)
41
+ i64, ptr, ptr, fpst, i32)
42
DEF_HELPER_FLAGS_4(sve_fminnmv_s, TCG_CALL_NO_RWG,
43
- i64, ptr, ptr, ptr, i32)
44
+ i64, ptr, ptr, fpst, i32)
45
DEF_HELPER_FLAGS_4(sve_fminnmv_d, TCG_CALL_NO_RWG,
46
- i64, ptr, ptr, ptr, i32)
47
+ i64, ptr, ptr, fpst, i32)
48
49
DEF_HELPER_FLAGS_4(sve_fmaxv_h, TCG_CALL_NO_RWG,
50
- i64, ptr, ptr, ptr, i32)
51
+ i64, ptr, ptr, fpst, i32)
52
DEF_HELPER_FLAGS_4(sve_fmaxv_s, TCG_CALL_NO_RWG,
53
- i64, ptr, ptr, ptr, i32)
54
+ i64, ptr, ptr, fpst, i32)
55
DEF_HELPER_FLAGS_4(sve_fmaxv_d, TCG_CALL_NO_RWG,
56
- i64, ptr, ptr, ptr, i32)
57
+ i64, ptr, ptr, fpst, i32)
58
59
DEF_HELPER_FLAGS_4(sve_fminv_h, TCG_CALL_NO_RWG,
60
- i64, ptr, ptr, ptr, i32)
61
+ i64, ptr, ptr, fpst, i32)
62
DEF_HELPER_FLAGS_4(sve_fminv_s, TCG_CALL_NO_RWG,
63
- i64, ptr, ptr, ptr, i32)
64
+ i64, ptr, ptr, fpst, i32)
65
DEF_HELPER_FLAGS_4(sve_fminv_d, TCG_CALL_NO_RWG,
66
- i64, ptr, ptr, ptr, i32)
67
+ i64, ptr, ptr, fpst, i32)
68
69
DEF_HELPER_FLAGS_5(sve_fadda_h, TCG_CALL_NO_RWG,
70
- i64, i64, ptr, ptr, ptr, i32)
71
+ i64, i64, ptr, ptr, fpst, i32)
72
DEF_HELPER_FLAGS_5(sve_fadda_s, TCG_CALL_NO_RWG,
73
- i64, i64, ptr, ptr, ptr, i32)
74
+ i64, i64, ptr, ptr, fpst, i32)
75
DEF_HELPER_FLAGS_5(sve_fadda_d, TCG_CALL_NO_RWG,
76
- i64, i64, ptr, ptr, ptr, i32)
77
+ i64, i64, ptr, ptr, fpst, i32)
78
79
DEF_HELPER_FLAGS_5(sve_fcmge0_h, TCG_CALL_NO_RWG,
80
- void, ptr, ptr, ptr, ptr, i32)
81
+ void, ptr, ptr, ptr, fpst, i32)
82
DEF_HELPER_FLAGS_5(sve_fcmge0_s, TCG_CALL_NO_RWG,
83
- void, ptr, ptr, ptr, ptr, i32)
84
+ void, ptr, ptr, ptr, fpst, i32)
85
DEF_HELPER_FLAGS_5(sve_fcmge0_d, TCG_CALL_NO_RWG,
86
- void, ptr, ptr, ptr, ptr, i32)
87
+ void, ptr, ptr, ptr, fpst, i32)
88
89
DEF_HELPER_FLAGS_5(sve_fcmgt0_h, TCG_CALL_NO_RWG,
90
- void, ptr, ptr, ptr, ptr, i32)
91
+ void, ptr, ptr, ptr, fpst, i32)
92
DEF_HELPER_FLAGS_5(sve_fcmgt0_s, TCG_CALL_NO_RWG,
93
- void, ptr, ptr, ptr, ptr, i32)
94
+ void, ptr, ptr, ptr, fpst, i32)
95
DEF_HELPER_FLAGS_5(sve_fcmgt0_d, TCG_CALL_NO_RWG,
96
- void, ptr, ptr, ptr, ptr, i32)
97
+ void, ptr, ptr, ptr, fpst, i32)
98
99
DEF_HELPER_FLAGS_5(sve_fcmlt0_h, TCG_CALL_NO_RWG,
100
- void, ptr, ptr, ptr, ptr, i32)
101
+ void, ptr, ptr, ptr, fpst, i32)
102
DEF_HELPER_FLAGS_5(sve_fcmlt0_s, TCG_CALL_NO_RWG,
103
- void, ptr, ptr, ptr, ptr, i32)
104
+ void, ptr, ptr, ptr, fpst, i32)
105
DEF_HELPER_FLAGS_5(sve_fcmlt0_d, TCG_CALL_NO_RWG,
106
- void, ptr, ptr, ptr, ptr, i32)
107
+ void, ptr, ptr, ptr, fpst, i32)
108
109
DEF_HELPER_FLAGS_5(sve_fcmle0_h, TCG_CALL_NO_RWG,
110
- void, ptr, ptr, ptr, ptr, i32)
111
+ void, ptr, ptr, ptr, fpst, i32)
112
DEF_HELPER_FLAGS_5(sve_fcmle0_s, TCG_CALL_NO_RWG,
113
- void, ptr, ptr, ptr, ptr, i32)
114
+ void, ptr, ptr, ptr, fpst, i32)
115
DEF_HELPER_FLAGS_5(sve_fcmle0_d, TCG_CALL_NO_RWG,
116
- void, ptr, ptr, ptr, ptr, i32)
117
+ void, ptr, ptr, ptr, fpst, i32)
118
119
DEF_HELPER_FLAGS_5(sve_fcmeq0_h, TCG_CALL_NO_RWG,
120
- void, ptr, ptr, ptr, ptr, i32)
121
+ void, ptr, ptr, ptr, fpst, i32)
122
DEF_HELPER_FLAGS_5(sve_fcmeq0_s, TCG_CALL_NO_RWG,
123
- void, ptr, ptr, ptr, ptr, i32)
124
+ void, ptr, ptr, ptr, fpst, i32)
125
DEF_HELPER_FLAGS_5(sve_fcmeq0_d, TCG_CALL_NO_RWG,
126
- void, ptr, ptr, ptr, ptr, i32)
127
+ void, ptr, ptr, ptr, fpst, i32)
128
129
DEF_HELPER_FLAGS_5(sve_fcmne0_h, TCG_CALL_NO_RWG,
130
- void, ptr, ptr, ptr, ptr, i32)
131
+ void, ptr, ptr, ptr, fpst, i32)
132
DEF_HELPER_FLAGS_5(sve_fcmne0_s, TCG_CALL_NO_RWG,
133
- void, ptr, ptr, ptr, ptr, i32)
134
+ void, ptr, ptr, ptr, fpst, i32)
135
DEF_HELPER_FLAGS_5(sve_fcmne0_d, TCG_CALL_NO_RWG,
136
- void, ptr, ptr, ptr, ptr, i32)
137
+ void, ptr, ptr, ptr, fpst, i32)
138
139
DEF_HELPER_FLAGS_6(sve_fadd_h, TCG_CALL_NO_RWG,
140
- void, ptr, ptr, ptr, ptr, ptr, i32)
141
+ void, ptr, ptr, ptr, ptr, fpst, i32)
142
DEF_HELPER_FLAGS_6(sve_fadd_s, TCG_CALL_NO_RWG,
143
- void, ptr, ptr, ptr, ptr, ptr, i32)
144
+ void, ptr, ptr, ptr, ptr, fpst, i32)
145
DEF_HELPER_FLAGS_6(sve_fadd_d, TCG_CALL_NO_RWG,
146
- void, ptr, ptr, ptr, ptr, ptr, i32)
147
+ void, ptr, ptr, ptr, ptr, fpst, i32)
148
149
DEF_HELPER_FLAGS_6(sve_fsub_h, TCG_CALL_NO_RWG,
150
- void, ptr, ptr, ptr, ptr, ptr, i32)
151
+ void, ptr, ptr, ptr, ptr, fpst, i32)
152
DEF_HELPER_FLAGS_6(sve_fsub_s, TCG_CALL_NO_RWG,
153
- void, ptr, ptr, ptr, ptr, ptr, i32)
154
+ void, ptr, ptr, ptr, ptr, fpst, i32)
155
DEF_HELPER_FLAGS_6(sve_fsub_d, TCG_CALL_NO_RWG,
156
- void, ptr, ptr, ptr, ptr, ptr, i32)
157
+ void, ptr, ptr, ptr, ptr, fpst, i32)
158
159
DEF_HELPER_FLAGS_6(sve_fmul_h, TCG_CALL_NO_RWG,
160
- void, ptr, ptr, ptr, ptr, ptr, i32)
161
+ void, ptr, ptr, ptr, ptr, fpst, i32)
162
DEF_HELPER_FLAGS_6(sve_fmul_s, TCG_CALL_NO_RWG,
163
- void, ptr, ptr, ptr, ptr, ptr, i32)
164
+ void, ptr, ptr, ptr, ptr, fpst, i32)
165
DEF_HELPER_FLAGS_6(sve_fmul_d, TCG_CALL_NO_RWG,
166
- void, ptr, ptr, ptr, ptr, ptr, i32)
167
+ void, ptr, ptr, ptr, ptr, fpst, i32)
168
169
DEF_HELPER_FLAGS_6(sve_fdiv_h, TCG_CALL_NO_RWG,
170
- void, ptr, ptr, ptr, ptr, ptr, i32)
171
+ void, ptr, ptr, ptr, ptr, fpst, i32)
172
DEF_HELPER_FLAGS_6(sve_fdiv_s, TCG_CALL_NO_RWG,
173
- void, ptr, ptr, ptr, ptr, ptr, i32)
174
+ void, ptr, ptr, ptr, ptr, fpst, i32)
175
DEF_HELPER_FLAGS_6(sve_fdiv_d, TCG_CALL_NO_RWG,
176
- void, ptr, ptr, ptr, ptr, ptr, i32)
177
+ void, ptr, ptr, ptr, ptr, fpst, i32)
178
179
DEF_HELPER_FLAGS_6(sve_fmin_h, TCG_CALL_NO_RWG,
180
- void, ptr, ptr, ptr, ptr, ptr, i32)
181
+ void, ptr, ptr, ptr, ptr, fpst, i32)
182
DEF_HELPER_FLAGS_6(sve_fmin_s, TCG_CALL_NO_RWG,
183
- void, ptr, ptr, ptr, ptr, ptr, i32)
184
+ void, ptr, ptr, ptr, ptr, fpst, i32)
185
DEF_HELPER_FLAGS_6(sve_fmin_d, TCG_CALL_NO_RWG,
186
- void, ptr, ptr, ptr, ptr, ptr, i32)
187
+ void, ptr, ptr, ptr, ptr, fpst, i32)
188
189
DEF_HELPER_FLAGS_6(sve_fmax_h, TCG_CALL_NO_RWG,
190
- void, ptr, ptr, ptr, ptr, ptr, i32)
191
+ void, ptr, ptr, ptr, ptr, fpst, i32)
192
DEF_HELPER_FLAGS_6(sve_fmax_s, TCG_CALL_NO_RWG,
193
- void, ptr, ptr, ptr, ptr, ptr, i32)
194
+ void, ptr, ptr, ptr, ptr, fpst, i32)
195
DEF_HELPER_FLAGS_6(sve_fmax_d, TCG_CALL_NO_RWG,
196
- void, ptr, ptr, ptr, ptr, ptr, i32)
197
+ void, ptr, ptr, ptr, ptr, fpst, i32)
198
199
DEF_HELPER_FLAGS_6(sve_fminnum_h, TCG_CALL_NO_RWG,
200
- void, ptr, ptr, ptr, ptr, ptr, i32)
201
+ void, ptr, ptr, ptr, ptr, fpst, i32)
202
DEF_HELPER_FLAGS_6(sve_fminnum_s, TCG_CALL_NO_RWG,
203
- void, ptr, ptr, ptr, ptr, ptr, i32)
204
+ void, ptr, ptr, ptr, ptr, fpst, i32)
205
DEF_HELPER_FLAGS_6(sve_fminnum_d, TCG_CALL_NO_RWG,
206
- void, ptr, ptr, ptr, ptr, ptr, i32)
207
+ void, ptr, ptr, ptr, ptr, fpst, i32)
208
209
DEF_HELPER_FLAGS_6(sve_fmaxnum_h, TCG_CALL_NO_RWG,
210
- void, ptr, ptr, ptr, ptr, ptr, i32)
211
+ void, ptr, ptr, ptr, ptr, fpst, i32)
212
DEF_HELPER_FLAGS_6(sve_fmaxnum_s, TCG_CALL_NO_RWG,
213
- void, ptr, ptr, ptr, ptr, ptr, i32)
214
+ void, ptr, ptr, ptr, ptr, fpst, i32)
215
DEF_HELPER_FLAGS_6(sve_fmaxnum_d, TCG_CALL_NO_RWG,
216
- void, ptr, ptr, ptr, ptr, ptr, i32)
217
+ void, ptr, ptr, ptr, ptr, fpst, i32)
218
219
DEF_HELPER_FLAGS_6(sve_fabd_h, TCG_CALL_NO_RWG,
220
- void, ptr, ptr, ptr, ptr, ptr, i32)
221
+ void, ptr, ptr, ptr, ptr, fpst, i32)
222
DEF_HELPER_FLAGS_6(sve_fabd_s, TCG_CALL_NO_RWG,
223
- void, ptr, ptr, ptr, ptr, ptr, i32)
224
+ void, ptr, ptr, ptr, ptr, fpst, i32)
225
DEF_HELPER_FLAGS_6(sve_fabd_d, TCG_CALL_NO_RWG,
226
- void, ptr, ptr, ptr, ptr, ptr, i32)
227
+ void, ptr, ptr, ptr, ptr, fpst, i32)
228
229
DEF_HELPER_FLAGS_6(sve_fscalbn_h, TCG_CALL_NO_RWG,
230
- void, ptr, ptr, ptr, ptr, ptr, i32)
231
+ void, ptr, ptr, ptr, ptr, fpst, i32)
232
DEF_HELPER_FLAGS_6(sve_fscalbn_s, TCG_CALL_NO_RWG,
233
- void, ptr, ptr, ptr, ptr, ptr, i32)
234
+ void, ptr, ptr, ptr, ptr, fpst, i32)
235
DEF_HELPER_FLAGS_6(sve_fscalbn_d, TCG_CALL_NO_RWG,
236
- void, ptr, ptr, ptr, ptr, ptr, i32)
237
+ void, ptr, ptr, ptr, ptr, fpst, i32)
238
239
DEF_HELPER_FLAGS_6(sve_fmulx_h, TCG_CALL_NO_RWG,
240
- void, ptr, ptr, ptr, ptr, ptr, i32)
241
+ void, ptr, ptr, ptr, ptr, fpst, i32)
242
DEF_HELPER_FLAGS_6(sve_fmulx_s, TCG_CALL_NO_RWG,
243
- void, ptr, ptr, ptr, ptr, ptr, i32)
244
+ void, ptr, ptr, ptr, ptr, fpst, i32)
245
DEF_HELPER_FLAGS_6(sve_fmulx_d, TCG_CALL_NO_RWG,
246
- void, ptr, ptr, ptr, ptr, ptr, i32)
247
+ void, ptr, ptr, ptr, ptr, fpst, i32)
248
249
DEF_HELPER_FLAGS_6(sve_fadds_h, TCG_CALL_NO_RWG,
250
- void, ptr, ptr, ptr, i64, ptr, i32)
251
+ void, ptr, ptr, ptr, i64, fpst, i32)
252
DEF_HELPER_FLAGS_6(sve_fadds_s, TCG_CALL_NO_RWG,
253
- void, ptr, ptr, ptr, i64, ptr, i32)
254
+ void, ptr, ptr, ptr, i64, fpst, i32)
255
DEF_HELPER_FLAGS_6(sve_fadds_d, TCG_CALL_NO_RWG,
256
- void, ptr, ptr, ptr, i64, ptr, i32)
257
+ void, ptr, ptr, ptr, i64, fpst, i32)
258
259
DEF_HELPER_FLAGS_6(sve_fsubs_h, TCG_CALL_NO_RWG,
260
- void, ptr, ptr, ptr, i64, ptr, i32)
261
+ void, ptr, ptr, ptr, i64, fpst, i32)
262
DEF_HELPER_FLAGS_6(sve_fsubs_s, TCG_CALL_NO_RWG,
263
- void, ptr, ptr, ptr, i64, ptr, i32)
264
+ void, ptr, ptr, ptr, i64, fpst, i32)
265
DEF_HELPER_FLAGS_6(sve_fsubs_d, TCG_CALL_NO_RWG,
266
- void, ptr, ptr, ptr, i64, ptr, i32)
267
+ void, ptr, ptr, ptr, i64, fpst, i32)
268
269
DEF_HELPER_FLAGS_6(sve_fmuls_h, TCG_CALL_NO_RWG,
270
- void, ptr, ptr, ptr, i64, ptr, i32)
271
+ void, ptr, ptr, ptr, i64, fpst, i32)
272
DEF_HELPER_FLAGS_6(sve_fmuls_s, TCG_CALL_NO_RWG,
273
- void, ptr, ptr, ptr, i64, ptr, i32)
274
+ void, ptr, ptr, ptr, i64, fpst, i32)
275
DEF_HELPER_FLAGS_6(sve_fmuls_d, TCG_CALL_NO_RWG,
276
- void, ptr, ptr, ptr, i64, ptr, i32)
277
+ void, ptr, ptr, ptr, i64, fpst, i32)
278
279
DEF_HELPER_FLAGS_6(sve_fsubrs_h, TCG_CALL_NO_RWG,
280
- void, ptr, ptr, ptr, i64, ptr, i32)
281
+ void, ptr, ptr, ptr, i64, fpst, i32)
282
DEF_HELPER_FLAGS_6(sve_fsubrs_s, TCG_CALL_NO_RWG,
283
- void, ptr, ptr, ptr, i64, ptr, i32)
284
+ void, ptr, ptr, ptr, i64, fpst, i32)
285
DEF_HELPER_FLAGS_6(sve_fsubrs_d, TCG_CALL_NO_RWG,
286
- void, ptr, ptr, ptr, i64, ptr, i32)
287
+ void, ptr, ptr, ptr, i64, fpst, i32)
288
289
DEF_HELPER_FLAGS_6(sve_fmaxnms_h, TCG_CALL_NO_RWG,
290
- void, ptr, ptr, ptr, i64, ptr, i32)
291
+ void, ptr, ptr, ptr, i64, fpst, i32)
292
DEF_HELPER_FLAGS_6(sve_fmaxnms_s, TCG_CALL_NO_RWG,
293
- void, ptr, ptr, ptr, i64, ptr, i32)
294
+ void, ptr, ptr, ptr, i64, fpst, i32)
295
DEF_HELPER_FLAGS_6(sve_fmaxnms_d, TCG_CALL_NO_RWG,
296
- void, ptr, ptr, ptr, i64, ptr, i32)
297
+ void, ptr, ptr, ptr, i64, fpst, i32)
298
299
DEF_HELPER_FLAGS_6(sve_fminnms_h, TCG_CALL_NO_RWG,
300
- void, ptr, ptr, ptr, i64, ptr, i32)
301
+ void, ptr, ptr, ptr, i64, fpst, i32)
302
DEF_HELPER_FLAGS_6(sve_fminnms_s, TCG_CALL_NO_RWG,
303
- void, ptr, ptr, ptr, i64, ptr, i32)
304
+ void, ptr, ptr, ptr, i64, fpst, i32)
305
DEF_HELPER_FLAGS_6(sve_fminnms_d, TCG_CALL_NO_RWG,
306
- void, ptr, ptr, ptr, i64, ptr, i32)
307
+ void, ptr, ptr, ptr, i64, fpst, i32)
308
309
DEF_HELPER_FLAGS_6(sve_fmaxs_h, TCG_CALL_NO_RWG,
310
- void, ptr, ptr, ptr, i64, ptr, i32)
311
+ void, ptr, ptr, ptr, i64, fpst, i32)
312
DEF_HELPER_FLAGS_6(sve_fmaxs_s, TCG_CALL_NO_RWG,
313
- void, ptr, ptr, ptr, i64, ptr, i32)
314
+ void, ptr, ptr, ptr, i64, fpst, i32)
315
DEF_HELPER_FLAGS_6(sve_fmaxs_d, TCG_CALL_NO_RWG,
316
- void, ptr, ptr, ptr, i64, ptr, i32)
317
+ void, ptr, ptr, ptr, i64, fpst, i32)
318
319
DEF_HELPER_FLAGS_6(sve_fmins_h, TCG_CALL_NO_RWG,
320
- void, ptr, ptr, ptr, i64, ptr, i32)
321
+ void, ptr, ptr, ptr, i64, fpst, i32)
322
DEF_HELPER_FLAGS_6(sve_fmins_s, TCG_CALL_NO_RWG,
323
- void, ptr, ptr, ptr, i64, ptr, i32)
324
+ void, ptr, ptr, ptr, i64, fpst, i32)
325
DEF_HELPER_FLAGS_6(sve_fmins_d, TCG_CALL_NO_RWG,
326
- void, ptr, ptr, ptr, i64, ptr, i32)
327
+ void, ptr, ptr, ptr, i64, fpst, i32)
328
329
DEF_HELPER_FLAGS_5(sve_fcvt_sh, TCG_CALL_NO_RWG,
330
- void, ptr, ptr, ptr, ptr, i32)
331
+ void, ptr, ptr, ptr, fpst, i32)
332
DEF_HELPER_FLAGS_5(sve_fcvt_dh, TCG_CALL_NO_RWG,
333
- void, ptr, ptr, ptr, ptr, i32)
334
+ void, ptr, ptr, ptr, fpst, i32)
335
DEF_HELPER_FLAGS_5(sve_fcvt_hs, TCG_CALL_NO_RWG,
336
- void, ptr, ptr, ptr, ptr, i32)
337
+ void, ptr, ptr, ptr, fpst, i32)
338
DEF_HELPER_FLAGS_5(sve_fcvt_ds, TCG_CALL_NO_RWG,
339
- void, ptr, ptr, ptr, ptr, i32)
340
+ void, ptr, ptr, ptr, fpst, i32)
341
DEF_HELPER_FLAGS_5(sve_fcvt_hd, TCG_CALL_NO_RWG,
342
- void, ptr, ptr, ptr, ptr, i32)
343
+ void, ptr, ptr, ptr, fpst, i32)
344
DEF_HELPER_FLAGS_5(sve_fcvt_sd, TCG_CALL_NO_RWG,
345
- void, ptr, ptr, ptr, ptr, i32)
346
+ void, ptr, ptr, ptr, fpst, i32)
347
DEF_HELPER_FLAGS_5(sve_bfcvt, TCG_CALL_NO_RWG,
348
- void, ptr, ptr, ptr, ptr, i32)
349
+ void, ptr, ptr, ptr, fpst, i32)
350
351
DEF_HELPER_FLAGS_5(sve_fcvtzs_hh, TCG_CALL_NO_RWG,
352
- void, ptr, ptr, ptr, ptr, i32)
353
+ void, ptr, ptr, ptr, fpst, i32)
354
DEF_HELPER_FLAGS_5(sve_fcvtzs_hs, TCG_CALL_NO_RWG,
355
- void, ptr, ptr, ptr, ptr, i32)
356
+ void, ptr, ptr, ptr, fpst, i32)
357
DEF_HELPER_FLAGS_5(sve_fcvtzs_ss, TCG_CALL_NO_RWG,
358
- void, ptr, ptr, ptr, ptr, i32)
359
+ void, ptr, ptr, ptr, fpst, i32)
360
DEF_HELPER_FLAGS_5(sve_fcvtzs_ds, TCG_CALL_NO_RWG,
361
- void, ptr, ptr, ptr, ptr, i32)
362
+ void, ptr, ptr, ptr, fpst, i32)
363
DEF_HELPER_FLAGS_5(sve_fcvtzs_hd, TCG_CALL_NO_RWG,
364
- void, ptr, ptr, ptr, ptr, i32)
365
+ void, ptr, ptr, ptr, fpst, i32)
366
DEF_HELPER_FLAGS_5(sve_fcvtzs_sd, TCG_CALL_NO_RWG,
367
- void, ptr, ptr, ptr, ptr, i32)
368
+ void, ptr, ptr, ptr, fpst, i32)
369
DEF_HELPER_FLAGS_5(sve_fcvtzs_dd, TCG_CALL_NO_RWG,
370
- void, ptr, ptr, ptr, ptr, i32)
371
+ void, ptr, ptr, ptr, fpst, i32)
372
373
DEF_HELPER_FLAGS_5(sve_fcvtzu_hh, TCG_CALL_NO_RWG,
374
- void, ptr, ptr, ptr, ptr, i32)
375
+ void, ptr, ptr, ptr, fpst, i32)
376
DEF_HELPER_FLAGS_5(sve_fcvtzu_hs, TCG_CALL_NO_RWG,
377
- void, ptr, ptr, ptr, ptr, i32)
378
+ void, ptr, ptr, ptr, fpst, i32)
379
DEF_HELPER_FLAGS_5(sve_fcvtzu_ss, TCG_CALL_NO_RWG,
380
- void, ptr, ptr, ptr, ptr, i32)
381
+ void, ptr, ptr, ptr, fpst, i32)
382
DEF_HELPER_FLAGS_5(sve_fcvtzu_ds, TCG_CALL_NO_RWG,
383
- void, ptr, ptr, ptr, ptr, i32)
384
+ void, ptr, ptr, ptr, fpst, i32)
385
DEF_HELPER_FLAGS_5(sve_fcvtzu_hd, TCG_CALL_NO_RWG,
386
- void, ptr, ptr, ptr, ptr, i32)
387
+ void, ptr, ptr, ptr, fpst, i32)
388
DEF_HELPER_FLAGS_5(sve_fcvtzu_sd, TCG_CALL_NO_RWG,
389
- void, ptr, ptr, ptr, ptr, i32)
390
+ void, ptr, ptr, ptr, fpst, i32)
391
DEF_HELPER_FLAGS_5(sve_fcvtzu_dd, TCG_CALL_NO_RWG,
392
- void, ptr, ptr, ptr, ptr, i32)
393
+ void, ptr, ptr, ptr, fpst, i32)
394
395
DEF_HELPER_FLAGS_5(sve_frint_h, TCG_CALL_NO_RWG,
396
- void, ptr, ptr, ptr, ptr, i32)
397
+ void, ptr, ptr, ptr, fpst, i32)
398
DEF_HELPER_FLAGS_5(sve_frint_s, TCG_CALL_NO_RWG,
399
- void, ptr, ptr, ptr, ptr, i32)
400
+ void, ptr, ptr, ptr, fpst, i32)
401
DEF_HELPER_FLAGS_5(sve_frint_d, TCG_CALL_NO_RWG,
402
- void, ptr, ptr, ptr, ptr, i32)
403
+ void, ptr, ptr, ptr, fpst, i32)
404
405
DEF_HELPER_FLAGS_5(sve_frintx_h, TCG_CALL_NO_RWG,
406
- void, ptr, ptr, ptr, ptr, i32)
407
+ void, ptr, ptr, ptr, fpst, i32)
408
DEF_HELPER_FLAGS_5(sve_frintx_s, TCG_CALL_NO_RWG,
409
- void, ptr, ptr, ptr, ptr, i32)
410
+ void, ptr, ptr, ptr, fpst, i32)
411
DEF_HELPER_FLAGS_5(sve_frintx_d, TCG_CALL_NO_RWG,
412
- void, ptr, ptr, ptr, ptr, i32)
413
+ void, ptr, ptr, ptr, fpst, i32)
414
415
DEF_HELPER_FLAGS_5(sve_frecpx_h, TCG_CALL_NO_RWG,
416
- void, ptr, ptr, ptr, ptr, i32)
417
+ void, ptr, ptr, ptr, fpst, i32)
418
DEF_HELPER_FLAGS_5(sve_frecpx_s, TCG_CALL_NO_RWG,
419
- void, ptr, ptr, ptr, ptr, i32)
420
+ void, ptr, ptr, ptr, fpst, i32)
421
DEF_HELPER_FLAGS_5(sve_frecpx_d, TCG_CALL_NO_RWG,
422
- void, ptr, ptr, ptr, ptr, i32)
423
+ void, ptr, ptr, ptr, fpst, i32)
424
425
DEF_HELPER_FLAGS_5(sve_fsqrt_h, TCG_CALL_NO_RWG,
426
- void, ptr, ptr, ptr, ptr, i32)
427
+ void, ptr, ptr, ptr, fpst, i32)
428
DEF_HELPER_FLAGS_5(sve_fsqrt_s, TCG_CALL_NO_RWG,
429
- void, ptr, ptr, ptr, ptr, i32)
430
+ void, ptr, ptr, ptr, fpst, i32)
431
DEF_HELPER_FLAGS_5(sve_fsqrt_d, TCG_CALL_NO_RWG,
432
- void, ptr, ptr, ptr, ptr, i32)
433
+ void, ptr, ptr, ptr, fpst, i32)
434
435
DEF_HELPER_FLAGS_5(sve_scvt_hh, TCG_CALL_NO_RWG,
436
- void, ptr, ptr, ptr, ptr, i32)
437
+ void, ptr, ptr, ptr, fpst, i32)
438
DEF_HELPER_FLAGS_5(sve_scvt_sh, TCG_CALL_NO_RWG,
439
- void, ptr, ptr, ptr, ptr, i32)
440
+ void, ptr, ptr, ptr, fpst, i32)
441
DEF_HELPER_FLAGS_5(sve_scvt_dh, TCG_CALL_NO_RWG,
442
- void, ptr, ptr, ptr, ptr, i32)
443
+ void, ptr, ptr, ptr, fpst, i32)
444
DEF_HELPER_FLAGS_5(sve_scvt_ss, TCG_CALL_NO_RWG,
445
- void, ptr, ptr, ptr, ptr, i32)
446
+ void, ptr, ptr, ptr, fpst, i32)
447
DEF_HELPER_FLAGS_5(sve_scvt_sd, TCG_CALL_NO_RWG,
448
- void, ptr, ptr, ptr, ptr, i32)
449
+ void, ptr, ptr, ptr, fpst, i32)
450
DEF_HELPER_FLAGS_5(sve_scvt_ds, TCG_CALL_NO_RWG,
451
- void, ptr, ptr, ptr, ptr, i32)
452
+ void, ptr, ptr, ptr, fpst, i32)
453
DEF_HELPER_FLAGS_5(sve_scvt_dd, TCG_CALL_NO_RWG,
454
- void, ptr, ptr, ptr, ptr, i32)
455
+ void, ptr, ptr, ptr, fpst, i32)
456
457
DEF_HELPER_FLAGS_5(sve_ucvt_hh, TCG_CALL_NO_RWG,
458
- void, ptr, ptr, ptr, ptr, i32)
459
+ void, ptr, ptr, ptr, fpst, i32)
460
DEF_HELPER_FLAGS_5(sve_ucvt_sh, TCG_CALL_NO_RWG,
461
- void, ptr, ptr, ptr, ptr, i32)
462
+ void, ptr, ptr, ptr, fpst, i32)
463
DEF_HELPER_FLAGS_5(sve_ucvt_dh, TCG_CALL_NO_RWG,
464
- void, ptr, ptr, ptr, ptr, i32)
465
+ void, ptr, ptr, ptr, fpst, i32)
466
DEF_HELPER_FLAGS_5(sve_ucvt_ss, TCG_CALL_NO_RWG,
467
- void, ptr, ptr, ptr, ptr, i32)
468
+ void, ptr, ptr, ptr, fpst, i32)
469
DEF_HELPER_FLAGS_5(sve_ucvt_sd, TCG_CALL_NO_RWG,
470
- void, ptr, ptr, ptr, ptr, i32)
471
+ void, ptr, ptr, ptr, fpst, i32)
472
DEF_HELPER_FLAGS_5(sve_ucvt_ds, TCG_CALL_NO_RWG,
473
- void, ptr, ptr, ptr, ptr, i32)
474
+ void, ptr, ptr, ptr, fpst, i32)
475
DEF_HELPER_FLAGS_5(sve_ucvt_dd, TCG_CALL_NO_RWG,
476
- void, ptr, ptr, ptr, ptr, i32)
477
+ void, ptr, ptr, ptr, fpst, i32)
478
479
DEF_HELPER_FLAGS_6(sve_fcmge_h, TCG_CALL_NO_RWG,
480
- void, ptr, ptr, ptr, ptr, ptr, i32)
481
+ void, ptr, ptr, ptr, ptr, fpst, i32)
482
DEF_HELPER_FLAGS_6(sve_fcmge_s, TCG_CALL_NO_RWG,
483
- void, ptr, ptr, ptr, ptr, ptr, i32)
484
+ void, ptr, ptr, ptr, ptr, fpst, i32)
485
DEF_HELPER_FLAGS_6(sve_fcmge_d, TCG_CALL_NO_RWG,
486
- void, ptr, ptr, ptr, ptr, ptr, i32)
487
+ void, ptr, ptr, ptr, ptr, fpst, i32)
488
489
DEF_HELPER_FLAGS_6(sve_fcmgt_h, TCG_CALL_NO_RWG,
490
- void, ptr, ptr, ptr, ptr, ptr, i32)
491
+ void, ptr, ptr, ptr, ptr, fpst, i32)
492
DEF_HELPER_FLAGS_6(sve_fcmgt_s, TCG_CALL_NO_RWG,
493
- void, ptr, ptr, ptr, ptr, ptr, i32)
494
+ void, ptr, ptr, ptr, ptr, fpst, i32)
495
DEF_HELPER_FLAGS_6(sve_fcmgt_d, TCG_CALL_NO_RWG,
496
- void, ptr, ptr, ptr, ptr, ptr, i32)
497
+ void, ptr, ptr, ptr, ptr, fpst, i32)
498
499
DEF_HELPER_FLAGS_6(sve_fcmeq_h, TCG_CALL_NO_RWG,
500
- void, ptr, ptr, ptr, ptr, ptr, i32)
501
+ void, ptr, ptr, ptr, ptr, fpst, i32)
502
DEF_HELPER_FLAGS_6(sve_fcmeq_s, TCG_CALL_NO_RWG,
503
- void, ptr, ptr, ptr, ptr, ptr, i32)
504
+ void, ptr, ptr, ptr, ptr, fpst, i32)
505
DEF_HELPER_FLAGS_6(sve_fcmeq_d, TCG_CALL_NO_RWG,
506
- void, ptr, ptr, ptr, ptr, ptr, i32)
507
+ void, ptr, ptr, ptr, ptr, fpst, i32)
508
509
DEF_HELPER_FLAGS_6(sve_fcmne_h, TCG_CALL_NO_RWG,
510
- void, ptr, ptr, ptr, ptr, ptr, i32)
511
+ void, ptr, ptr, ptr, ptr, fpst, i32)
512
DEF_HELPER_FLAGS_6(sve_fcmne_s, TCG_CALL_NO_RWG,
513
- void, ptr, ptr, ptr, ptr, ptr, i32)
514
+ void, ptr, ptr, ptr, ptr, fpst, i32)
515
DEF_HELPER_FLAGS_6(sve_fcmne_d, TCG_CALL_NO_RWG,
516
- void, ptr, ptr, ptr, ptr, ptr, i32)
517
+ void, ptr, ptr, ptr, ptr, fpst, i32)
518
519
DEF_HELPER_FLAGS_6(sve_fcmuo_h, TCG_CALL_NO_RWG,
520
- void, ptr, ptr, ptr, ptr, ptr, i32)
521
+ void, ptr, ptr, ptr, ptr, fpst, i32)
522
DEF_HELPER_FLAGS_6(sve_fcmuo_s, TCG_CALL_NO_RWG,
523
- void, ptr, ptr, ptr, ptr, ptr, i32)
524
+ void, ptr, ptr, ptr, ptr, fpst, i32)
525
DEF_HELPER_FLAGS_6(sve_fcmuo_d, TCG_CALL_NO_RWG,
526
- void, ptr, ptr, ptr, ptr, ptr, i32)
527
+ void, ptr, ptr, ptr, ptr, fpst, i32)
528
529
DEF_HELPER_FLAGS_6(sve_facge_h, TCG_CALL_NO_RWG,
530
- void, ptr, ptr, ptr, ptr, ptr, i32)
531
+ void, ptr, ptr, ptr, ptr, fpst, i32)
532
DEF_HELPER_FLAGS_6(sve_facge_s, TCG_CALL_NO_RWG,
533
- void, ptr, ptr, ptr, ptr, ptr, i32)
534
+ void, ptr, ptr, ptr, ptr, fpst, i32)
535
DEF_HELPER_FLAGS_6(sve_facge_d, TCG_CALL_NO_RWG,
536
- void, ptr, ptr, ptr, ptr, ptr, i32)
537
+ void, ptr, ptr, ptr, ptr, fpst, i32)
538
539
DEF_HELPER_FLAGS_6(sve_facgt_h, TCG_CALL_NO_RWG,
540
- void, ptr, ptr, ptr, ptr, ptr, i32)
541
+ void, ptr, ptr, ptr, ptr, fpst, i32)
542
DEF_HELPER_FLAGS_6(sve_facgt_s, TCG_CALL_NO_RWG,
543
- void, ptr, ptr, ptr, ptr, ptr, i32)
544
+ void, ptr, ptr, ptr, ptr, fpst, i32)
545
DEF_HELPER_FLAGS_6(sve_facgt_d, TCG_CALL_NO_RWG,
546
- void, ptr, ptr, ptr, ptr, ptr, i32)
547
+ void, ptr, ptr, ptr, ptr, fpst, i32)
548
549
DEF_HELPER_FLAGS_6(sve_fcadd_h, TCG_CALL_NO_RWG,
550
- void, ptr, ptr, ptr, ptr, ptr, i32)
551
+ void, ptr, ptr, ptr, ptr, fpst, i32)
552
DEF_HELPER_FLAGS_6(sve_fcadd_s, TCG_CALL_NO_RWG,
553
- void, ptr, ptr, ptr, ptr, ptr, i32)
554
+ void, ptr, ptr, ptr, ptr, fpst, i32)
555
DEF_HELPER_FLAGS_6(sve_fcadd_d, TCG_CALL_NO_RWG,
556
- void, ptr, ptr, ptr, ptr, ptr, i32)
557
+ void, ptr, ptr, ptr, ptr, fpst, i32)
558
559
DEF_HELPER_FLAGS_7(sve_fmla_zpzzz_h, TCG_CALL_NO_RWG,
560
- void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
561
+ void, ptr, ptr, ptr, ptr, ptr, fpst, i32)
562
DEF_HELPER_FLAGS_7(sve_fmla_zpzzz_s, TCG_CALL_NO_RWG,
563
- void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
564
+ void, ptr, ptr, ptr, ptr, ptr, fpst, i32)
565
DEF_HELPER_FLAGS_7(sve_fmla_zpzzz_d, TCG_CALL_NO_RWG,
566
- void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
567
+ void, ptr, ptr, ptr, ptr, ptr, fpst, i32)
568
569
DEF_HELPER_FLAGS_7(sve_fmls_zpzzz_h, TCG_CALL_NO_RWG,
570
- void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
571
+ void, ptr, ptr, ptr, ptr, ptr, fpst, i32)
572
DEF_HELPER_FLAGS_7(sve_fmls_zpzzz_s, TCG_CALL_NO_RWG,
573
- void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
574
+ void, ptr, ptr, ptr, ptr, ptr, fpst, i32)
575
DEF_HELPER_FLAGS_7(sve_fmls_zpzzz_d, TCG_CALL_NO_RWG,
576
- void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
577
+ void, ptr, ptr, ptr, ptr, ptr, fpst, i32)
578
579
DEF_HELPER_FLAGS_7(sve_fnmla_zpzzz_h, TCG_CALL_NO_RWG,
580
- void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
581
+ void, ptr, ptr, ptr, ptr, ptr, fpst, i32)
582
DEF_HELPER_FLAGS_7(sve_fnmla_zpzzz_s, TCG_CALL_NO_RWG,
583
- void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
584
+ void, ptr, ptr, ptr, ptr, ptr, fpst, i32)
585
DEF_HELPER_FLAGS_7(sve_fnmla_zpzzz_d, TCG_CALL_NO_RWG,
586
- void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
587
+ void, ptr, ptr, ptr, ptr, ptr, fpst, i32)
588
589
DEF_HELPER_FLAGS_7(sve_fnmls_zpzzz_h, TCG_CALL_NO_RWG,
590
- void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
591
+ void, ptr, ptr, ptr, ptr, ptr, fpst, i32)
592
DEF_HELPER_FLAGS_7(sve_fnmls_zpzzz_s, TCG_CALL_NO_RWG,
593
- void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
594
+ void, ptr, ptr, ptr, ptr, ptr, fpst, i32)
595
DEF_HELPER_FLAGS_7(sve_fnmls_zpzzz_d, TCG_CALL_NO_RWG,
596
- void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
597
+ void, ptr, ptr, ptr, ptr, ptr, fpst, i32)
598
599
DEF_HELPER_FLAGS_7(sve_fcmla_zpzzz_h, TCG_CALL_NO_RWG,
600
- void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
601
+ void, ptr, ptr, ptr, ptr, ptr, fpst, i32)
602
DEF_HELPER_FLAGS_7(sve_fcmla_zpzzz_s, TCG_CALL_NO_RWG,
603
- void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
604
+ void, ptr, ptr, ptr, ptr, ptr, fpst, i32)
605
DEF_HELPER_FLAGS_7(sve_fcmla_zpzzz_d, TCG_CALL_NO_RWG,
606
- void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
607
+ void, ptr, ptr, ptr, ptr, ptr, fpst, i32)
608
609
-DEF_HELPER_FLAGS_5(sve_ftmad_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
610
-DEF_HELPER_FLAGS_5(sve_ftmad_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
611
-DEF_HELPER_FLAGS_5(sve_ftmad_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
612
+DEF_HELPER_FLAGS_5(sve_ftmad_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
613
+DEF_HELPER_FLAGS_5(sve_ftmad_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
614
+DEF_HELPER_FLAGS_5(sve_ftmad_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
615
616
DEF_HELPER_FLAGS_4(sve2_saddl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
617
DEF_HELPER_FLAGS_4(sve2_saddl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
618
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(sve2_xar_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
619
DEF_HELPER_FLAGS_4(sve2_xar_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
620
621
DEF_HELPER_FLAGS_6(sve2_faddp_zpzz_h, TCG_CALL_NO_RWG,
622
- void, ptr, ptr, ptr, ptr, ptr, i32)
623
+ void, ptr, ptr, ptr, ptr, fpst, i32)
624
DEF_HELPER_FLAGS_6(sve2_faddp_zpzz_s, TCG_CALL_NO_RWG,
625
- void, ptr, ptr, ptr, ptr, ptr, i32)
626
+ void, ptr, ptr, ptr, ptr, fpst, i32)
627
DEF_HELPER_FLAGS_6(sve2_faddp_zpzz_d, TCG_CALL_NO_RWG,
628
- void, ptr, ptr, ptr, ptr, ptr, i32)
629
+ void, ptr, ptr, ptr, ptr, fpst, i32)
630
631
DEF_HELPER_FLAGS_6(sve2_fmaxnmp_zpzz_h, TCG_CALL_NO_RWG,
632
- void, ptr, ptr, ptr, ptr, ptr, i32)
633
+ void, ptr, ptr, ptr, ptr, fpst, i32)
634
DEF_HELPER_FLAGS_6(sve2_fmaxnmp_zpzz_s, TCG_CALL_NO_RWG,
635
- void, ptr, ptr, ptr, ptr, ptr, i32)
636
+ void, ptr, ptr, ptr, ptr, fpst, i32)
637
DEF_HELPER_FLAGS_6(sve2_fmaxnmp_zpzz_d, TCG_CALL_NO_RWG,
638
- void, ptr, ptr, ptr, ptr, ptr, i32)
639
+ void, ptr, ptr, ptr, ptr, fpst, i32)
640
641
DEF_HELPER_FLAGS_6(sve2_fminnmp_zpzz_h, TCG_CALL_NO_RWG,
642
- void, ptr, ptr, ptr, ptr, ptr, i32)
643
+ void, ptr, ptr, ptr, ptr, fpst, i32)
644
DEF_HELPER_FLAGS_6(sve2_fminnmp_zpzz_s, TCG_CALL_NO_RWG,
645
- void, ptr, ptr, ptr, ptr, ptr, i32)
646
+ void, ptr, ptr, ptr, ptr, fpst, i32)
647
DEF_HELPER_FLAGS_6(sve2_fminnmp_zpzz_d, TCG_CALL_NO_RWG,
648
- void, ptr, ptr, ptr, ptr, ptr, i32)
649
+ void, ptr, ptr, ptr, ptr, fpst, i32)
650
651
DEF_HELPER_FLAGS_6(sve2_fmaxp_zpzz_h, TCG_CALL_NO_RWG,
652
- void, ptr, ptr, ptr, ptr, ptr, i32)
653
+ void, ptr, ptr, ptr, ptr, fpst, i32)
654
DEF_HELPER_FLAGS_6(sve2_fmaxp_zpzz_s, TCG_CALL_NO_RWG,
655
- void, ptr, ptr, ptr, ptr, ptr, i32)
656
+ void, ptr, ptr, ptr, ptr, fpst, i32)
657
DEF_HELPER_FLAGS_6(sve2_fmaxp_zpzz_d, TCG_CALL_NO_RWG,
658
- void, ptr, ptr, ptr, ptr, ptr, i32)
659
+ void, ptr, ptr, ptr, ptr, fpst, i32)
660
661
DEF_HELPER_FLAGS_6(sve2_fminp_zpzz_h, TCG_CALL_NO_RWG,
662
- void, ptr, ptr, ptr, ptr, ptr, i32)
663
+ void, ptr, ptr, ptr, ptr, fpst, i32)
664
DEF_HELPER_FLAGS_6(sve2_fminp_zpzz_s, TCG_CALL_NO_RWG,
665
- void, ptr, ptr, ptr, ptr, ptr, i32)
666
+ void, ptr, ptr, ptr, ptr, fpst, i32)
667
DEF_HELPER_FLAGS_6(sve2_fminp_zpzz_d, TCG_CALL_NO_RWG,
668
- void, ptr, ptr, ptr, ptr, ptr, i32)
669
+ void, ptr, ptr, ptr, ptr, fpst, i32)
670
671
DEF_HELPER_FLAGS_5(sve2_eor3, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
672
DEF_HELPER_FLAGS_5(sve2_bcax, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
673
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(sve2_sqrdcmlah_zzzz_s, TCG_CALL_NO_RWG,
674
DEF_HELPER_FLAGS_5(sve2_sqrdcmlah_zzzz_d, TCG_CALL_NO_RWG,
675
void, ptr, ptr, ptr, ptr, i32)
676
677
-DEF_HELPER_FLAGS_6(fmmla_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr, i32)
678
-DEF_HELPER_FLAGS_6(fmmla_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr, i32)
679
+DEF_HELPER_FLAGS_6(fmmla_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, fpst, i32)
680
+DEF_HELPER_FLAGS_6(fmmla_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, fpst, i32)
681
682
DEF_HELPER_FLAGS_5(sve2_sqrdmlah_idx_h, TCG_CALL_NO_RWG,
683
void, ptr, ptr, ptr, ptr, i32)
684
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(sve2_cdot_idx_d, TCG_CALL_NO_RWG,
685
void, ptr, ptr, ptr, ptr, i32)
686
687
DEF_HELPER_FLAGS_5(sve2_fcvtnt_sh, TCG_CALL_NO_RWG,
688
- void, ptr, ptr, ptr, ptr, i32)
689
+ void, ptr, ptr, ptr, fpst, i32)
690
DEF_HELPER_FLAGS_5(sve2_fcvtnt_ds, TCG_CALL_NO_RWG,
691
- void, ptr, ptr, ptr, ptr, i32)
692
+ void, ptr, ptr, ptr, fpst, i32)
693
DEF_HELPER_FLAGS_5(sve_bfcvtnt, TCG_CALL_NO_RWG,
694
- void, ptr, ptr, ptr, ptr, i32)
695
+ void, ptr, ptr, ptr, fpst, i32)
696
697
DEF_HELPER_FLAGS_5(sve2_fcvtlt_hs, TCG_CALL_NO_RWG,
698
- void, ptr, ptr, ptr, ptr, i32)
699
+ void, ptr, ptr, ptr, fpst, i32)
700
DEF_HELPER_FLAGS_5(sve2_fcvtlt_sd, TCG_CALL_NO_RWG,
701
- void, ptr, ptr, ptr, ptr, i32)
702
+ void, ptr, ptr, ptr, fpst, i32)
703
704
-DEF_HELPER_FLAGS_5(flogb_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
705
-DEF_HELPER_FLAGS_5(flogb_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
706
-DEF_HELPER_FLAGS_5(flogb_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
707
+DEF_HELPER_FLAGS_5(flogb_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
708
+DEF_HELPER_FLAGS_5(flogb_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
709
+DEF_HELPER_FLAGS_5(flogb_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
710
711
DEF_HELPER_FLAGS_4(sve2_sqshl_zpzi_b, TCG_CALL_NO_RWG,
712
void, ptr, ptr, ptr, i32)
713
diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c
714
index XXXXXXX..XXXXXXX 100644
715
--- a/target/arm/tcg/sve_helper.c
716
+++ b/target/arm/tcg/sve_helper.c
717
@@ -XXX,XX +XXX,XX @@ DO_ZPZZ_PAIR_D(sve2_sminp_zpzz_d, int64_t, DO_MIN)
718
719
#define DO_ZPZZ_PAIR_FP(NAME, TYPE, H, OP) \
720
void HELPER(NAME)(void *vd, void *vn, void *vm, void *vg, \
721
- void *status, uint32_t desc) \
722
+ float_status *status, uint32_t desc) \
723
{ \
724
intptr_t i, opr_sz = simd_oprsz(desc); \
725
for (i = 0; i < opr_sz; ) { \
726
@@ -XXX,XX +XXX,XX @@ static TYPE NAME##_reduce(TYPE *data, float_status *status, uintptr_t n) \
727
return TYPE##_##FUNC(lo, hi, status); \
728
} \
729
} \
730
-uint64_t HELPER(NAME)(void *vn, void *vg, void *vs, uint32_t desc) \
731
+uint64_t HELPER(NAME)(void *vn, void *vg, float_status *s, uint32_t desc) \
732
{ \
733
uintptr_t i, oprsz = simd_oprsz(desc), maxsz = simd_data(desc); \
734
TYPE data[sizeof(ARMVectorReg) / sizeof(TYPE)]; \
735
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(NAME)(void *vn, void *vg, void *vs, uint32_t desc) \
736
for (; i < maxsz; i += sizeof(TYPE)) { \
737
*(TYPE *)((void *)data + i) = IDENT; \
738
} \
739
- return NAME##_reduce(data, vs, maxsz / sizeof(TYPE)); \
740
+ return NAME##_reduce(data, s, maxsz / sizeof(TYPE)); \
741
}
742
743
DO_REDUCE(sve_faddv_h, float16, H1_2, add, float16_zero)
744
@@ -XXX,XX +XXX,XX @@ DO_REDUCE(sve_fmaxv_d, float64, H1_8, max, float64_chs(float64_infinity))
745
#undef DO_REDUCE
746
747
uint64_t HELPER(sve_fadda_h)(uint64_t nn, void *vm, void *vg,
748
- void *status, uint32_t desc)
749
+ float_status *status, uint32_t desc)
750
{
751
intptr_t i = 0, opr_sz = simd_oprsz(desc);
752
float16 result = nn;
753
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(sve_fadda_h)(uint64_t nn, void *vm, void *vg,
754
}
755
756
uint64_t HELPER(sve_fadda_s)(uint64_t nn, void *vm, void *vg,
757
- void *status, uint32_t desc)
758
+ float_status *status, uint32_t desc)
759
{
760
intptr_t i = 0, opr_sz = simd_oprsz(desc);
761
float32 result = nn;
762
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(sve_fadda_s)(uint64_t nn, void *vm, void *vg,
763
}
764
765
uint64_t HELPER(sve_fadda_d)(uint64_t nn, void *vm, void *vg,
766
- void *status, uint32_t desc)
767
+ float_status *status, uint32_t desc)
768
{
769
intptr_t i = 0, opr_sz = simd_oprsz(desc) / 8;
770
uint64_t *m = vm;
771
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(sve_fadda_d)(uint64_t nn, void *vm, void *vg,
772
*/
773
#define DO_ZPZZ_FP(NAME, TYPE, H, OP) \
774
void HELPER(NAME)(void *vd, void *vn, void *vm, void *vg, \
775
- void *status, uint32_t desc) \
776
+ float_status *status, uint32_t desc) \
777
{ \
778
intptr_t i = simd_oprsz(desc); \
779
uint64_t *g = vg; \
780
@@ -XXX,XX +XXX,XX @@ DO_ZPZZ_FP(sve_fmulx_d, uint64_t, H1_8, helper_vfp_mulxd)
781
*/
782
#define DO_ZPZS_FP(NAME, TYPE, H, OP) \
783
void HELPER(NAME)(void *vd, void *vn, void *vg, uint64_t scalar, \
784
- void *status, uint32_t desc) \
785
+ float_status *status, uint32_t desc) \
786
{ \
787
intptr_t i = simd_oprsz(desc); \
788
uint64_t *g = vg; \
789
@@ -XXX,XX +XXX,XX @@ DO_ZPZS_FP(sve_fmins_d, float64, H1_8, float64_min)
790
* With the extra float_status parameter.
791
*/
792
#define DO_ZPZ_FP(NAME, TYPE, H, OP) \
793
-void HELPER(NAME)(void *vd, void *vn, void *vg, void *status, uint32_t desc) \
794
+void HELPER(NAME)(void *vd, void *vn, void *vg, \
795
+ float_status *status, uint32_t desc) \
796
{ \
797
intptr_t i = simd_oprsz(desc); \
798
uint64_t *g = vg; \
799
@@ -XXX,XX +XXX,XX @@ static void do_fmla_zpzzz_h(void *vd, void *vn, void *vm, void *va, void *vg,
800
}
801
802
void HELPER(sve_fmla_zpzzz_h)(void *vd, void *vn, void *vm, void *va,
803
- void *vg, void *status, uint32_t desc)
804
+ void *vg, float_status *status, uint32_t desc)
805
{
806
do_fmla_zpzzz_h(vd, vn, vm, va, vg, status, desc, 0, 0);
807
}
808
809
void HELPER(sve_fmls_zpzzz_h)(void *vd, void *vn, void *vm, void *va,
810
- void *vg, void *status, uint32_t desc)
811
+ void *vg, float_status *status, uint32_t desc)
812
{
813
do_fmla_zpzzz_h(vd, vn, vm, va, vg, status, desc, 0x8000, 0);
814
}
815
816
void HELPER(sve_fnmla_zpzzz_h)(void *vd, void *vn, void *vm, void *va,
817
- void *vg, void *status, uint32_t desc)
818
+ void *vg, float_status *status, uint32_t desc)
819
{
820
do_fmla_zpzzz_h(vd, vn, vm, va, vg, status, desc, 0x8000, 0x8000);
821
}
822
823
void HELPER(sve_fnmls_zpzzz_h)(void *vd, void *vn, void *vm, void *va,
824
- void *vg, void *status, uint32_t desc)
825
+ void *vg, float_status *status, uint32_t desc)
826
{
827
do_fmla_zpzzz_h(vd, vn, vm, va, vg, status, desc, 0, 0x8000);
828
}
829
@@ -XXX,XX +XXX,XX @@ static void do_fmla_zpzzz_s(void *vd, void *vn, void *vm, void *va, void *vg,
830
}
831
832
void HELPER(sve_fmla_zpzzz_s)(void *vd, void *vn, void *vm, void *va,
833
- void *vg, void *status, uint32_t desc)
834
+ void *vg, float_status *status, uint32_t desc)
835
{
836
do_fmla_zpzzz_s(vd, vn, vm, va, vg, status, desc, 0, 0);
837
}
838
839
void HELPER(sve_fmls_zpzzz_s)(void *vd, void *vn, void *vm, void *va,
840
- void *vg, void *status, uint32_t desc)
841
+ void *vg, float_status *status, uint32_t desc)
842
{
843
do_fmla_zpzzz_s(vd, vn, vm, va, vg, status, desc, 0x80000000, 0);
844
}
845
846
void HELPER(sve_fnmla_zpzzz_s)(void *vd, void *vn, void *vm, void *va,
847
- void *vg, void *status, uint32_t desc)
848
+ void *vg, float_status *status, uint32_t desc)
849
{
850
do_fmla_zpzzz_s(vd, vn, vm, va, vg, status, desc, 0x80000000, 0x80000000);
851
}
852
853
void HELPER(sve_fnmls_zpzzz_s)(void *vd, void *vn, void *vm, void *va,
854
- void *vg, void *status, uint32_t desc)
855
+ void *vg, float_status *status, uint32_t desc)
856
{
857
do_fmla_zpzzz_s(vd, vn, vm, va, vg, status, desc, 0, 0x80000000);
858
}
859
@@ -XXX,XX +XXX,XX @@ static void do_fmla_zpzzz_d(void *vd, void *vn, void *vm, void *va, void *vg,
860
}
861
862
void HELPER(sve_fmla_zpzzz_d)(void *vd, void *vn, void *vm, void *va,
863
- void *vg, void *status, uint32_t desc)
864
+ void *vg, float_status *status, uint32_t desc)
865
{
866
do_fmla_zpzzz_d(vd, vn, vm, va, vg, status, desc, 0, 0);
867
}
868
869
void HELPER(sve_fmls_zpzzz_d)(void *vd, void *vn, void *vm, void *va,
870
- void *vg, void *status, uint32_t desc)
871
+ void *vg, float_status *status, uint32_t desc)
872
{
873
do_fmla_zpzzz_d(vd, vn, vm, va, vg, status, desc, INT64_MIN, 0);
874
}
875
876
void HELPER(sve_fnmla_zpzzz_d)(void *vd, void *vn, void *vm, void *va,
877
- void *vg, void *status, uint32_t desc)
878
+ void *vg, float_status *status, uint32_t desc)
879
{
880
do_fmla_zpzzz_d(vd, vn, vm, va, vg, status, desc, INT64_MIN, INT64_MIN);
881
}
882
883
void HELPER(sve_fnmls_zpzzz_d)(void *vd, void *vn, void *vm, void *va,
884
- void *vg, void *status, uint32_t desc)
885
+ void *vg, float_status *status, uint32_t desc)
886
{
887
do_fmla_zpzzz_d(vd, vn, vm, va, vg, status, desc, 0, INT64_MIN);
888
}
889
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_fnmls_zpzzz_d)(void *vd, void *vn, void *vm, void *va,
890
*/
891
#define DO_FPCMP_PPZZ(NAME, TYPE, H, OP) \
892
void HELPER(NAME)(void *vd, void *vn, void *vm, void *vg, \
893
- void *status, uint32_t desc) \
894
+ float_status *status, uint32_t desc) \
895
{ \
896
intptr_t i = simd_oprsz(desc), j = (i - 1) >> 6; \
897
uint64_t *d = vd, *g = vg; \
898
@@ -XXX,XX +XXX,XX @@ DO_FPCMP_PPZZ_ALL(sve_facgt, DO_FACGT)
899
*/
900
#define DO_FPCMP_PPZ0(NAME, TYPE, H, OP) \
901
void HELPER(NAME)(void *vd, void *vn, void *vg, \
902
- void *status, uint32_t desc) \
903
+ float_status *status, uint32_t desc) \
904
{ \
905
intptr_t i = simd_oprsz(desc), j = (i - 1) >> 6; \
906
uint64_t *d = vd, *g = vg; \
907
@@ -XXX,XX +XXX,XX @@ DO_FPCMP_PPZ0_ALL(sve_fcmne0, DO_FCMNE)
908
909
/* FP Trig Multiply-Add. */
910
911
-void HELPER(sve_ftmad_h)(void *vd, void *vn, void *vm, void *vs, uint32_t desc)
912
+void HELPER(sve_ftmad_h)(void *vd, void *vn, void *vm,
913
+ float_status *s, uint32_t desc)
914
{
915
static const float16 coeff[16] = {
916
0x3c00, 0xb155, 0x2030, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
917
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_ftmad_h)(void *vd, void *vn, void *vm, void *vs, uint32_t desc)
918
mm = float16_abs(mm);
919
xx += 8;
920
}
921
- d[i] = float16_muladd(n[i], mm, coeff[xx], 0, vs);
922
+ d[i] = float16_muladd(n[i], mm, coeff[xx], 0, s);
34
}
923
}
35
}
924
}
36
925
926
-void HELPER(sve_ftmad_s)(void *vd, void *vn, void *vm, void *vs, uint32_t desc)
927
+void HELPER(sve_ftmad_s)(void *vd, void *vn, void *vm,
928
+ float_status *s, uint32_t desc)
929
{
930
static const float32 coeff[16] = {
931
0x3f800000, 0xbe2aaaab, 0x3c088886, 0xb95008b9,
932
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_ftmad_s)(void *vd, void *vn, void *vm, void *vs, uint32_t desc)
933
mm = float32_abs(mm);
934
xx += 8;
935
}
936
- d[i] = float32_muladd(n[i], mm, coeff[xx], 0, vs);
937
+ d[i] = float32_muladd(n[i], mm, coeff[xx], 0, s);
938
}
939
}
940
941
-void HELPER(sve_ftmad_d)(void *vd, void *vn, void *vm, void *vs, uint32_t desc)
942
+void HELPER(sve_ftmad_d)(void *vd, void *vn, void *vm,
943
+ float_status *s, uint32_t desc)
944
{
945
static const float64 coeff[16] = {
946
0x3ff0000000000000ull, 0xbfc5555555555543ull,
947
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_ftmad_d)(void *vd, void *vn, void *vm, void *vs, uint32_t desc)
948
mm = float64_abs(mm);
949
xx += 8;
950
}
951
- d[i] = float64_muladd(n[i], mm, coeff[xx], 0, vs);
952
+ d[i] = float64_muladd(n[i], mm, coeff[xx], 0, s);
953
}
954
}
955
956
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_ftmad_d)(void *vd, void *vn, void *vm, void *vs, uint32_t desc)
957
*/
958
959
void HELPER(sve_fcadd_h)(void *vd, void *vn, void *vm, void *vg,
960
- void *vs, uint32_t desc)
961
+ float_status *s, uint32_t desc)
962
{
963
intptr_t j, i = simd_oprsz(desc);
964
uint64_t *g = vg;
965
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_fcadd_h)(void *vd, void *vn, void *vm, void *vg,
966
e3 = *(float16 *)(vm + H1_2(i)) ^ neg_imag;
967
968
if (likely((pg >> (i & 63)) & 1)) {
969
- *(float16 *)(vd + H1_2(i)) = float16_add(e0, e1, vs);
970
+ *(float16 *)(vd + H1_2(i)) = float16_add(e0, e1, s);
971
}
972
if (likely((pg >> (j & 63)) & 1)) {
973
- *(float16 *)(vd + H1_2(j)) = float16_add(e2, e3, vs);
974
+ *(float16 *)(vd + H1_2(j)) = float16_add(e2, e3, s);
975
}
976
} while (i & 63);
977
} while (i != 0);
978
}
979
980
void HELPER(sve_fcadd_s)(void *vd, void *vn, void *vm, void *vg,
981
- void *vs, uint32_t desc)
982
+ float_status *s, uint32_t desc)
983
{
984
intptr_t j, i = simd_oprsz(desc);
985
uint64_t *g = vg;
986
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_fcadd_s)(void *vd, void *vn, void *vm, void *vg,
987
e3 = *(float32 *)(vm + H1_2(i)) ^ neg_imag;
988
989
if (likely((pg >> (i & 63)) & 1)) {
990
- *(float32 *)(vd + H1_2(i)) = float32_add(e0, e1, vs);
991
+ *(float32 *)(vd + H1_2(i)) = float32_add(e0, e1, s);
992
}
993
if (likely((pg >> (j & 63)) & 1)) {
994
- *(float32 *)(vd + H1_2(j)) = float32_add(e2, e3, vs);
995
+ *(float32 *)(vd + H1_2(j)) = float32_add(e2, e3, s);
996
}
997
} while (i & 63);
998
} while (i != 0);
999
}
1000
1001
void HELPER(sve_fcadd_d)(void *vd, void *vn, void *vm, void *vg,
1002
- void *vs, uint32_t desc)
1003
+ float_status *s, uint32_t desc)
1004
{
1005
intptr_t j, i = simd_oprsz(desc);
1006
uint64_t *g = vg;
1007
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_fcadd_d)(void *vd, void *vn, void *vm, void *vg,
1008
e3 = *(float64 *)(vm + H1_2(i)) ^ neg_imag;
1009
1010
if (likely((pg >> (i & 63)) & 1)) {
1011
- *(float64 *)(vd + H1_2(i)) = float64_add(e0, e1, vs);
1012
+ *(float64 *)(vd + H1_2(i)) = float64_add(e0, e1, s);
1013
}
1014
if (likely((pg >> (j & 63)) & 1)) {
1015
- *(float64 *)(vd + H1_2(j)) = float64_add(e2, e3, vs);
1016
+ *(float64 *)(vd + H1_2(j)) = float64_add(e2, e3, s);
1017
}
1018
} while (i & 63);
1019
} while (i != 0);
1020
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_fcadd_d)(void *vd, void *vn, void *vm, void *vg,
1021
*/
1022
1023
void HELPER(sve_fcmla_zpzzz_h)(void *vd, void *vn, void *vm, void *va,
1024
- void *vg, void *status, uint32_t desc)
1025
+ void *vg, float_status *status, uint32_t desc)
1026
{
1027
intptr_t j, i = simd_oprsz(desc);
1028
unsigned rot = simd_data(desc);
1029
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_fcmla_zpzzz_h)(void *vd, void *vn, void *vm, void *va,
1030
}
1031
1032
void HELPER(sve_fcmla_zpzzz_s)(void *vd, void *vn, void *vm, void *va,
1033
- void *vg, void *status, uint32_t desc)
1034
+ void *vg, float_status *status, uint32_t desc)
1035
{
1036
intptr_t j, i = simd_oprsz(desc);
1037
unsigned rot = simd_data(desc);
1038
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_fcmla_zpzzz_s)(void *vd, void *vn, void *vm, void *va,
1039
}
1040
1041
void HELPER(sve_fcmla_zpzzz_d)(void *vd, void *vn, void *vm, void *va,
1042
- void *vg, void *status, uint32_t desc)
1043
+ void *vg, float_status *status, uint32_t desc)
1044
{
1045
intptr_t j, i = simd_oprsz(desc);
1046
unsigned rot = simd_data(desc);
1047
@@ -XXX,XX +XXX,XX @@ void HELPER(sve2_xar_s)(void *vd, void *vn, void *vm, uint32_t desc)
1048
}
1049
1050
void HELPER(fmmla_s)(void *vd, void *vn, void *vm, void *va,
1051
- void *status, uint32_t desc)
1052
+ float_status *status, uint32_t desc)
1053
{
1054
intptr_t s, opr_sz = simd_oprsz(desc) / (sizeof(float32) * 4);
1055
1056
@@ -XXX,XX +XXX,XX @@ void HELPER(fmmla_s)(void *vd, void *vn, void *vm, void *va,
1057
}
1058
1059
void HELPER(fmmla_d)(void *vd, void *vn, void *vm, void *va,
1060
- void *status, uint32_t desc)
1061
+ float_status *status, uint32_t desc)
1062
{
1063
intptr_t s, opr_sz = simd_oprsz(desc) / (sizeof(float64) * 4);
1064
1065
@@ -XXX,XX +XXX,XX @@ void HELPER(fmmla_d)(void *vd, void *vn, void *vm, void *va,
1066
}
1067
1068
#define DO_FCVTNT(NAME, TYPEW, TYPEN, HW, HN, OP) \
1069
-void HELPER(NAME)(void *vd, void *vn, void *vg, void *status, uint32_t desc) \
1070
+void HELPER(NAME)(void *vd, void *vn, void *vg, \
1071
+ float_status *status, uint32_t desc) \
1072
{ \
1073
intptr_t i = simd_oprsz(desc); \
1074
uint64_t *g = vg; \
1075
@@ -XXX,XX +XXX,XX @@ DO_FCVTNT(sve2_fcvtnt_sh, uint32_t, uint16_t, H1_4, H1_2, sve_f32_to_f16)
1076
DO_FCVTNT(sve2_fcvtnt_ds, uint64_t, uint32_t, H1_8, H1_4, float64_to_float32)
1077
1078
#define DO_FCVTLT(NAME, TYPEW, TYPEN, HW, HN, OP) \
1079
-void HELPER(NAME)(void *vd, void *vn, void *vg, void *status, uint32_t desc) \
1080
+void HELPER(NAME)(void *vd, void *vn, void *vg, \
1081
+ float_status *status, uint32_t desc) \
1082
{ \
1083
intptr_t i = simd_oprsz(desc); \
1084
uint64_t *g = vg; \
37
--
1085
--
38
2.34.1
1086
2.34.1
1087
1088
diff view generated by jsdifflib
[PULL 09/12] hw/core/loader: gunzip(): initialize z_stream
[PULL 07/19] target/arm: Convert sme_helper.c to fpst alias
1
From: Vladimir Sementsov-Ogievskiy <vsementsov@yandex-team.ru>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Coverity signals that variable as being used uninitialized. And really,
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
when work with external APIs that's better to zero out the structure,
5
where we set some fields by hand.
6
7
Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@yandex-team.ru>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Maksim Davydov <davydov-max@yandex-team.ru>
5
Message-id: 20241206031224.78525-8-richard.henderson@linaro.org
10
Message-id: 20231017125941.810461-6-vsementsov@yandex-team.ru
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
7
---
13
hw/core/loader.c | 2 +-
8
target/arm/tcg/helper-sme.h | 4 ++--
14
1 file changed, 1 insertion(+), 1 deletion(-)
9
target/arm/tcg/sme_helper.c | 8 ++++----
10
2 files changed, 6 insertions(+), 6 deletions(-)
15
11
16
diff --git a/hw/core/loader.c b/hw/core/loader.c
12
diff --git a/target/arm/tcg/helper-sme.h b/target/arm/tcg/helper-sme.h
17
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/core/loader.c
14
--- a/target/arm/tcg/helper-sme.h
19
+++ b/hw/core/loader.c
15
+++ b/target/arm/tcg/helper-sme.h
20
@@ -XXX,XX +XXX,XX @@ static void zfree(void *x, void *addr)
16
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(sme_addva_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
21
17
DEF_HELPER_FLAGS_7(sme_fmopa_h, TCG_CALL_NO_RWG,
22
ssize_t gunzip(void *dst, size_t dstlen, uint8_t *src, size_t srclen)
18
void, ptr, ptr, ptr, ptr, ptr, env, i32)
19
DEF_HELPER_FLAGS_7(sme_fmopa_s, TCG_CALL_NO_RWG,
20
- void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
21
+ void, ptr, ptr, ptr, ptr, ptr, fpst, i32)
22
DEF_HELPER_FLAGS_7(sme_fmopa_d, TCG_CALL_NO_RWG,
23
- void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
24
+ void, ptr, ptr, ptr, ptr, ptr, fpst, i32)
25
DEF_HELPER_FLAGS_7(sme_bfmopa, TCG_CALL_NO_RWG,
26
void, ptr, ptr, ptr, ptr, ptr, env, i32)
27
DEF_HELPER_FLAGS_6(sme_smopa_s, TCG_CALL_NO_RWG,
28
diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c
29
index XXXXXXX..XXXXXXX 100644
30
--- a/target/arm/tcg/sme_helper.c
31
+++ b/target/arm/tcg/sme_helper.c
32
@@ -XXX,XX +XXX,XX @@ void HELPER(sme_addva_d)(void *vzda, void *vzn, void *vpn,
33
}
34
35
void HELPER(sme_fmopa_s)(void *vza, void *vzn, void *vzm, void *vpn,
36
- void *vpm, void *vst, uint32_t desc)
37
+ void *vpm, float_status *fpst_in, uint32_t desc)
23
{
38
{
24
- z_stream s;
39
intptr_t row, col, oprsz = simd_maxsz(desc);
25
+ z_stream s = {};
40
uint32_t neg = simd_data(desc) << 31;
26
ssize_t dstbytes;
41
@@ -XXX,XX +XXX,XX @@ void HELPER(sme_fmopa_s)(void *vza, void *vzn, void *vzm, void *vpn,
27
int r, i, flags;
42
* update the cumulative fp exception status. It also produces
43
* default nans.
44
*/
45
- fpst = *(float_status *)vst;
46
+ fpst = *fpst_in;
47
set_default_nan_mode(true, &fpst);
48
49
for (row = 0; row < oprsz; ) {
50
@@ -XXX,XX +XXX,XX @@ void HELPER(sme_fmopa_s)(void *vza, void *vzn, void *vzm, void *vpn,
51
}
52
53
void HELPER(sme_fmopa_d)(void *vza, void *vzn, void *vzm, void *vpn,
54
- void *vpm, void *vst, uint32_t desc)
55
+ void *vpm, float_status *fpst_in, uint32_t desc)
56
{
57
intptr_t row, col, oprsz = simd_oprsz(desc) / 8;
58
uint64_t neg = (uint64_t)simd_data(desc) << 63;
59
uint64_t *za = vza, *zn = vzn, *zm = vzm;
60
uint8_t *pn = vpn, *pm = vpm;
61
- float_status fpst = *(float_status *)vst;
62
+ float_status fpst = *fpst_in;
63
64
set_default_nan_mode(true, &fpst);
28
65
29
--
66
--
30
2.34.1
67
2.34.1
diff view generated by jsdifflib
New patch
[PULL 08/19] target/arm: Convert vec_helper.c to use env alias
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Allow the helpers to receive CPUARMState* directly
4
instead of via void*.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Message-id: 20241206031224.78525-9-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/helper.h | 12 ++++++------
12
target/arm/tcg/helper-a64.h | 2 +-
13
target/arm/tcg/vec_helper.c | 21 +++++++--------------
14
3 files changed, 14 insertions(+), 21 deletions(-)
15
16
diff --git a/target/arm/helper.h b/target/arm/helper.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/helper.h
19
+++ b/target/arm/helper.h
20
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(gvec_suqadd_d, TCG_CALL_NO_RWG,
21
void, ptr, ptr, ptr, ptr, i32)
22
23
DEF_HELPER_FLAGS_5(gvec_fmlal_a32, TCG_CALL_NO_RWG,
24
- void, ptr, ptr, ptr, ptr, i32)
25
+ void, ptr, ptr, ptr, env, i32)
26
DEF_HELPER_FLAGS_5(gvec_fmlal_a64, TCG_CALL_NO_RWG,
27
- void, ptr, ptr, ptr, ptr, i32)
28
+ void, ptr, ptr, ptr, env, i32)
29
DEF_HELPER_FLAGS_5(gvec_fmlal_idx_a32, TCG_CALL_NO_RWG,
30
- void, ptr, ptr, ptr, ptr, i32)
31
+ void, ptr, ptr, ptr, env, i32)
32
DEF_HELPER_FLAGS_5(gvec_fmlal_idx_a64, TCG_CALL_NO_RWG,
33
- void, ptr, ptr, ptr, ptr, i32)
34
+ void, ptr, ptr, ptr, env, i32)
35
36
DEF_HELPER_FLAGS_2(frint32_s, TCG_CALL_NO_RWG, f32, f32, fpst)
37
DEF_HELPER_FLAGS_2(frint64_s, TCG_CALL_NO_RWG, f32, f32, fpst)
38
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(sve2_sqrdmulh_idx_d, TCG_CALL_NO_RWG,
39
void, ptr, ptr, ptr, i32)
40
41
DEF_HELPER_FLAGS_6(sve2_fmlal_zzzw_s, TCG_CALL_NO_RWG,
42
- void, ptr, ptr, ptr, ptr, ptr, i32)
43
+ void, ptr, ptr, ptr, ptr, env, i32)
44
DEF_HELPER_FLAGS_6(sve2_fmlal_zzxw_s, TCG_CALL_NO_RWG,
45
- void, ptr, ptr, ptr, ptr, ptr, i32)
46
+ void, ptr, ptr, ptr, ptr, env, i32)
47
48
DEF_HELPER_FLAGS_4(gvec_xar_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
49
50
diff --git a/target/arm/tcg/helper-a64.h b/target/arm/tcg/helper-a64.h
51
index XXXXXXX..XXXXXXX 100644
52
--- a/target/arm/tcg/helper-a64.h
53
+++ b/target/arm/tcg/helper-a64.h
54
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(vfp_cmps_a64, i64, f32, f32, fpst)
55
DEF_HELPER_3(vfp_cmpes_a64, i64, f32, f32, fpst)
56
DEF_HELPER_3(vfp_cmpd_a64, i64, f64, f64, fpst)
57
DEF_HELPER_3(vfp_cmped_a64, i64, f64, f64, fpst)
58
-DEF_HELPER_FLAGS_4(simd_tblx, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
59
+DEF_HELPER_FLAGS_4(simd_tblx, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
60
DEF_HELPER_FLAGS_3(vfp_mulxs, TCG_CALL_NO_RWG, f32, f32, f32, fpst)
61
DEF_HELPER_FLAGS_3(vfp_mulxd, TCG_CALL_NO_RWG, f64, f64, f64, fpst)
62
DEF_HELPER_FLAGS_3(neon_ceq_f64, TCG_CALL_NO_RWG, i64, i64, i64, fpst)
63
diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c
64
index XXXXXXX..XXXXXXX 100644
65
--- a/target/arm/tcg/vec_helper.c
66
+++ b/target/arm/tcg/vec_helper.c
67
@@ -XXX,XX +XXX,XX @@ static void do_fmlal(float32 *d, void *vn, void *vm, float_status *fpst,
68
}
69
70
void HELPER(gvec_fmlal_a32)(void *vd, void *vn, void *vm,
71
- void *venv, uint32_t desc)
72
+ CPUARMState *env, uint32_t desc)
73
{
74
- CPUARMState *env = venv;
75
do_fmlal(vd, vn, vm, &env->vfp.standard_fp_status, desc,
76
get_flush_inputs_to_zero(&env->vfp.fp_status_f16));
77
}
78
79
void HELPER(gvec_fmlal_a64)(void *vd, void *vn, void *vm,
80
- void *venv, uint32_t desc)
81
+ CPUARMState *env, uint32_t desc)
82
{
83
- CPUARMState *env = venv;
84
do_fmlal(vd, vn, vm, &env->vfp.fp_status, desc,
85
get_flush_inputs_to_zero(&env->vfp.fp_status_f16));
86
}
87
88
void HELPER(sve2_fmlal_zzzw_s)(void *vd, void *vn, void *vm, void *va,
89
- void *venv, uint32_t desc)
90
+ CPUARMState *env, uint32_t desc)
91
{
92
intptr_t i, oprsz = simd_oprsz(desc);
93
uint16_t negn = extract32(desc, SIMD_DATA_SHIFT, 1) << 15;
94
intptr_t sel = extract32(desc, SIMD_DATA_SHIFT + 1, 1) * sizeof(float16);
95
- CPUARMState *env = venv;
96
float_status *status = &env->vfp.fp_status;
97
bool fz16 = get_flush_inputs_to_zero(&env->vfp.fp_status_f16);
98
99
@@ -XXX,XX +XXX,XX @@ static void do_fmlal_idx(float32 *d, void *vn, void *vm, float_status *fpst,
100
}
101
102
void HELPER(gvec_fmlal_idx_a32)(void *vd, void *vn, void *vm,
103
- void *venv, uint32_t desc)
104
+ CPUARMState *env, uint32_t desc)
105
{
106
- CPUARMState *env = venv;
107
do_fmlal_idx(vd, vn, vm, &env->vfp.standard_fp_status, desc,
108
get_flush_inputs_to_zero(&env->vfp.fp_status_f16));
109
}
110
111
void HELPER(gvec_fmlal_idx_a64)(void *vd, void *vn, void *vm,
112
- void *venv, uint32_t desc)
113
+ CPUARMState *env, uint32_t desc)
114
{
115
- CPUARMState *env = venv;
116
do_fmlal_idx(vd, vn, vm, &env->vfp.fp_status, desc,
117
get_flush_inputs_to_zero(&env->vfp.fp_status_f16));
118
}
119
120
void HELPER(sve2_fmlal_zzxw_s)(void *vd, void *vn, void *vm, void *va,
121
- void *venv, uint32_t desc)
122
+ CPUARMState *env, uint32_t desc)
123
{
124
intptr_t i, j, oprsz = simd_oprsz(desc);
125
uint16_t negn = extract32(desc, SIMD_DATA_SHIFT, 1) << 15;
126
intptr_t sel = extract32(desc, SIMD_DATA_SHIFT + 1, 1) * sizeof(float16);
127
intptr_t idx = extract32(desc, SIMD_DATA_SHIFT + 2, 3) * sizeof(float16);
128
- CPUARMState *env = venv;
129
float_status *status = &env->vfp.fp_status;
130
bool fz16 = get_flush_inputs_to_zero(&env->vfp.fp_status_f16);
131
132
@@ -XXX,XX +XXX,XX @@ DO_VRINT_RMODE(gvec_vrint_rm_s, helper_rints, uint32_t)
133
#undef DO_VRINT_RMODE
134
135
#ifdef TARGET_AARCH64
136
-void HELPER(simd_tblx)(void *vd, void *vm, void *venv, uint32_t desc)
137
+void HELPER(simd_tblx)(void *vd, void *vm, CPUARMState *env, uint32_t desc)
138
{
139
const uint8_t *indices = vm;
140
- CPUARMState *env = venv;
141
size_t oprsz = simd_oprsz(desc);
142
uint32_t rn = extract32(desc, SIMD_DATA_SHIFT, 5);
143
bool is_tbx = extract32(desc, SIMD_DATA_SHIFT + 5, 1);
144
--
145
2.34.1
146
147
diff view generated by jsdifflib
New patch
[PULL 09/19] target/arm: Convert neon_helper.c to use env alias
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
Message-id: 20241206031224.78525-10-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/helper.h | 56 ++++++++++++++++++------------------
9
target/arm/tcg/neon_helper.c | 6 ++--
10
2 files changed, 30 insertions(+), 32 deletions(-)
11
12
diff --git a/target/arm/helper.h b/target/arm/helper.h
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/helper.h
15
+++ b/target/arm/helper.h
16
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(neon_qrshl_u32, i32, env, i32, i32)
17
DEF_HELPER_3(neon_qrshl_s32, i32, env, i32, i32)
18
DEF_HELPER_3(neon_qrshl_u64, i64, env, i64, i64)
19
DEF_HELPER_3(neon_qrshl_s64, i64, env, i64, i64)
20
-DEF_HELPER_FLAGS_5(neon_sqshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
21
-DEF_HELPER_FLAGS_5(neon_sqshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
22
-DEF_HELPER_FLAGS_5(neon_sqshl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
23
-DEF_HELPER_FLAGS_5(neon_sqshl_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
24
-DEF_HELPER_FLAGS_5(neon_uqshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
25
-DEF_HELPER_FLAGS_5(neon_uqshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
26
-DEF_HELPER_FLAGS_5(neon_uqshl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
27
-DEF_HELPER_FLAGS_5(neon_uqshl_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
28
-DEF_HELPER_FLAGS_5(neon_sqrshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
29
-DEF_HELPER_FLAGS_5(neon_sqrshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
30
-DEF_HELPER_FLAGS_5(neon_sqrshl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
31
-DEF_HELPER_FLAGS_5(neon_sqrshl_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
32
-DEF_HELPER_FLAGS_5(neon_uqrshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
33
-DEF_HELPER_FLAGS_5(neon_uqrshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
34
-DEF_HELPER_FLAGS_5(neon_uqrshl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
35
-DEF_HELPER_FLAGS_5(neon_uqrshl_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
36
-DEF_HELPER_FLAGS_4(neon_sqshli_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
37
-DEF_HELPER_FLAGS_4(neon_sqshli_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
38
-DEF_HELPER_FLAGS_4(neon_sqshli_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
39
-DEF_HELPER_FLAGS_4(neon_sqshli_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
40
-DEF_HELPER_FLAGS_4(neon_uqshli_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
41
-DEF_HELPER_FLAGS_4(neon_uqshli_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
42
-DEF_HELPER_FLAGS_4(neon_uqshli_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
43
-DEF_HELPER_FLAGS_4(neon_uqshli_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
44
-DEF_HELPER_FLAGS_4(neon_sqshlui_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
45
-DEF_HELPER_FLAGS_4(neon_sqshlui_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
46
-DEF_HELPER_FLAGS_4(neon_sqshlui_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
47
-DEF_HELPER_FLAGS_4(neon_sqshlui_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
48
+DEF_HELPER_FLAGS_5(neon_sqshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
49
+DEF_HELPER_FLAGS_5(neon_sqshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
50
+DEF_HELPER_FLAGS_5(neon_sqshl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
51
+DEF_HELPER_FLAGS_5(neon_sqshl_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
52
+DEF_HELPER_FLAGS_5(neon_uqshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
53
+DEF_HELPER_FLAGS_5(neon_uqshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
54
+DEF_HELPER_FLAGS_5(neon_uqshl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
55
+DEF_HELPER_FLAGS_5(neon_uqshl_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
56
+DEF_HELPER_FLAGS_5(neon_sqrshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
57
+DEF_HELPER_FLAGS_5(neon_sqrshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
58
+DEF_HELPER_FLAGS_5(neon_sqrshl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
59
+DEF_HELPER_FLAGS_5(neon_sqrshl_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
60
+DEF_HELPER_FLAGS_5(neon_uqrshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
61
+DEF_HELPER_FLAGS_5(neon_uqrshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
62
+DEF_HELPER_FLAGS_5(neon_uqrshl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
63
+DEF_HELPER_FLAGS_5(neon_uqrshl_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
64
+DEF_HELPER_FLAGS_4(neon_sqshli_b, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
65
+DEF_HELPER_FLAGS_4(neon_sqshli_h, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
66
+DEF_HELPER_FLAGS_4(neon_sqshli_s, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
67
+DEF_HELPER_FLAGS_4(neon_sqshli_d, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
68
+DEF_HELPER_FLAGS_4(neon_uqshli_b, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
69
+DEF_HELPER_FLAGS_4(neon_uqshli_h, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
70
+DEF_HELPER_FLAGS_4(neon_uqshli_s, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
71
+DEF_HELPER_FLAGS_4(neon_uqshli_d, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
72
+DEF_HELPER_FLAGS_4(neon_sqshlui_b, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
73
+DEF_HELPER_FLAGS_4(neon_sqshlui_h, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
74
+DEF_HELPER_FLAGS_4(neon_sqshlui_s, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
75
+DEF_HELPER_FLAGS_4(neon_sqshlui_d, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
76
77
DEF_HELPER_FLAGS_4(gvec_srshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
78
DEF_HELPER_FLAGS_4(gvec_srshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
79
diff --git a/target/arm/tcg/neon_helper.c b/target/arm/tcg/neon_helper.c
80
index XXXXXXX..XXXXXXX 100644
81
--- a/target/arm/tcg/neon_helper.c
82
+++ b/target/arm/tcg/neon_helper.c
83
@@ -XXX,XX +XXX,XX @@ void HELPER(name)(void *vd, void *vn, void *vm, uint32_t desc) \
84
}
85
86
#define NEON_GVEC_VOP2_ENV(name, vtype) \
87
-void HELPER(name)(void *vd, void *vn, void *vm, void *venv, uint32_t desc) \
88
+void HELPER(name)(void *vd, void *vn, void *vm, CPUARMState *env, uint32_t desc) \
89
{ \
90
intptr_t i, opr_sz = simd_oprsz(desc); \
91
vtype *d = vd, *n = vn, *m = vm; \
92
- CPUARMState *env = venv; \
93
for (i = 0; i < opr_sz / sizeof(vtype); i++) { \
94
NEON_FN(d[i], n[i], m[i]); \
95
} \
96
@@ -XXX,XX +XXX,XX @@ void HELPER(name)(void *vd, void *vn, void *vm, void *venv, uint32_t desc) \
97
}
98
99
#define NEON_GVEC_VOP2i_ENV(name, vtype) \
100
-void HELPER(name)(void *vd, void *vn, void *venv, uint32_t desc) \
101
+void HELPER(name)(void *vd, void *vn, CPUARMState *env, uint32_t desc) \
102
{ \
103
intptr_t i, opr_sz = simd_oprsz(desc); \
104
int imm = simd_data(desc); \
105
vtype *d = vd, *n = vn; \
106
- CPUARMState *env = venv; \
107
for (i = 0; i < opr_sz / sizeof(vtype); i++) { \
108
NEON_FN(d[i], n[i], imm); \
109
} \
110
--
111
2.34.1
112
113
diff view generated by jsdifflib
[PULL 12/12] target/arm: Fix A64 LDRA immediate decode
[PULL 10/19] target/arm: Use float_status in helper_fcvtx_f64_to_f32
1
In commit be23a049 in the conversion to decodetree we broke the
1
From: Richard Henderson <richard.henderson@linaro.org>
2
decoding of the immediate value in the LDRA instruction. This should
3
be a 10 bit signed value that is scaled by 8, but in the conversion
4
we incorrectly ended up scaling it only by 2. Fix the scaling
5
factor.
6
2
7
Cc: qemu-stable@nongnu.org
3
Pass float_status not env to match other functions.
8
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1970
4
9
Fixes: be23a049 ("target/arm: Convert load (pointer auth) insns to decodetree")
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Message-id: 20241206031952.78776-2-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
12
Message-id: 20231106113445.1163063-1-peter.maydell@linaro.org
13
---
9
---
14
target/arm/tcg/translate.h | 5 +++++
10
target/arm/tcg/helper-a64.h | 2 +-
15
target/arm/tcg/a64.decode | 2 +-
11
target/arm/tcg/helper-a64.c | 3 +--
16
2 files changed, 6 insertions(+), 1 deletion(-)
12
target/arm/tcg/translate-a64.c | 2 +-
13
3 files changed, 3 insertions(+), 4 deletions(-)
17
14
18
diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h
15
diff --git a/target/arm/tcg/helper-a64.h b/target/arm/tcg/helper-a64.h
19
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/tcg/translate.h
17
--- a/target/arm/tcg/helper-a64.h
21
+++ b/target/arm/tcg/translate.h
18
+++ b/target/arm/tcg/helper-a64.h
22
@@ -XXX,XX +XXX,XX @@ static inline int times_4(DisasContext *s, int x)
19
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(rsqrtsf_f64, TCG_CALL_NO_RWG, f64, f64, f64, fpst)
23
return x * 4;
20
DEF_HELPER_FLAGS_2(frecpx_f64, TCG_CALL_NO_RWG, f64, f64, fpst)
21
DEF_HELPER_FLAGS_2(frecpx_f32, TCG_CALL_NO_RWG, f32, f32, fpst)
22
DEF_HELPER_FLAGS_2(frecpx_f16, TCG_CALL_NO_RWG, f16, f16, fpst)
23
-DEF_HELPER_FLAGS_2(fcvtx_f64_to_f32, TCG_CALL_NO_RWG, f32, f64, env)
24
+DEF_HELPER_FLAGS_2(fcvtx_f64_to_f32, TCG_CALL_NO_RWG, f32, f64, fpst)
25
DEF_HELPER_FLAGS_3(crc32_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32)
26
DEF_HELPER_FLAGS_3(crc32c_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32)
27
DEF_HELPER_FLAGS_3(advsimd_maxh, TCG_CALL_NO_RWG, f16, f16, f16, fpst)
28
diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c
29
index XXXXXXX..XXXXXXX 100644
30
--- a/target/arm/tcg/helper-a64.c
31
+++ b/target/arm/tcg/helper-a64.c
32
@@ -XXX,XX +XXX,XX @@ float64 HELPER(frecpx_f64)(float64 a, float_status *fpst)
33
}
24
}
34
}
25
35
26
+static inline int times_8(DisasContext *s, int x)
36
-float32 HELPER(fcvtx_f64_to_f32)(float64 a, CPUARMState *env)
27
+{
37
+float32 HELPER(fcvtx_f64_to_f32)(float64 a, float_status *fpst)
28
+ return x * 8;
29
+}
30
+
31
static inline int times_2_plus_1(DisasContext *s, int x)
32
{
38
{
33
return x * 2 + 1;
39
float32 r;
34
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
40
- float_status *fpst = &env->vfp.fp_status;
41
int old = get_float_rounding_mode(fpst);
42
43
set_float_rounding_mode(float_round_to_odd, fpst);
44
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
35
index XXXXXXX..XXXXXXX 100644
45
index XXXXXXX..XXXXXXX 100644
36
--- a/target/arm/tcg/a64.decode
46
--- a/target/arm/tcg/translate-a64.c
37
+++ b/target/arm/tcg/a64.decode
47
+++ b/target/arm/tcg/translate-a64.c
38
@@ -XXX,XX +XXX,XX @@ LDAPR sz:2 111 0 00 1 0 1 11111 1100 00 rn:5 rt:5
48
@@ -XXX,XX +XXX,XX @@ static void gen_fcvtxn_sd(TCGv_i64 d, TCGv_i64 n)
39
# Load/store register (pointer authentication)
49
* with von Neumann rounding (round to odd)
40
50
*/
41
# LDRA immediate is 10 bits signed and scaled, but the bits aren't all contiguous
51
TCGv_i32 tmp = tcg_temp_new_i32();
42
-%ldra_imm 22:s1 12:9 !function=times_2
52
- gen_helper_fcvtx_f64_to_f32(tmp, n, tcg_env);
43
+%ldra_imm 22:s1 12:9 !function=times_8
53
+ gen_helper_fcvtx_f64_to_f32(tmp, n, fpstatus_ptr(FPST_FPCR));
44
54
tcg_gen_extu_i32_i64(d, tmp);
45
LDRA 11 111 0 00 m:1 . 1 ......... w:1 1 rn:5 rt:5 imm=%ldra_imm
55
}
46
56
47
--
57
--
48
2.34.1
58
2.34.1
49
59
50
60
diff view generated by jsdifflib
[PULL 11/12] hw/arm/vexpress-a9: Remove useless mapping of RAM at address 0
[PULL 11/19] target/arm: Use float_status in helper_vfp_fcvt{ds,sd}
1
On the vexpress-a9 board we try to map both RAM and flash to address 0,
1
From: Richard Henderson <richard.henderson@linaro.org>
2
as seen in "info mtree":
3
2
4
address-space: memory
3
Pass float_status not env to match other functions.
5
0000000000000000-ffffffffffffffff (prio 0, i/o): system
6
0000000000000000-0000000003ffffff (prio 0, romd): alias vexpress.flashalias @vexpress.flash0 0000000000000000-0000000003ffffff
7
0000000000000000-0000000003ffffff (prio 0, ram): alias vexpress.lowmem @vexpress.highmem 0000000000000000-0000000003ffffff
8
0000000010000000-0000000010000fff (prio 0, i/o): arm-sysctl
9
0000000010004000-0000000010004fff (prio 0, i/o): pl041
10
(etc)
11
4
12
The flash "wins" and the RAM mapping is useless (but also harmless).
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Message-id: 20241206031952.78776-3-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/helper.h | 4 ++--
11
target/arm/tcg/translate-a64.c | 15 ++++++++++-----
12
target/arm/tcg/translate-vfp.c | 4 ++--
13
target/arm/vfp_helper.c | 8 ++++----
14
4 files changed, 18 insertions(+), 13 deletions(-)
13
15
14
This happened as a result of commit 6ec1588e in 2014, which changed
16
diff --git a/target/arm/helper.h b/target/arm/helper.h
15
"we always map the RAM to the low addresses for vexpress-a9" to "we
16
always map flash in the low addresses", but forgot to stop mapping
17
the RAM.
18
19
In real hardware, this low part of memory is remappable, both at
20
runtime by the guest writing to a control register, and configurably
21
as to what you get out of reset -- you can have the first flash
22
device, or the second, or the DDR2 RAM, or the external AXI bus
23
(which for QEMU means "nothing there"). In an ideal world we would
24
support that remapping both at runtime and via a machine property to
25
select the out-of-reset behaviour.
26
27
Pending anybody caring enough to implement the full remapping
28
behaviour:
29
* remove the useless mapped-but-inaccessible lowram MR
30
* document that QEMU doesn't support remapping of low memory
31
32
Fixes: 6ec1588e ("hw/arm/vexpress: Alias NOR flash at 0 for vexpress-a9")
33
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1761
34
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
35
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
36
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
37
Message-id: 20231103185602.875849-1-peter.maydell@linaro.org
38
---
39
docs/system/arm/vexpress.rst | 3 +++
40
hw/arm/vexpress.c | 14 +++-----------
41
2 files changed, 6 insertions(+), 11 deletions(-)
42
43
diff --git a/docs/system/arm/vexpress.rst b/docs/system/arm/vexpress.rst
44
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
45
--- a/docs/system/arm/vexpress.rst
18
--- a/target/arm/helper.h
46
+++ b/docs/system/arm/vexpress.rst
19
+++ b/target/arm/helper.h
47
@@ -XXX,XX +XXX,XX @@ Other differences between the hardware and the QEMU model:
20
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(vfp_cmpeh, void, f16, f16, env)
48
``vexpress-a15``, and have IRQs from 40 upwards. If a dtb is
21
DEF_HELPER_3(vfp_cmpes, void, f32, f32, env)
49
provided on the command line then QEMU will edit it to include
22
DEF_HELPER_3(vfp_cmped, void, f64, f64, env)
50
suitable entries describing these transports for the guest.
23
51
+- QEMU does not currently support either dynamic or static remapping
24
-DEF_HELPER_2(vfp_fcvtds, f64, f32, env)
52
+ of the area of memory at address 0: it is always mapped to alias
25
-DEF_HELPER_2(vfp_fcvtsd, f32, f64, env)
53
+ the first flash bank
26
+DEF_HELPER_2(vfp_fcvtds, f64, f32, fpst)
54
27
+DEF_HELPER_2(vfp_fcvtsd, f32, f64, fpst)
55
Booting a Linux kernel
28
DEF_HELPER_FLAGS_2(bfcvt, TCG_CALL_NO_RWG, i32, f32, fpst)
56
----------------------
29
DEF_HELPER_FLAGS_2(bfcvt_pair, TCG_CALL_NO_RWG, i32, i64, fpst)
57
diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
30
31
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
58
index XXXXXXX..XXXXXXX 100644
32
index XXXXXXX..XXXXXXX 100644
59
--- a/hw/arm/vexpress.c
33
--- a/target/arm/tcg/translate-a64.c
60
+++ b/hw/arm/vexpress.c
34
+++ b/target/arm/tcg/translate-a64.c
61
@@ -XXX,XX +XXX,XX @@ struct VexpressMachineState {
35
@@ -XXX,XX +XXX,XX @@ static bool trans_FCVT_s_ds(DisasContext *s, arg_rr *a)
62
MemoryRegion vram;
36
if (fp_access_check(s)) {
63
MemoryRegion sram;
37
TCGv_i32 tcg_rn = read_fp_sreg(s, a->rn);
64
MemoryRegion flashalias;
38
TCGv_i64 tcg_rd = tcg_temp_new_i64();
65
- MemoryRegion lowram;
39
+ TCGv_ptr fpst = fpstatus_ptr(FPST_FPCR);
66
MemoryRegion a15sram;
40
67
bool secure;
41
- gen_helper_vfp_fcvtds(tcg_rd, tcg_rn, tcg_env);
68
bool virt;
42
+ gen_helper_vfp_fcvtds(tcg_rd, tcg_rn, fpst);
69
@@ -XXX,XX +XXX,XX @@ static void a9_daughterboard_init(VexpressMachineState *vms,
43
write_fp_dreg(s, a->rd, tcg_rd);
44
}
45
return true;
46
@@ -XXX,XX +XXX,XX @@ static bool trans_FCVT_s_sd(DisasContext *s, arg_rr *a)
47
if (fp_access_check(s)) {
48
TCGv_i64 tcg_rn = read_fp_dreg(s, a->rn);
49
TCGv_i32 tcg_rd = tcg_temp_new_i32();
50
+ TCGv_ptr fpst = fpstatus_ptr(FPST_FPCR);
51
52
- gen_helper_vfp_fcvtsd(tcg_rd, tcg_rn, tcg_env);
53
+ gen_helper_vfp_fcvtsd(tcg_rd, tcg_rn, fpst);
54
write_fp_sreg(s, a->rd, tcg_rd);
55
}
56
return true;
57
@@ -XXX,XX +XXX,XX @@ static void gen_fcvtn_hs(TCGv_i64 d, TCGv_i64 n)
58
static void gen_fcvtn_sd(TCGv_i64 d, TCGv_i64 n)
70
{
59
{
71
MachineState *machine = MACHINE(vms);
60
TCGv_i32 tmp = tcg_temp_new_i32();
72
MemoryRegion *sysmem = get_system_memory();
61
- gen_helper_vfp_fcvtsd(tmp, n, tcg_env);
73
- ram_addr_t low_ram_size;
62
+ TCGv_ptr fpst = fpstatus_ptr(FPST_FPCR);
74
63
+
75
if (ram_size > 0x40000000) {
64
+ gen_helper_vfp_fcvtsd(tmp, n, fpst);
76
/* 1GB is the maximum the address space permits */
65
tcg_gen_extu_i32_i64(d, tmp);
77
@@ -XXX,XX +XXX,XX @@ static void a9_daughterboard_init(VexpressMachineState *vms,
66
}
78
exit(1);
67
68
@@ -XXX,XX +XXX,XX @@ static bool trans_FCVTL_v(DisasContext *s, arg_qrr_e *a)
69
* The only instruction like this is FCVTL.
70
*/
71
int pass;
72
+ TCGv_ptr fpst;
73
74
if (!fp_access_check(s)) {
75
return true;
79
}
76
}
80
77
81
- low_ram_size = ram_size;
78
+ fpst = fpstatus_ptr(FPST_FPCR);
82
- if (low_ram_size > 0x4000000) {
79
if (a->esz == MO_64) {
83
- low_ram_size = 0x4000000;
80
/* 32 -> 64 bit fp conversion */
84
- }
81
TCGv_i64 tcg_res[2];
85
- /* RAM is from 0x60000000 upwards. The bottom 64MB of the
82
@@ -XXX,XX +XXX,XX @@ static bool trans_FCVTL_v(DisasContext *s, arg_qrr_e *a)
86
+ /*
83
for (pass = 0; pass < 2; pass++) {
87
+ * RAM is from 0x60000000 upwards. The bottom 64MB of the
84
tcg_res[pass] = tcg_temp_new_i64();
88
* address space should in theory be remappable to various
85
read_vec_element_i32(s, tcg_op, a->rn, srcelt + pass, MO_32);
89
- * things including ROM or RAM; we always map the RAM there.
86
- gen_helper_vfp_fcvtds(tcg_res[pass], tcg_op, tcg_env);
90
+ * things including ROM or RAM; we always map the flash there.
87
+ gen_helper_vfp_fcvtds(tcg_res[pass], tcg_op, fpst);
91
*/
88
}
92
- memory_region_init_alias(&vms->lowram, NULL, "vexpress.lowmem",
89
for (pass = 0; pass < 2; pass++) {
93
- machine->ram, 0, low_ram_size);
90
write_vec_element(s, tcg_res[pass], a->rd, pass, MO_64);
94
- memory_region_add_subregion(sysmem, 0x0, &vms->lowram);
91
@@ -XXX,XX +XXX,XX @@ static bool trans_FCVTL_v(DisasContext *s, arg_qrr_e *a)
95
memory_region_add_subregion(sysmem, 0x60000000, machine->ram);
92
/* 16 -> 32 bit fp conversion */
96
93
int srcelt = a->q ? 4 : 0;
97
/* 0x1e000000 A9MPCore (SCU) private memory region */
94
TCGv_i32 tcg_res[4];
95
- TCGv_ptr fpst = fpstatus_ptr(FPST_FPCR);
96
TCGv_i32 ahp = get_ahp_flag();
97
98
for (pass = 0; pass < 4; pass++) {
99
diff --git a/target/arm/tcg/translate-vfp.c b/target/arm/tcg/translate-vfp.c
100
index XXXXXXX..XXXXXXX 100644
101
--- a/target/arm/tcg/translate-vfp.c
102
+++ b/target/arm/tcg/translate-vfp.c
103
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_sp *a)
104
vm = tcg_temp_new_i32();
105
vd = tcg_temp_new_i64();
106
vfp_load_reg32(vm, a->vm);
107
- gen_helper_vfp_fcvtds(vd, vm, tcg_env);
108
+ gen_helper_vfp_fcvtds(vd, vm, fpstatus_ptr(FPST_FPCR));
109
vfp_store_reg64(vd, a->vd);
110
return true;
111
}
112
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_dp *a)
113
vd = tcg_temp_new_i32();
114
vm = tcg_temp_new_i64();
115
vfp_load_reg64(vm, a->vm);
116
- gen_helper_vfp_fcvtsd(vd, vm, tcg_env);
117
+ gen_helper_vfp_fcvtsd(vd, vm, fpstatus_ptr(FPST_FPCR));
118
vfp_store_reg32(vd, a->vd);
119
return true;
120
}
121
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
122
index XXXXXXX..XXXXXXX 100644
123
--- a/target/arm/vfp_helper.c
124
+++ b/target/arm/vfp_helper.c
125
@@ -XXX,XX +XXX,XX @@ FLOAT_CONVS(ui, d, float64, 64, u)
126
#undef FLOAT_CONVS
127
128
/* floating point conversion */
129
-float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env)
130
+float64 VFP_HELPER(fcvtd, s)(float32 x, float_status *status)
131
{
132
- return float32_to_float64(x, &env->vfp.fp_status);
133
+ return float32_to_float64(x, status);
134
}
135
136
-float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
137
+float32 VFP_HELPER(fcvts, d)(float64 x, float_status *status)
138
{
139
- return float64_to_float32(x, &env->vfp.fp_status);
140
+ return float64_to_float32(x, status);
141
}
142
143
uint32_t HELPER(bfcvt)(float32 x, float_status *status)
98
--
144
--
99
2.34.1
145
2.34.1
100
146
101
147
diff view generated by jsdifflib
[PULL 02/12] tests/qtest/bios-tables-test: Allow changes to virt SPCR and DBG2
[PULL 12/19] target/arm: Implement fine-grained-trap handling for FEAT_XS
1
Allow changes to the virt board SPCR and DBG2 -- we are going to fix
1
FEAT_XS introduces a set of new TLBI maintenance instructions with an
2
an error in the UART descriptions there.
2
"nXS" qualifier. These behave like the stardard ones except that
3
they do not wait for memory accesses with the XS attribute to
4
complete. They have an interaction with the fine-grained-trap
5
handling: the FGT bits that a hypervisor can use to trap TLBI
6
maintenance instructions normally trap also the nXS variants, but the
7
hypervisor can elect to not trap the nXS variants by setting
8
HCRX_EL2.FGTnXS to 1.
9
10
Add support to our FGT mechanism for these TLBI bits. For each
11
TLBI-trapping FGT bit we define, for example:
12
* FGT_TLBIVAE1 -- the same value we do at present for the
13
normal variant of the insn
14
* FGT_TLBIVAE1NXS -- for the nXS qualified insn; the value of
15
this enum has an NXS bit ORed into it
16
17
In access_check_cp_reg() we can then ignore the trap bit for an
18
access where ri->fgt has the NXS bit set and HCRX_EL2.FGTnXS is 1.
3
19
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
22
Message-id: 20241211144440.2700268-2-peter.maydell@linaro.org
5
---
23
---
6
tests/qtest/bios-tables-test-allowed-diff.h | 2 ++
24
target/arm/cpregs.h | 72 ++++++++++++++++++++++----------------
7
1 file changed, 2 insertions(+)
25
target/arm/cpu-features.h | 5 +++
26
target/arm/helper.c | 5 ++-
27
target/arm/tcg/op_helper.c | 11 +++++-
28
4 files changed, 61 insertions(+), 32 deletions(-)
8
29
9
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
30
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
10
index XXXXXXX..XXXXXXX 100644
31
index XXXXXXX..XXXXXXX 100644
11
--- a/tests/qtest/bios-tables-test-allowed-diff.h
32
--- a/target/arm/cpregs.h
12
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
33
+++ b/target/arm/cpregs.h
13
@@ -1 +1,3 @@
34
@@ -XXX,XX +XXX,XX @@ FIELD(HDFGWTR_EL2, NBRBCTL, 60, 1)
14
/* List of comma-separated changed AML files to ignore */
35
FIELD(HDFGWTR_EL2, NBRBDATA, 61, 1)
15
+"tests/data/acpi/virt/SPCR",
36
FIELD(HDFGWTR_EL2, NPMSNEVFR_EL1, 62, 1)
16
+"tests/data/acpi/virt/DBG2",
37
38
+FIELD(FGT, NXS, 13, 1) /* Honour HCR_EL2.FGTnXS to suppress FGT */
39
/* Which fine-grained trap bit register to check, if any */
40
FIELD(FGT, TYPE, 10, 3)
41
FIELD(FGT, REV, 9, 1) /* Is bit sense reversed? */
42
@@ -XXX,XX +XXX,XX @@ FIELD(FGT, BITPOS, 0, 6) /* Bit position within the uint64_t */
43
#define DO_REV_BIT(REG, BITNAME) \
44
FGT_##BITNAME = FGT_##REG | FGT_REV | R_##REG##_EL2_##BITNAME##_SHIFT
45
46
+/*
47
+ * The FGT bits for TLBI maintenance instructions accessible at EL1 always
48
+ * affect the "normal" TLBI insns; they affect the corresponding TLBI insns
49
+ * with the nXS qualifier only if HCRX_EL2.FGTnXS is 0. We define e.g.
50
+ * FGT_TLBIVAE1 to use for the normal insn, and FGT_TLBIVAE1NXS to use
51
+ * for the nXS qualified insn.
52
+ */
53
+#define DO_TLBINXS_BIT(REG, BITNAME) \
54
+ FGT_##BITNAME = FGT_##REG | R_##REG##_EL2_##BITNAME##_SHIFT, \
55
+ FGT_##BITNAME##NXS = FGT_##BITNAME | R_FGT_NXS_MASK
56
+
57
typedef enum FGTBit {
58
/*
59
* These bits tell us which register arrays to use:
60
@@ -XXX,XX +XXX,XX @@ typedef enum FGTBit {
61
DO_BIT(HFGITR, ATS1E0W),
62
DO_BIT(HFGITR, ATS1E1RP),
63
DO_BIT(HFGITR, ATS1E1WP),
64
- DO_BIT(HFGITR, TLBIVMALLE1OS),
65
- DO_BIT(HFGITR, TLBIVAE1OS),
66
- DO_BIT(HFGITR, TLBIASIDE1OS),
67
- DO_BIT(HFGITR, TLBIVAAE1OS),
68
- DO_BIT(HFGITR, TLBIVALE1OS),
69
- DO_BIT(HFGITR, TLBIVAALE1OS),
70
- DO_BIT(HFGITR, TLBIRVAE1OS),
71
- DO_BIT(HFGITR, TLBIRVAAE1OS),
72
- DO_BIT(HFGITR, TLBIRVALE1OS),
73
- DO_BIT(HFGITR, TLBIRVAALE1OS),
74
- DO_BIT(HFGITR, TLBIVMALLE1IS),
75
- DO_BIT(HFGITR, TLBIVAE1IS),
76
- DO_BIT(HFGITR, TLBIASIDE1IS),
77
- DO_BIT(HFGITR, TLBIVAAE1IS),
78
- DO_BIT(HFGITR, TLBIVALE1IS),
79
- DO_BIT(HFGITR, TLBIVAALE1IS),
80
- DO_BIT(HFGITR, TLBIRVAE1IS),
81
- DO_BIT(HFGITR, TLBIRVAAE1IS),
82
- DO_BIT(HFGITR, TLBIRVALE1IS),
83
- DO_BIT(HFGITR, TLBIRVAALE1IS),
84
- DO_BIT(HFGITR, TLBIRVAE1),
85
- DO_BIT(HFGITR, TLBIRVAAE1),
86
- DO_BIT(HFGITR, TLBIRVALE1),
87
- DO_BIT(HFGITR, TLBIRVAALE1),
88
- DO_BIT(HFGITR, TLBIVMALLE1),
89
- DO_BIT(HFGITR, TLBIVAE1),
90
- DO_BIT(HFGITR, TLBIASIDE1),
91
- DO_BIT(HFGITR, TLBIVAAE1),
92
- DO_BIT(HFGITR, TLBIVALE1),
93
- DO_BIT(HFGITR, TLBIVAALE1),
94
+ DO_TLBINXS_BIT(HFGITR, TLBIVMALLE1OS),
95
+ DO_TLBINXS_BIT(HFGITR, TLBIVAE1OS),
96
+ DO_TLBINXS_BIT(HFGITR, TLBIASIDE1OS),
97
+ DO_TLBINXS_BIT(HFGITR, TLBIVAAE1OS),
98
+ DO_TLBINXS_BIT(HFGITR, TLBIVALE1OS),
99
+ DO_TLBINXS_BIT(HFGITR, TLBIVAALE1OS),
100
+ DO_TLBINXS_BIT(HFGITR, TLBIRVAE1OS),
101
+ DO_TLBINXS_BIT(HFGITR, TLBIRVAAE1OS),
102
+ DO_TLBINXS_BIT(HFGITR, TLBIRVALE1OS),
103
+ DO_TLBINXS_BIT(HFGITR, TLBIRVAALE1OS),
104
+ DO_TLBINXS_BIT(HFGITR, TLBIVMALLE1IS),
105
+ DO_TLBINXS_BIT(HFGITR, TLBIVAE1IS),
106
+ DO_TLBINXS_BIT(HFGITR, TLBIASIDE1IS),
107
+ DO_TLBINXS_BIT(HFGITR, TLBIVAAE1IS),
108
+ DO_TLBINXS_BIT(HFGITR, TLBIVALE1IS),
109
+ DO_TLBINXS_BIT(HFGITR, TLBIVAALE1IS),
110
+ DO_TLBINXS_BIT(HFGITR, TLBIRVAE1IS),
111
+ DO_TLBINXS_BIT(HFGITR, TLBIRVAAE1IS),
112
+ DO_TLBINXS_BIT(HFGITR, TLBIRVALE1IS),
113
+ DO_TLBINXS_BIT(HFGITR, TLBIRVAALE1IS),
114
+ DO_TLBINXS_BIT(HFGITR, TLBIRVAE1),
115
+ DO_TLBINXS_BIT(HFGITR, TLBIRVAAE1),
116
+ DO_TLBINXS_BIT(HFGITR, TLBIRVALE1),
117
+ DO_TLBINXS_BIT(HFGITR, TLBIRVAALE1),
118
+ DO_TLBINXS_BIT(HFGITR, TLBIVMALLE1),
119
+ DO_TLBINXS_BIT(HFGITR, TLBIVAE1),
120
+ DO_TLBINXS_BIT(HFGITR, TLBIASIDE1),
121
+ DO_TLBINXS_BIT(HFGITR, TLBIVAAE1),
122
+ DO_TLBINXS_BIT(HFGITR, TLBIVALE1),
123
+ DO_TLBINXS_BIT(HFGITR, TLBIVAALE1),
124
DO_BIT(HFGITR, CFPRCTX),
125
DO_BIT(HFGITR, DVPRCTX),
126
DO_BIT(HFGITR, CPPRCTX),
127
diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
128
index XXXXXXX..XXXXXXX 100644
129
--- a/target/arm/cpu-features.h
130
+++ b/target/arm/cpu-features.h
131
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id)
132
return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0;
133
}
134
135
+static inline bool isar_feature_aa64_xs(const ARMISARegisters *id)
136
+{
137
+ return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, XS) != 0;
138
+}
139
+
140
/*
141
* These are the values from APA/API/APA3.
142
* In general these must be compared '>=', per the normal Arm ARM
143
diff --git a/target/arm/helper.c b/target/arm/helper.c
144
index XXXXXXX..XXXXXXX 100644
145
--- a/target/arm/helper.c
146
+++ b/target/arm/helper.c
147
@@ -XXX,XX +XXX,XX @@ static void hcrx_write(CPUARMState *env, const ARMCPRegInfo *ri,
148
valid_mask |= HCRX_TALLINT | HCRX_VINMI | HCRX_VFNMI;
149
}
150
/* FEAT_CMOW adds CMOW */
151
-
152
if (cpu_isar_feature(aa64_cmow, cpu)) {
153
valid_mask |= HCRX_CMOW;
154
}
155
+ /* FEAT_XS adds FGTnXS, FnXS */
156
+ if (cpu_isar_feature(aa64_xs, cpu)) {
157
+ valid_mask |= HCRX_FGTNXS | HCRX_FNXS;
158
+ }
159
160
/* Clear RES0 bits. */
161
env->cp15.hcrx_el2 = value & valid_mask;
162
diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c
163
index XXXXXXX..XXXXXXX 100644
164
--- a/target/arm/tcg/op_helper.c
165
+++ b/target/arm/tcg/op_helper.c
166
@@ -XXX,XX +XXX,XX @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key,
167
unsigned int idx = FIELD_EX32(ri->fgt, FGT, IDX);
168
unsigned int bitpos = FIELD_EX32(ri->fgt, FGT, BITPOS);
169
bool rev = FIELD_EX32(ri->fgt, FGT, REV);
170
+ bool nxs = FIELD_EX32(ri->fgt, FGT, NXS);
171
bool trapbit;
172
173
if (ri->fgt & FGT_EXEC) {
174
@@ -XXX,XX +XXX,XX @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key,
175
trapword = env->cp15.fgt_write[idx];
176
}
177
178
- trapbit = extract64(trapword, bitpos, 1);
179
+ if (nxs && (arm_hcrx_el2_eff(env) & HCRX_FGTNXS)) {
180
+ /*
181
+ * If HCRX_EL2.FGTnXS is 1 then the fine-grained trap for
182
+ * TLBI maintenance insns does *not* apply to the nXS variant.
183
+ */
184
+ trapbit = 0;
185
+ } else {
186
+ trapbit = extract64(trapword, bitpos, 1);
187
+ }
188
if (trapbit != rev) {
189
res = CP_ACCESS_TRAP_EL2;
190
goto fail;
17
--
191
--
18
2.34.1
192
2.34.1
diff view generated by jsdifflib
[PULL 04/12] tests/qtest/bios-tables-test: Update virt SPCR and DBG2 golden references
[PULL 13/19] target/arm: Add ARM_CP_ADD_TLBI_NXS type flag for NXS insns
1
Update the virt SPCR and DBG2 golden reference files to have the
1
All of the TLBI insns with an NXS variant put that variant at the
2
fix for the description of the UART.
2
same encoding but with a CRn field that is one greater than for the
3
original TLBI insn. To avoid having to define every TLBI insn
4
effectively twice, once in the normal way and once in a set of cpreg
5
arrays that are only registered when FEAT_XS is present, we define a
6
new ARM_CP_ADD_TLB_NXS type flag for cpregs. When this flag is set
7
in a cpreg struct and FEAT_XS is present,
8
define_one_arm_cp_reg_with_opaque() will automatically add a second
9
cpreg to the hash table for the TLBI NXS insn with:
10
* the crn+1 encoding
11
* an FGT field that indicates that it should honour HCR_EL2.FGTnXS
12
* a name with the "NXS" suffix
3
13
4
Diffs from iasl:
14
(If there are future TLBI NXS insns that don't use this same
5
15
encoding convention, it is also possible to define them manually.)
6
@@ -XXX,XX +XXX,XX @@
7
/*
8
* Intel ACPI Component Architecture
9
* AML/ASL+ Disassembler version 20200925 (64-bit version)
10
* Copyright (c) 2000 - 2020 Intel Corporation
11
*
12
- * Disassembly of tests/data/acpi/virt/SPCR, Fri Nov 3 14:12:06 2023
13
+ * Disassembly of /tmp/aml-E6YUD2, Fri Nov 3 14:12:06 2023
14
*
15
* ACPI Data Table [SPCR]
16
*
17
* Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
18
*/
19
20
[000h 0000 4] Signature : "SPCR" [Serial Port Console Redirection table]
21
[004h 0004 4] Table Length : 00000050
22
[008h 0008 1] Revision : 02
23
-[009h 0009 1] Checksum : CB
24
+[009h 0009 1] Checksum : B1
25
[00Ah 0010 6] Oem ID : "BOCHS "
26
[010h 0016 8] Oem Table ID : "BXPC "
27
[018h 0024 4] Oem Revision : 00000001
28
[01Ch 0028 4] Asl Compiler ID : "BXPC"
29
[020h 0032 4] Asl Compiler Revision : 00000001
30
31
[024h 0036 1] Interface Type : 03
32
[025h 0037 3] Reserved : 000000
33
34
[028h 0040 12] Serial Port Register : [Generic Address Structure]
35
[028h 0040 1] Space ID : 00 [SystemMemory]
36
-[029h 0041 1] Bit Width : 08
37
+[029h 0041 1] Bit Width : 20
38
[02Ah 0042 1] Bit Offset : 00
39
-[02Bh 0043 1] Encoded Access Width : 01 [Byte Access:8]
40
+[02Bh 0043 1] Encoded Access Width : 03 [DWord Access:32]
41
[02Ch 0044 8] Address : 0000000009000000
42
43
[034h 0052 1] Interrupt Type : 08
44
[035h 0053 1] PCAT-compatible IRQ : 00
45
[036h 0054 4] Interrupt : 00000021
46
[03Ah 0058 1] Baud Rate : 03
47
[03Bh 0059 1] Parity : 00
48
[03Ch 0060 1] Stop Bits : 01
49
[03Dh 0061 1] Flow Control : 02
50
[03Eh 0062 1] Terminal Type : 00
51
[04Ch 0076 1] Reserved : 00
52
[040h 0064 2] PCI Device ID : FFFF
53
[042h 0066 2] PCI Vendor ID : FFFF
54
[044h 0068 1] PCI Bus : 00
55
[045h 0069 1] PCI Device : 00
56
[046h 0070 1] PCI Function : 00
57
[047h 0071 4] PCI Flags : 00000000
58
[04Bh 0075 1] PCI Segment : 00
59
[04Ch 0076 4] Reserved : 00000000
60
61
Raw Table Data: Length 80 (0x50)
62
63
- 0000: 53 50 43 52 50 00 00 00 02 CB 42 4F 43 48 53 20 // SPCRP.....BOCHS
64
+ 0000: 53 50 43 52 50 00 00 00 02 B1 42 4F 43 48 53 20 // SPCRP.....BOCHS
65
0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC
66
- 0020: 01 00 00 00 03 00 00 00 00 08 00 01 00 00 00 09 // ................
67
+ 0020: 01 00 00 00 03 00 00 00 00 20 00 03 00 00 00 09 // ......... ......
68
0030: 00 00 00 00 08 00 21 00 00 00 03 00 01 02 00 00 // ......!.........
69
0040: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00 // ................
70
71
@@ -XXX,XX +XXX,XX @@
72
/*
73
* Intel ACPI Component Architecture
74
* AML/ASL+ Disassembler version 20200925 (64-bit version)
75
* Copyright (c) 2000 - 2020 Intel Corporation
76
*
77
- * Disassembly of tests/data/acpi/virt/DBG2, Fri Nov 3 14:12:06 2023
78
+ * Disassembly of /tmp/aml-V1YUD2, Fri Nov 3 14:12:06 2023
79
*
80
* ACPI Data Table [DBG2]
81
*
82
* Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
83
*/
84
85
[000h 0000 4] Signature : "DBG2" [Debug Port table type 2]
86
[004h 0004 4] Table Length : 00000057
87
[008h 0008 1] Revision : 00
88
-[009h 0009 1] Checksum : CF
89
+[009h 0009 1] Checksum : B5
90
[00Ah 0010 6] Oem ID : "BOCHS "
91
[010h 0016 8] Oem Table ID : "BXPC "
92
[018h 0024 4] Oem Revision : 00000001
93
[01Ch 0028 4] Asl Compiler ID : "BXPC"
94
[020h 0032 4] Asl Compiler Revision : 00000001
95
96
[024h 0036 4] Info Offset : 0000002C
97
[028h 0040 4] Info Count : 00000001
98
99
[02Ch 0044 1] Revision : 00
100
[02Dh 0045 2] Length : 002B
101
[02Fh 0047 1] Register Count : 01
102
[030h 0048 2] Namepath Length : 0005
103
[032h 0050 2] Namepath Offset : 0026
104
[034h 0052 2] OEM Data Length : 0000 [Optional field not present]
105
[036h 0054 2] OEM Data Offset : 0000 [Optional field not present]
106
[038h 0056 2] Port Type : 8000
107
[03Ah 0058 2] Port Subtype : 0003
108
[03Ch 0060 2] Reserved : 0000
109
[03Eh 0062 2] Base Address Offset : 0016
110
[040h 0064 2] Address Size Offset : 0022
111
112
[042h 0066 12] Base Address Register : [Generic Address Structure]
113
[042h 0066 1] Space ID : 00 [SystemMemory]
114
-[043h 0067 1] Bit Width : 08
115
+[043h 0067 1] Bit Width : 20
116
[044h 0068 1] Bit Offset : 00
117
-[045h 0069 1] Encoded Access Width : 01 [Byte Access:8]
118
+[045h 0069 1] Encoded Access Width : 03 [DWord Access:32]
119
[046h 0070 8] Address : 0000000009000000
120
121
[04Eh 0078 4] Address Size : 00001000
122
123
[052h 0082 5] Namepath : "COM0"
124
125
Raw Table Data: Length 87 (0x57)
126
127
- 0000: 44 42 47 32 57 00 00 00 00 CF 42 4F 43 48 53 20 // DBG2W.....BOCHS
128
+ 0000: 44 42 47 32 57 00 00 00 00 B5 42 4F 43 48 53 20 // DBG2W.....BOCHS
129
0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC
130
0020: 01 00 00 00 2C 00 00 00 01 00 00 00 00 2B 00 01 // ....,........+..
131
0030: 05 00 26 00 00 00 00 00 00 80 03 00 00 00 16 00 // ..&.............
132
- 0040: 22 00 00 08 00 01 00 00 00 09 00 00 00 00 00 10 // "...............
133
+ 0040: 22 00 00 20 00 03 00 00 00 09 00 00 00 00 00 10 // ".. ............
134
0050: 00 00 43 4F 4D 30 00 // ..COM0.
135
16
136
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
19
Message-id: 20241211144440.2700268-3-peter.maydell@linaro.org
137
---
20
---
138
tests/qtest/bios-tables-test-allowed-diff.h | 2 --
21
target/arm/cpregs.h | 8 ++++++++
139
tests/data/acpi/virt/DBG2 | Bin 87 -> 87 bytes
22
target/arm/helper.c | 25 +++++++++++++++++++++++++
140
tests/data/acpi/virt/SPCR | Bin 80 -> 80 bytes
23
2 files changed, 33 insertions(+)
141
3 files changed, 2 deletions(-)
142
24
143
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
25
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
144
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100644
145
--- a/tests/qtest/bios-tables-test-allowed-diff.h
27
--- a/target/arm/cpregs.h
146
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
28
+++ b/target/arm/cpregs.h
147
@@ -1,3 +1 @@
29
@@ -XXX,XX +XXX,XX @@ enum {
148
/* List of comma-separated changed AML files to ignore */
30
* equivalent EL1 register when FEAT_NV2 is enabled.
149
-"tests/data/acpi/virt/SPCR",
31
*/
150
-"tests/data/acpi/virt/DBG2",
32
ARM_CP_NV2_REDIRECT = 1 << 20,
151
diff --git a/tests/data/acpi/virt/DBG2 b/tests/data/acpi/virt/DBG2
33
+ /*
34
+ * Flag: this is a TLBI insn which (when FEAT_XS is present) also has
35
+ * an NXS variant at the same encoding except that crn is 1 greater,
36
+ * so when registering this cpreg automatically also register one
37
+ * for the TLBI NXS variant. (For QEMU the NXS variant behaves
38
+ * identically to the normal one, other than FGT trapping handling.)
39
+ */
40
+ ARM_CP_ADD_TLBI_NXS = 1 << 21,
41
};
42
43
/*
44
diff --git a/target/arm/helper.c b/target/arm/helper.c
152
index XXXXXXX..XXXXXXX 100644
45
index XXXXXXX..XXXXXXX 100644
153
GIT binary patch
46
--- a/target/arm/helper.c
154
delta 37
47
+++ b/target/arm/helper.c
155
ncmWF!=W=m!HwtF}f~^y|EJYL;n1M`A5T8MSfx+3|*MI>4b2kL{
48
@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
156
49
if (r->state != state && r->state != ARM_CP_STATE_BOTH) {
157
delta 37
50
continue;
158
ncmWF!=W=m!HwtF}g7Xu(EJZjN7=cVq5T8MSfx+3|*MI>4bG-!j
51
}
159
52
+ if ((r->type & ARM_CP_ADD_TLBI_NXS) &&
160
diff --git a/tests/data/acpi/virt/SPCR b/tests/data/acpi/virt/SPCR
53
+ cpu_isar_feature(aa64_xs, cpu)) {
161
index XXXXXXX..XXXXXXX 100644
54
+ /*
162
GIT binary patch
55
+ * This is a TLBI insn which has an NXS variant. The
163
delta 23
56
+ * NXS variant is at the same encoding except that
164
ecmWFt;0g|K4hmpkU|`xfkxQOgfq{9VjtT%gOa!L@
57
+ * crn is +1, and has the same behaviour except for
165
58
+ * fine-grained trapping. Add the NXS insn here and
166
delta 23
59
+ * then fall through to add the normal register.
167
ecmWFt;0g|K4hmpkU|>2ukxQPLgMo3PjtT%g(gddf
60
+ * add_cpreg_to_hashtable() copies the cpreg struct
168
61
+ * and name that it is passed, so it's OK to use
62
+ * a local struct here.
63
+ */
64
+ ARMCPRegInfo nxs_ri = *r;
65
+ g_autofree char *name = g_strdup_printf("%sNXS", r->name);
66
+
67
+ assert(state == ARM_CP_STATE_AA64);
68
+ assert(nxs_ri.crn < 0xf);
69
+ nxs_ri.crn++;
70
+ if (nxs_ri.fgt) {
71
+ nxs_ri.fgt |= R_FGT_NXS_MASK;
72
+ }
73
+ add_cpreg_to_hashtable(cpu, &nxs_ri, opaque, state,
74
+ ARM_CP_SECSTATE_NS,
75
+ crm, opc1, opc2, name);
76
+ }
77
if (state == ARM_CP_STATE_AA32) {
78
/*
79
* Under AArch32 CP registers can be common
169
--
80
--
170
2.34.1
81
2.34.1
diff view generated by jsdifflib
[PULL 06/12] util/filemonitor-inotify: qemu_file_monitor_watch(): assert no overflow
[PULL 14/19] target/arm: Add ARM_CP_ADD_TLBI_NXS type flag to TLBI insns
1
From: Vladimir Sementsov-Ogievskiy <vsementsov@yandex-team.ru>
1
Add the ARM_CP_ADD_TLBI_NXS to the TLBI insns with an NXS variant.
2
This is every AArch64 TLBI encoding except for the four FEAT_RME TLBI
3
insns.
2
4
3
Prefer clear assertions instead of [im]possible array overflow.
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20241211144440.2700268-4-peter.maydell@linaro.org
8
---
9
target/arm/tcg/tlb-insns.c | 202 +++++++++++++++++++++++--------------
10
1 file changed, 124 insertions(+), 78 deletions(-)
4
11
5
Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@yandex-team.ru>
12
diff --git a/target/arm/tcg/tlb-insns.c b/target/arm/tcg/tlb-insns.c
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Maksim Davydov <davydov-max@yandex-team.ru>
8
Message-id: 20231017125941.810461-3-vsementsov@yandex-team.ru
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
util/filemonitor-inotify.c | 25 +++++++++++++++++--------
12
1 file changed, 17 insertions(+), 8 deletions(-)
13
14
diff --git a/util/filemonitor-inotify.c b/util/filemonitor-inotify.c
15
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
16
--- a/util/filemonitor-inotify.c
14
--- a/target/arm/tcg/tlb-insns.c
17
+++ b/util/filemonitor-inotify.c
15
+++ b/target/arm/tcg/tlb-insns.c
18
@@ -XXX,XX +XXX,XX @@ static void qemu_file_monitor_watch(void *arg)
16
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbi_v8_cp_reginfo[] = {
19
17
/* AArch64 TLBI operations */
20
/* Loop over all events in the buffer */
18
{ .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
21
while (used < len) {
19
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
22
- struct inotify_event *ev =
20
- .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
23
- (struct inotify_event *)(buf + used);
21
+ .access = PL1_W, .accessfn = access_ttlbis,
24
- const char *name = ev->len ? ev->name : "";
22
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
25
- QFileMonitorDir *dir = g_hash_table_lookup(mon->idmap,
23
.fgt = FGT_TLBIVMALLE1IS,
26
- GINT_TO_POINTER(ev->wd));
24
.writefn = tlbi_aa64_vmalle1is_write },
27
- uint32_t iev = ev->mask &
25
{ .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64,
28
- (IN_CREATE | IN_MODIFY | IN_DELETE | IN_IGNORED |
26
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
29
- IN_MOVED_TO | IN_MOVED_FROM | IN_ATTRIB);
27
- .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
30
+ const char *name;
28
+ .access = PL1_W, .accessfn = access_ttlbis,
31
+ QFileMonitorDir *dir;
29
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
32
+ uint32_t iev;
30
.fgt = FGT_TLBIVAE1IS,
33
int qev;
31
.writefn = tlbi_aa64_vae1is_write },
34
gsize i;
32
{ .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64,
35
+ struct inotify_event *ev = (struct inotify_event *)(buf + used);
33
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
36
+
34
- .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
37
+ /*
35
+ .access = PL1_W, .accessfn = access_ttlbis,
38
+ * We trust the kenel to provide valid buffer with complete event
36
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
39
+ * records.
37
.fgt = FGT_TLBIASIDE1IS,
40
+ */
38
.writefn = tlbi_aa64_vmalle1is_write },
41
+ assert(len - used >= sizeof(struct inotify_event));
39
{ .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64,
42
+ assert(len - used - sizeof(struct inotify_event) >= ev->len);
40
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
43
+
41
- .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
44
+ name = ev->len ? ev->name : "";
42
+ .access = PL1_W, .accessfn = access_ttlbis,
45
+ dir = g_hash_table_lookup(mon->idmap, GINT_TO_POINTER(ev->wd));
43
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
46
+ iev = ev->mask &
44
.fgt = FGT_TLBIVAAE1IS,
47
+ (IN_CREATE | IN_MODIFY | IN_DELETE | IN_IGNORED |
45
.writefn = tlbi_aa64_vae1is_write },
48
+ IN_MOVED_TO | IN_MOVED_FROM | IN_ATTRIB);
46
{ .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64,
49
47
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
50
used += sizeof(struct inotify_event) + ev->len;
48
- .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
49
+ .access = PL1_W, .accessfn = access_ttlbis,
50
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
51
.fgt = FGT_TLBIVALE1IS,
52
.writefn = tlbi_aa64_vae1is_write },
53
{ .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64,
54
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
55
- .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
56
+ .access = PL1_W, .accessfn = access_ttlbis,
57
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
58
.fgt = FGT_TLBIVAALE1IS,
59
.writefn = tlbi_aa64_vae1is_write },
60
{ .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64,
61
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
62
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
63
+ .access = PL1_W, .accessfn = access_ttlb,
64
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
65
.fgt = FGT_TLBIVMALLE1,
66
.writefn = tlbi_aa64_vmalle1_write },
67
{ .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64,
68
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
69
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
70
+ .access = PL1_W, .accessfn = access_ttlb,
71
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
72
.fgt = FGT_TLBIVAE1,
73
.writefn = tlbi_aa64_vae1_write },
74
{ .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64,
75
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
76
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
77
+ .access = PL1_W, .accessfn = access_ttlb,
78
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
79
.fgt = FGT_TLBIASIDE1,
80
.writefn = tlbi_aa64_vmalle1_write },
81
{ .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64,
82
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
83
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
84
+ .access = PL1_W, .accessfn = access_ttlb,
85
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
86
.fgt = FGT_TLBIVAAE1,
87
.writefn = tlbi_aa64_vae1_write },
88
{ .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64,
89
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
90
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
91
+ .access = PL1_W, .accessfn = access_ttlb,
92
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
93
.fgt = FGT_TLBIVALE1,
94
.writefn = tlbi_aa64_vae1_write },
95
{ .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64,
96
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
97
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
98
+ .access = PL1_W, .accessfn = access_ttlb,
99
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
100
.fgt = FGT_TLBIVAALE1,
101
.writefn = tlbi_aa64_vae1_write },
102
{ .name = "TLBI_IPAS2E1IS", .state = ARM_CP_STATE_AA64,
103
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1,
104
- .access = PL2_W, .type = ARM_CP_NO_RAW,
105
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
106
.writefn = tlbi_aa64_ipas2e1is_write },
107
{ .name = "TLBI_IPAS2LE1IS", .state = ARM_CP_STATE_AA64,
108
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5,
109
- .access = PL2_W, .type = ARM_CP_NO_RAW,
110
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
111
.writefn = tlbi_aa64_ipas2e1is_write },
112
{ .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64,
113
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4,
114
- .access = PL2_W, .type = ARM_CP_NO_RAW,
115
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
116
.writefn = tlbi_aa64_alle1is_write },
117
{ .name = "TLBI_VMALLS12E1IS", .state = ARM_CP_STATE_AA64,
118
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 6,
119
- .access = PL2_W, .type = ARM_CP_NO_RAW,
120
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
121
.writefn = tlbi_aa64_alle1is_write },
122
{ .name = "TLBI_IPAS2E1", .state = ARM_CP_STATE_AA64,
123
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1,
124
- .access = PL2_W, .type = ARM_CP_NO_RAW,
125
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
126
.writefn = tlbi_aa64_ipas2e1_write },
127
{ .name = "TLBI_IPAS2LE1", .state = ARM_CP_STATE_AA64,
128
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5,
129
- .access = PL2_W, .type = ARM_CP_NO_RAW,
130
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
131
.writefn = tlbi_aa64_ipas2e1_write },
132
{ .name = "TLBI_ALLE1", .state = ARM_CP_STATE_AA64,
133
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4,
134
- .access = PL2_W, .type = ARM_CP_NO_RAW,
135
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
136
.writefn = tlbi_aa64_alle1_write },
137
{ .name = "TLBI_VMALLS12E1", .state = ARM_CP_STATE_AA64,
138
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 6,
139
- .access = PL2_W, .type = ARM_CP_NO_RAW,
140
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
141
.writefn = tlbi_aa64_alle1is_write },
142
};
143
144
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbi_el2_cp_reginfo[] = {
145
.writefn = tlbimva_hyp_is_write },
146
{ .name = "TLBI_ALLE2", .state = ARM_CP_STATE_AA64,
147
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0,
148
- .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
149
+ .access = PL2_W,
150
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF,
151
.writefn = tlbi_aa64_alle2_write },
152
{ .name = "TLBI_VAE2", .state = ARM_CP_STATE_AA64,
153
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1,
154
- .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
155
+ .access = PL2_W,
156
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF,
157
.writefn = tlbi_aa64_vae2_write },
158
{ .name = "TLBI_VALE2", .state = ARM_CP_STATE_AA64,
159
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5,
160
- .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
161
+ .access = PL2_W,
162
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF,
163
.writefn = tlbi_aa64_vae2_write },
164
{ .name = "TLBI_ALLE2IS", .state = ARM_CP_STATE_AA64,
165
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0,
166
- .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
167
+ .access = PL2_W,
168
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF,
169
.writefn = tlbi_aa64_alle2is_write },
170
{ .name = "TLBI_VAE2IS", .state = ARM_CP_STATE_AA64,
171
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1,
172
- .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
173
+ .access = PL2_W,
174
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF,
175
.writefn = tlbi_aa64_vae2is_write },
176
{ .name = "TLBI_VALE2IS", .state = ARM_CP_STATE_AA64,
177
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5,
178
- .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
179
+ .access = PL2_W,
180
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF,
181
.writefn = tlbi_aa64_vae2is_write },
182
};
183
184
static const ARMCPRegInfo tlbi_el3_cp_reginfo[] = {
185
{ .name = "TLBI_ALLE3IS", .state = ARM_CP_STATE_AA64,
186
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 0,
187
- .access = PL3_W, .type = ARM_CP_NO_RAW,
188
+ .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
189
.writefn = tlbi_aa64_alle3is_write },
190
{ .name = "TLBI_VAE3IS", .state = ARM_CP_STATE_AA64,
191
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 1,
192
- .access = PL3_W, .type = ARM_CP_NO_RAW,
193
+ .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
194
.writefn = tlbi_aa64_vae3is_write },
195
{ .name = "TLBI_VALE3IS", .state = ARM_CP_STATE_AA64,
196
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 5,
197
- .access = PL3_W, .type = ARM_CP_NO_RAW,
198
+ .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
199
.writefn = tlbi_aa64_vae3is_write },
200
{ .name = "TLBI_ALLE3", .state = ARM_CP_STATE_AA64,
201
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 0,
202
- .access = PL3_W, .type = ARM_CP_NO_RAW,
203
+ .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
204
.writefn = tlbi_aa64_alle3_write },
205
{ .name = "TLBI_VAE3", .state = ARM_CP_STATE_AA64,
206
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 1,
207
- .access = PL3_W, .type = ARM_CP_NO_RAW,
208
+ .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
209
.writefn = tlbi_aa64_vae3_write },
210
{ .name = "TLBI_VALE3", .state = ARM_CP_STATE_AA64,
211
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 5,
212
- .access = PL3_W, .type = ARM_CP_NO_RAW,
213
+ .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
214
.writefn = tlbi_aa64_vae3_write },
215
};
216
217
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_ripas2e1is_write(CPUARMState *env,
218
static const ARMCPRegInfo tlbirange_reginfo[] = {
219
{ .name = "TLBI_RVAE1IS", .state = ARM_CP_STATE_AA64,
220
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 1,
221
- .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
222
+ .access = PL1_W, .accessfn = access_ttlbis,
223
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
224
.fgt = FGT_TLBIRVAE1IS,
225
.writefn = tlbi_aa64_rvae1is_write },
226
{ .name = "TLBI_RVAAE1IS", .state = ARM_CP_STATE_AA64,
227
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 3,
228
- .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
229
+ .access = PL1_W, .accessfn = access_ttlbis,
230
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
231
.fgt = FGT_TLBIRVAAE1IS,
232
.writefn = tlbi_aa64_rvae1is_write },
233
{ .name = "TLBI_RVALE1IS", .state = ARM_CP_STATE_AA64,
234
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 5,
235
- .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
236
+ .access = PL1_W, .accessfn = access_ttlbis,
237
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
238
.fgt = FGT_TLBIRVALE1IS,
239
.writefn = tlbi_aa64_rvae1is_write },
240
{ .name = "TLBI_RVAALE1IS", .state = ARM_CP_STATE_AA64,
241
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 7,
242
- .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
243
+ .access = PL1_W, .accessfn = access_ttlbis,
244
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
245
.fgt = FGT_TLBIRVAALE1IS,
246
.writefn = tlbi_aa64_rvae1is_write },
247
{ .name = "TLBI_RVAE1OS", .state = ARM_CP_STATE_AA64,
248
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1,
249
- .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
250
+ .access = PL1_W, .accessfn = access_ttlbos,
251
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
252
.fgt = FGT_TLBIRVAE1OS,
253
.writefn = tlbi_aa64_rvae1is_write },
254
{ .name = "TLBI_RVAAE1OS", .state = ARM_CP_STATE_AA64,
255
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 3,
256
- .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
257
+ .access = PL1_W, .accessfn = access_ttlbos,
258
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
259
.fgt = FGT_TLBIRVAAE1OS,
260
.writefn = tlbi_aa64_rvae1is_write },
261
{ .name = "TLBI_RVALE1OS", .state = ARM_CP_STATE_AA64,
262
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 5,
263
- .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
264
+ .access = PL1_W, .accessfn = access_ttlbos,
265
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
266
.fgt = FGT_TLBIRVALE1OS,
267
.writefn = tlbi_aa64_rvae1is_write },
268
{ .name = "TLBI_RVAALE1OS", .state = ARM_CP_STATE_AA64,
269
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 7,
270
- .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
271
+ .access = PL1_W, .accessfn = access_ttlbos,
272
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
273
.fgt = FGT_TLBIRVAALE1OS,
274
.writefn = tlbi_aa64_rvae1is_write },
275
{ .name = "TLBI_RVAE1", .state = ARM_CP_STATE_AA64,
276
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1,
277
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
278
+ .access = PL1_W, .accessfn = access_ttlb,
279
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
280
.fgt = FGT_TLBIRVAE1,
281
.writefn = tlbi_aa64_rvae1_write },
282
{ .name = "TLBI_RVAAE1", .state = ARM_CP_STATE_AA64,
283
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 3,
284
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
285
+ .access = PL1_W, .accessfn = access_ttlb,
286
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
287
.fgt = FGT_TLBIRVAAE1,
288
.writefn = tlbi_aa64_rvae1_write },
289
{ .name = "TLBI_RVALE1", .state = ARM_CP_STATE_AA64,
290
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 5,
291
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
292
+ .access = PL1_W, .accessfn = access_ttlb,
293
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
294
.fgt = FGT_TLBIRVALE1,
295
.writefn = tlbi_aa64_rvae1_write },
296
{ .name = "TLBI_RVAALE1", .state = ARM_CP_STATE_AA64,
297
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 7,
298
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
299
+ .access = PL1_W, .accessfn = access_ttlb,
300
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
301
.fgt = FGT_TLBIRVAALE1,
302
.writefn = tlbi_aa64_rvae1_write },
303
{ .name = "TLBI_RIPAS2E1IS", .state = ARM_CP_STATE_AA64,
304
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 2,
305
- .access = PL2_W, .type = ARM_CP_NO_RAW,
306
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
307
.writefn = tlbi_aa64_ripas2e1is_write },
308
{ .name = "TLBI_RIPAS2LE1IS", .state = ARM_CP_STATE_AA64,
309
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 6,
310
- .access = PL2_W, .type = ARM_CP_NO_RAW,
311
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
312
.writefn = tlbi_aa64_ripas2e1is_write },
313
{ .name = "TLBI_RVAE2IS", .state = ARM_CP_STATE_AA64,
314
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 1,
315
- .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
316
+ .access = PL2_W,
317
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF,
318
.writefn = tlbi_aa64_rvae2is_write },
319
{ .name = "TLBI_RVALE2IS", .state = ARM_CP_STATE_AA64,
320
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 5,
321
- .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
322
+ .access = PL2_W,
323
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF,
324
.writefn = tlbi_aa64_rvae2is_write },
325
{ .name = "TLBI_RIPAS2E1", .state = ARM_CP_STATE_AA64,
326
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 2,
327
- .access = PL2_W, .type = ARM_CP_NO_RAW,
328
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
329
.writefn = tlbi_aa64_ripas2e1_write },
330
{ .name = "TLBI_RIPAS2LE1", .state = ARM_CP_STATE_AA64,
331
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 6,
332
- .access = PL2_W, .type = ARM_CP_NO_RAW,
333
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
334
.writefn = tlbi_aa64_ripas2e1_write },
335
{ .name = "TLBI_RVAE2OS", .state = ARM_CP_STATE_AA64,
336
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 1,
337
- .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
338
+ .access = PL2_W,
339
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF,
340
.writefn = tlbi_aa64_rvae2is_write },
341
{ .name = "TLBI_RVALE2OS", .state = ARM_CP_STATE_AA64,
342
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 5,
343
- .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
344
+ .access = PL2_W,
345
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF,
346
.writefn = tlbi_aa64_rvae2is_write },
347
{ .name = "TLBI_RVAE2", .state = ARM_CP_STATE_AA64,
348
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 6, .opc2 = 1,
349
- .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
350
+ .access = PL2_W,
351
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF,
352
.writefn = tlbi_aa64_rvae2_write },
353
{ .name = "TLBI_RVALE2", .state = ARM_CP_STATE_AA64,
354
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 6, .opc2 = 5,
355
- .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
356
+ .access = PL2_W,
357
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF,
358
.writefn = tlbi_aa64_rvae2_write },
359
{ .name = "TLBI_RVAE3IS", .state = ARM_CP_STATE_AA64,
360
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 2, .opc2 = 1,
361
- .access = PL3_W, .type = ARM_CP_NO_RAW,
362
+ .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
363
.writefn = tlbi_aa64_rvae3is_write },
364
{ .name = "TLBI_RVALE3IS", .state = ARM_CP_STATE_AA64,
365
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 2, .opc2 = 5,
366
- .access = PL3_W, .type = ARM_CP_NO_RAW,
367
+ .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
368
.writefn = tlbi_aa64_rvae3is_write },
369
{ .name = "TLBI_RVAE3OS", .state = ARM_CP_STATE_AA64,
370
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 5, .opc2 = 1,
371
- .access = PL3_W, .type = ARM_CP_NO_RAW,
372
+ .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
373
.writefn = tlbi_aa64_rvae3is_write },
374
{ .name = "TLBI_RVALE3OS", .state = ARM_CP_STATE_AA64,
375
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 5, .opc2 = 5,
376
- .access = PL3_W, .type = ARM_CP_NO_RAW,
377
+ .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
378
.writefn = tlbi_aa64_rvae3is_write },
379
{ .name = "TLBI_RVAE3", .state = ARM_CP_STATE_AA64,
380
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 6, .opc2 = 1,
381
- .access = PL3_W, .type = ARM_CP_NO_RAW,
382
+ .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
383
.writefn = tlbi_aa64_rvae3_write },
384
{ .name = "TLBI_RVALE3", .state = ARM_CP_STATE_AA64,
385
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 6, .opc2 = 5,
386
- .access = PL3_W, .type = ARM_CP_NO_RAW,
387
+ .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
388
.writefn = tlbi_aa64_rvae3_write },
389
};
390
391
static const ARMCPRegInfo tlbios_reginfo[] = {
392
{ .name = "TLBI_VMALLE1OS", .state = ARM_CP_STATE_AA64,
393
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 0,
394
- .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
395
+ .access = PL1_W, .accessfn = access_ttlbos,
396
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
397
.fgt = FGT_TLBIVMALLE1OS,
398
.writefn = tlbi_aa64_vmalle1is_write },
399
{ .name = "TLBI_VAE1OS", .state = ARM_CP_STATE_AA64,
400
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 1,
401
.fgt = FGT_TLBIVAE1OS,
402
- .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
403
+ .access = PL1_W, .accessfn = access_ttlbos,
404
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
405
.writefn = tlbi_aa64_vae1is_write },
406
{ .name = "TLBI_ASIDE1OS", .state = ARM_CP_STATE_AA64,
407
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 2,
408
- .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
409
+ .access = PL1_W, .accessfn = access_ttlbos,
410
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
411
.fgt = FGT_TLBIASIDE1OS,
412
.writefn = tlbi_aa64_vmalle1is_write },
413
{ .name = "TLBI_VAAE1OS", .state = ARM_CP_STATE_AA64,
414
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 3,
415
- .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
416
+ .access = PL1_W, .accessfn = access_ttlbos,
417
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
418
.fgt = FGT_TLBIVAAE1OS,
419
.writefn = tlbi_aa64_vae1is_write },
420
{ .name = "TLBI_VALE1OS", .state = ARM_CP_STATE_AA64,
421
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 5,
422
- .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
423
+ .access = PL1_W, .accessfn = access_ttlbos,
424
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
425
.fgt = FGT_TLBIVALE1OS,
426
.writefn = tlbi_aa64_vae1is_write },
427
{ .name = "TLBI_VAALE1OS", .state = ARM_CP_STATE_AA64,
428
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 7,
429
- .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
430
+ .access = PL1_W, .accessfn = access_ttlbos,
431
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
432
.fgt = FGT_TLBIVAALE1OS,
433
.writefn = tlbi_aa64_vae1is_write },
434
{ .name = "TLBI_ALLE2OS", .state = ARM_CP_STATE_AA64,
435
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 0,
436
- .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
437
+ .access = PL2_W,
438
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF,
439
.writefn = tlbi_aa64_alle2is_write },
440
{ .name = "TLBI_VAE2OS", .state = ARM_CP_STATE_AA64,
441
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 1,
442
- .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
443
+ .access = PL2_W,
444
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF,
445
.writefn = tlbi_aa64_vae2is_write },
446
{ .name = "TLBI_ALLE1OS", .state = ARM_CP_STATE_AA64,
447
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 4,
448
- .access = PL2_W, .type = ARM_CP_NO_RAW,
449
+ .access = PL2_W,
450
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
451
.writefn = tlbi_aa64_alle1is_write },
452
{ .name = "TLBI_VALE2OS", .state = ARM_CP_STATE_AA64,
453
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 5,
454
- .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
455
+ .access = PL2_W,
456
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF,
457
.writefn = tlbi_aa64_vae2is_write },
458
{ .name = "TLBI_VMALLS12E1OS", .state = ARM_CP_STATE_AA64,
459
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 6,
460
- .access = PL2_W, .type = ARM_CP_NO_RAW,
461
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
462
.writefn = tlbi_aa64_alle1is_write },
463
{ .name = "TLBI_IPAS2E1OS", .state = ARM_CP_STATE_AA64,
464
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 0,
465
- .access = PL2_W, .type = ARM_CP_NOP },
466
+ .access = PL2_W, .type = ARM_CP_NOP | ARM_CP_ADD_TLBI_NXS },
467
{ .name = "TLBI_RIPAS2E1OS", .state = ARM_CP_STATE_AA64,
468
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 3,
469
- .access = PL2_W, .type = ARM_CP_NOP },
470
+ .access = PL2_W, .type = ARM_CP_NOP | ARM_CP_ADD_TLBI_NXS },
471
{ .name = "TLBI_IPAS2LE1OS", .state = ARM_CP_STATE_AA64,
472
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 4,
473
- .access = PL2_W, .type = ARM_CP_NOP },
474
+ .access = PL2_W, .type = ARM_CP_NOP | ARM_CP_ADD_TLBI_NXS },
475
{ .name = "TLBI_RIPAS2LE1OS", .state = ARM_CP_STATE_AA64,
476
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 7,
477
- .access = PL2_W, .type = ARM_CP_NOP },
478
+ .access = PL2_W, .type = ARM_CP_NOP | ARM_CP_ADD_TLBI_NXS },
479
{ .name = "TLBI_ALLE3OS", .state = ARM_CP_STATE_AA64,
480
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 1, .opc2 = 0,
481
- .access = PL3_W, .type = ARM_CP_NO_RAW,
482
+ .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
483
.writefn = tlbi_aa64_alle3is_write },
484
{ .name = "TLBI_VAE3OS", .state = ARM_CP_STATE_AA64,
485
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 1, .opc2 = 1,
486
- .access = PL3_W, .type = ARM_CP_NO_RAW,
487
+ .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
488
.writefn = tlbi_aa64_vae3is_write },
489
{ .name = "TLBI_VALE3OS", .state = ARM_CP_STATE_AA64,
490
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 1, .opc2 = 5,
491
- .access = PL3_W, .type = ARM_CP_NO_RAW,
492
+ .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
493
.writefn = tlbi_aa64_vae3is_write },
494
};
51
495
52
--
496
--
53
2.34.1
497
2.34.1
diff view generated by jsdifflib
[PULL 08/12] block/nvme: nvme_process_completion() fix bound for cid
[PULL 15/19] target/arm: Add decodetree entry for DSB nXS variant
1
From: Vladimir Sementsov-Ogievskiy <vsementsov@yandex-team.ru>
1
From: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
2
2
3
NVMeQueuePair::reqs has length NVME_NUM_REQS, which less than
3
The DSB nXS variant is always both a reads and writes request type.
4
NVME_QUEUE_SIZE by 1.
4
Ignore the domain field like we do in plain DSB and perform a full
5
system barrier operation.
5
6
6
Fixes: 1086e95da17050 ("block/nvme: switch to a NVMeRequest freelist")
7
The DSB nXS variant is part of FEAT_XS made mandatory from Armv8.7.
7
Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@yandex-team.ru>
8
8
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
9
Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
9
Reviewed-by: Maksim Davydov <davydov-max@yandex-team.ru>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Message-id: 20231017125941.810461-5-vsementsov@yandex-team.ru
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20241211144440.2700268-5-peter.maydell@linaro.org
13
[PMM: added missing "UNDEF unless feature present" check]
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
15
---
13
block/nvme.c | 7 ++++---
16
target/arm/tcg/a64.decode | 3 +++
14
1 file changed, 4 insertions(+), 3 deletions(-)
17
target/arm/tcg/translate-a64.c | 9 +++++++++
18
2 files changed, 12 insertions(+)
15
19
16
diff --git a/block/nvme.c b/block/nvme.c
20
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
17
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
18
--- a/block/nvme.c
22
--- a/target/arm/tcg/a64.decode
19
+++ b/block/nvme.c
23
+++ b/target/arm/tcg/a64.decode
20
@@ -XXX,XX +XXX,XX @@ static bool nvme_process_completion(NVMeQueuePair *q)
24
@@ -XXX,XX +XXX,XX @@ WFIT 1101 0101 0000 0011 0001 0000 001 rd:5
21
q->cq_phase = !q->cq_phase;
25
22
}
26
CLREX 1101 0101 0000 0011 0011 ---- 010 11111
23
cid = le16_to_cpu(c->cid);
27
DSB_DMB 1101 0101 0000 0011 0011 domain:2 types:2 10- 11111
24
- if (cid == 0 || cid > NVME_QUEUE_SIZE) {
28
+# For the DSB nXS variant, types always equals MBReqTypes_All and we ignore the
25
- warn_report("NVMe: Unexpected CID in completion queue: %"PRIu32", "
29
+# domain bits.
26
- "queue size: %u", cid, NVME_QUEUE_SIZE);
30
+DSB_nXS 1101 0101 0000 0011 0011 -- 10 001 11111
27
+ if (cid == 0 || cid > NVME_NUM_REQS) {
31
ISB 1101 0101 0000 0011 0011 ---- 110 11111
28
+ warn_report("NVMe: Unexpected CID in completion queue: %" PRIu32
32
SB 1101 0101 0000 0011 0011 0000 111 11111
29
+ ", should be within: 1..%u inclusively", cid,
33
30
+ NVME_NUM_REQS);
34
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
31
continue;
35
index XXXXXXX..XXXXXXX 100644
32
}
36
--- a/target/arm/tcg/translate-a64.c
33
trace_nvme_complete_command(s, q->index, cid);
37
+++ b/target/arm/tcg/translate-a64.c
38
@@ -XXX,XX +XXX,XX @@ static bool trans_DSB_DMB(DisasContext *s, arg_DSB_DMB *a)
39
return true;
40
}
41
42
+static bool trans_DSB_nXS(DisasContext *s, arg_DSB_nXS *a)
43
+{
44
+ if (!dc_isar_feature(aa64_xs, s)) {
45
+ return false;
46
+ }
47
+ tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL);
48
+ return true;
49
+}
50
+
51
static bool trans_ISB(DisasContext *s, arg_ISB *a)
52
{
53
/*
34
--
54
--
35
2.34.1
55
2.34.1
diff view generated by jsdifflib
New patch
[PULL 16/19] target/arm: Enable FEAT_XS for the max cpu
1
From: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
1
2
3
Add FEAT_XS feature report value in max cpu's ID_AA64ISAR1 sys register.
4
5
Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20241211144440.2700268-6-peter.maydell@linaro.org
9
[PMM: Add entry for FEAT_XS to documentation]
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
---
12
docs/system/arm/emulation.rst | 1 +
13
target/arm/tcg/cpu64.c | 1 +
14
2 files changed, 2 insertions(+)
15
16
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
17
index XXXXXXX..XXXXXXX 100644
18
--- a/docs/system/arm/emulation.rst
19
+++ b/docs/system/arm/emulation.rst
20
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
21
- FEAT_VMID16 (16-bit VMID)
22
- FEAT_WFxT (WFE and WFI instructions with timeout)
23
- FEAT_XNX (Translation table stage 2 Unprivileged Execute-never)
24
+- FEAT_XS (XS attribute)
25
26
For information on the specifics of these extensions, please refer
27
to the `Arm Architecture Reference Manual for A-profile architecture
28
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
29
index XXXXXXX..XXXXXXX 100644
30
--- a/target/arm/tcg/cpu64.c
31
+++ b/target/arm/tcg/cpu64.c
32
@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
33
t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 2); /* FEAT_BF16, FEAT_EBF16 */
34
t = FIELD_DP64(t, ID_AA64ISAR1, DGH, 1); /* FEAT_DGH */
35
t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */
36
+ t = FIELD_DP64(t, ID_AA64ISAR1, XS, 1); /* FEAT_XS */
37
cpu->isar.id_aa64isar1 = t;
38
39
t = cpu->isar.id_aa64isar2;
40
--
41
2.34.1
diff view generated by jsdifflib
[PULL 07/12] mc146818rtc: rtc_set_time(): initialize tm to zeroes
[PULL 17/19] tests/tcg/aarch64: add system test for FEAT_XS
1
From: Vladimir Sementsov-Ogievskiy <vsementsov@yandex-team.ru>
1
From: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
2
2
3
set_time() function doesn't set all the fields, so it's better to
3
Add system test to make sure FEAT_XS is enabled for max cpu emulation
4
initialize tm structure. And Coverity will be happier about it.
4
and that QEMU doesn't crash when encountering an NXS instruction
5
variant.
5
6
6
Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@yandex-team.ru>
7
Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Maksim Davydov <davydov-max@yandex-team.ru>
9
Message-id: 20241211144440.2700268-7-peter.maydell@linaro.org
9
Message-id: 20231017125941.810461-4-vsementsov@yandex-team.ru
10
[PMM: In ISAR field test, mask with 0xf, not 0xff; use < rather
11
than an equality test to follow the standard ID register field
12
check guidelines]
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
14
---
12
hw/rtc/mc146818rtc.c | 2 +-
15
tests/tcg/aarch64/system/feat-xs.c | 27 +++++++++++++++++++++++++++
13
1 file changed, 1 insertion(+), 1 deletion(-)
16
1 file changed, 27 insertions(+)
17
create mode 100644 tests/tcg/aarch64/system/feat-xs.c
14
18
15
diff --git a/hw/rtc/mc146818rtc.c b/hw/rtc/mc146818rtc.c
19
diff --git a/tests/tcg/aarch64/system/feat-xs.c b/tests/tcg/aarch64/system/feat-xs.c
16
index XXXXXXX..XXXXXXX 100644
20
new file mode 100644
17
--- a/hw/rtc/mc146818rtc.c
21
index XXXXXXX..XXXXXXX
18
+++ b/hw/rtc/mc146818rtc.c
22
--- /dev/null
19
@@ -XXX,XX +XXX,XX @@ static void rtc_get_time(MC146818RtcState *s, struct tm *tm)
23
+++ b/tests/tcg/aarch64/system/feat-xs.c
20
24
@@ -XXX,XX +XXX,XX @@
21
static void rtc_set_time(MC146818RtcState *s)
25
+/*
22
{
26
+ * FEAT_XS Test
23
- struct tm tm;
27
+ *
24
+ struct tm tm = {};
28
+ * Copyright (c) 2024 Linaro Ltd
25
g_autofree const char *qom_path = object_get_canonical_path(OBJECT(s));
29
+ *
26
30
+ * SPDX-License-Identifier: GPL-2.0-or-later
27
rtc_get_time(s, &tm);
31
+ */
32
+
33
+#include <minilib.h>
34
+#include <stdint.h>
35
+
36
+int main(void)
37
+{
38
+ uint64_t isar1;
39
+
40
+ asm volatile ("mrs %0, id_aa64isar1_el1" : "=r"(isar1));
41
+ if (((isar1 >> 56) & 0xf) < 1) {
42
+ ml_printf("FEAT_XS not supported by CPU");
43
+ return 1;
44
+ }
45
+ /* VMALLE1NXS */
46
+ asm volatile (".inst 0xd508971f");
47
+ /* VMALLE1OSNXS */
48
+ asm volatile (".inst 0xd508911f");
49
+
50
+ return 0;
51
+}
28
--
52
--
29
2.34.1
53
2.34.1
diff view generated by jsdifflib
New patch
[PULL 18/19] hw/intc/arm_gicv3_its: Zero initialize local DTEntry etc structs
1
In the GICv3 ITS model, we have a common coding pattern which has a
2
local C struct like "DTEntry dte", which is a C representation of an
3
in-guest-memory data structure, and we call a function such as
4
get_dte() to read guest memory and fill in the C struct. These
5
functions to read in the struct sometimes have cases where they will
6
leave early and not fill in the whole struct (for instance get_dte()
7
will set "dte->valid = false" and nothing else for the case where it
8
is passed an entry_addr implying that there is no L2 table entry for
9
the DTE). This then causes potential use of uninitialized memory
10
later, for instance when we call a trace event which prints all the
11
fields of the struct. Sufficiently advanced compilers may produce
12
-Wmaybe-uninitialized warnings about this, especially if LTO is
13
enabled.
1
14
15
Rather than trying to carefully separate out these trace events into
16
"only the 'valid' field is initialized" and "all fields can be
17
printed", zero-init all the structs when we define them. None of
18
these structs are large (the biggest is 24 bytes) and having
19
consistent behaviour is less likely to be buggy.
20
21
Cc: qemu-stable@nongnu.org
22
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2718
23
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
24
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
25
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
26
Message-id: 20241213182337.3343068-1-peter.maydell@linaro.org
27
---
28
hw/intc/arm_gicv3_its.c | 44 ++++++++++++++++++++---------------------
29
1 file changed, 22 insertions(+), 22 deletions(-)
30
31
diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/hw/intc/arm_gicv3_its.c
34
+++ b/hw/intc/arm_gicv3_its.c
35
@@ -XXX,XX +XXX,XX @@ static ItsCmdResult lookup_vte(GICv3ITSState *s, const char *who,
36
static ItsCmdResult process_its_cmd_phys(GICv3ITSState *s, const ITEntry *ite,
37
int irqlevel)
38
{
39
- CTEntry cte;
40
+ CTEntry cte = {};
41
ItsCmdResult cmdres;
42
43
cmdres = lookup_cte(s, __func__, ite->icid, &cte);
44
@@ -XXX,XX +XXX,XX @@ static ItsCmdResult process_its_cmd_phys(GICv3ITSState *s, const ITEntry *ite,
45
static ItsCmdResult process_its_cmd_virt(GICv3ITSState *s, const ITEntry *ite,
46
int irqlevel)
47
{
48
- VTEntry vte;
49
+ VTEntry vte = {};
50
ItsCmdResult cmdres;
51
52
cmdres = lookup_vte(s, __func__, ite->vpeid, &vte);
53
@@ -XXX,XX +XXX,XX @@ static ItsCmdResult process_its_cmd_virt(GICv3ITSState *s, const ITEntry *ite,
54
static ItsCmdResult do_process_its_cmd(GICv3ITSState *s, uint32_t devid,
55
uint32_t eventid, ItsCmdType cmd)
56
{
57
- DTEntry dte;
58
- ITEntry ite;
59
+ DTEntry dte = {};
60
+ ITEntry ite = {};
61
ItsCmdResult cmdres;
62
int irqlevel;
63
64
@@ -XXX,XX +XXX,XX @@ static ItsCmdResult process_mapti(GICv3ITSState *s, const uint64_t *cmdpkt,
65
uint32_t pIntid = 0;
66
uint64_t num_eventids;
67
uint16_t icid = 0;
68
- DTEntry dte;
69
- ITEntry ite;
70
+ DTEntry dte = {};
71
+ ITEntry ite = {};
72
73
devid = (cmdpkt[0] & DEVID_MASK) >> DEVID_SHIFT;
74
eventid = cmdpkt[1] & EVENTID_MASK;
75
@@ -XXX,XX +XXX,XX @@ static ItsCmdResult process_vmapti(GICv3ITSState *s, const uint64_t *cmdpkt,
76
{
77
uint32_t devid, eventid, vintid, doorbell, vpeid;
78
uint32_t num_eventids;
79
- DTEntry dte;
80
- ITEntry ite;
81
+ DTEntry dte = {};
82
+ ITEntry ite = {};
83
84
if (!its_feature_virtual(s)) {
85
return CMD_CONTINUE;
86
@@ -XXX,XX +XXX,XX @@ static bool update_cte(GICv3ITSState *s, uint16_t icid, const CTEntry *cte)
87
static ItsCmdResult process_mapc(GICv3ITSState *s, const uint64_t *cmdpkt)
88
{
89
uint16_t icid;
90
- CTEntry cte;
91
+ CTEntry cte = {};
92
93
icid = cmdpkt[2] & ICID_MASK;
94
cte.valid = cmdpkt[2] & CMD_FIELD_VALID_MASK;
95
@@ -XXX,XX +XXX,XX @@ static bool update_dte(GICv3ITSState *s, uint32_t devid, const DTEntry *dte)
96
static ItsCmdResult process_mapd(GICv3ITSState *s, const uint64_t *cmdpkt)
97
{
98
uint32_t devid;
99
- DTEntry dte;
100
+ DTEntry dte = {};
101
102
devid = (cmdpkt[0] & DEVID_MASK) >> DEVID_SHIFT;
103
dte.size = cmdpkt[1] & SIZE_MASK;
104
@@ -XXX,XX +XXX,XX @@ static ItsCmdResult process_movi(GICv3ITSState *s, const uint64_t *cmdpkt)
105
{
106
uint32_t devid, eventid;
107
uint16_t new_icid;
108
- DTEntry dte;
109
- CTEntry old_cte, new_cte;
110
- ITEntry old_ite;
111
+ DTEntry dte = {};
112
+ CTEntry old_cte = {}, new_cte = {};
113
+ ITEntry old_ite = {};
114
ItsCmdResult cmdres;
115
116
devid = FIELD_EX64(cmdpkt[0], MOVI_0, DEVICEID);
117
@@ -XXX,XX +XXX,XX @@ static bool update_vte(GICv3ITSState *s, uint32_t vpeid, const VTEntry *vte)
118
119
static ItsCmdResult process_vmapp(GICv3ITSState *s, const uint64_t *cmdpkt)
120
{
121
- VTEntry vte;
122
+ VTEntry vte = {};
123
uint32_t vpeid;
124
125
if (!its_feature_virtual(s)) {
126
@@ -XXX,XX +XXX,XX @@ static void vmovp_callback(gpointer data, gpointer opaque)
127
*/
128
GICv3ITSState *s = data;
129
VmovpCallbackData *cbdata = opaque;
130
- VTEntry vte;
131
+ VTEntry vte = {};
132
ItsCmdResult cmdres;
133
134
cmdres = lookup_vte(s, __func__, cbdata->vpeid, &vte);
135
@@ -XXX,XX +XXX,XX @@ static ItsCmdResult process_vmovi(GICv3ITSState *s, const uint64_t *cmdpkt)
136
{
137
uint32_t devid, eventid, vpeid, doorbell;
138
bool doorbell_valid;
139
- DTEntry dte;
140
- ITEntry ite;
141
- VTEntry old_vte, new_vte;
142
+ DTEntry dte = {};
143
+ ITEntry ite = {};
144
+ VTEntry old_vte = {}, new_vte = {};
145
ItsCmdResult cmdres;
146
147
if (!its_feature_virtual(s)) {
148
@@ -XXX,XX +XXX,XX @@ static ItsCmdResult process_vinvall(GICv3ITSState *s, const uint64_t *cmdpkt)
149
static ItsCmdResult process_inv(GICv3ITSState *s, const uint64_t *cmdpkt)
150
{
151
uint32_t devid, eventid;
152
- ITEntry ite;
153
- DTEntry dte;
154
- CTEntry cte;
155
- VTEntry vte;
156
+ ITEntry ite = {};
157
+ DTEntry dte = {};
158
+ CTEntry cte = {};
159
+ VTEntry vte = {};
160
ItsCmdResult cmdres;
161
162
devid = FIELD_EX64(cmdpkt[0], INV_0, DEVICEID);
163
--
164
2.34.1
165
166
diff view generated by jsdifflib
[PULL 03/12] hw/arm/virt: Report correct register sizes in ACPI DBG2/SPCR tables.
[PULL 19/19] tests/functional: update sbsa-ref firmware used in test
1
From: Udo Steinberg <udo@hypervisor.org>
1
From: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
2
2
3
Documentation for using the GAS in ACPI tables to report debug UART addresses at
3
Update the URLs for the binaries we use for the firmware in the
4
https://learn.microsoft.com/en-us/windows-hardware/drivers/bringup/acpi-debug-port-table
4
sbsa-ref functional tests.
5
states the following:
6
5
7
- The Register Bit Width field contains the register stride and must be a
6
The firmware is built using Debian 'bookworm' cross toolchain (gcc
8
power of 2 that is at least as large as the access size. On 32-bit
7
12.2.0).
9
platforms this value cannot exceed 32. On 64-bit platforms this value
10
cannot exceed 64.
11
- The Access Size field is used to determine whether byte, WORD, DWORD, or
12
QWORD accesses are to be used. QWORD accesses are only valid on 64-bit
13
architectures.
14
8
15
Documentation for the ARM PL011 at
9
Used versions:
16
https://developer.arm.com/documentation/ddi0183/latest/
17
states that the registers are:
18
10
19
- spaced 4 bytes apart (see Table 3-2), so register stride must be 32.
11
- Trusted Firmware v2.12.0
20
- 16 bits in size in some cases (see individual registers), so access
12
- Tianocore EDK2 stable202411
21
size must be at least 2.
13
- Tianocore EDK2 Platforms code commit 4b3530d
22
14
23
Linux doesn't seem to care about this error in the table, but it does
15
This allows us to move away from "some git commit on trunk"
24
affect at least the NOVA microhypervisor.
16
to a stable release for both TF-A and EDK2.
25
17
26
In theory we therefore have a choice between reporting the access
18
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
27
size as 2 (16 bit accesses) or 3 (32-bit accesses). In practice,
19
Message-id: 20241125125448.185504-1-marcin.juszkiewicz@linaro.org
28
Linux does not correctly handle the case where the table reports the
29
access size as 2: as of kernel commit 750b95887e5678, the code in
30
acpi_parse_spcr() tries to tell the serial driver to use 16 bit
31
accesses by passing "mmio16" in the option string, but the PL011
32
driver code in pl011_console_match() only recognizes "mmio" or
33
"mmio32". The result is that unless the user has enabled 'earlycon'
34
there is no console output from the guest kernel.
35
36
We therefore choose to report the access size as 32 bits; this works
37
for NOVA and also for Linux. It is also what the UEFI firmware on a
38
Raspberry Pi 4 reports, so we're in line with existing real-world
39
practice.
40
41
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1938
42
Signed-off-by: Udo Steinberg <udo@hypervisor.org>
43
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
20
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
44
[PMM: minor commit message tweaks; use 32 bit accesses]
45
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
46
---
22
---
47
hw/arm/virt-acpi-build.c | 4 ++--
23
tests/functional/test_aarch64_sbsaref.py | 20 ++++++++++----------
48
1 file changed, 2 insertions(+), 2 deletions(-)
24
1 file changed, 10 insertions(+), 10 deletions(-)
49
25
50
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
26
diff --git a/tests/functional/test_aarch64_sbsaref.py b/tests/functional/test_aarch64_sbsaref.py
51
index XXXXXXX..XXXXXXX 100644
27
index XXXXXXX..XXXXXXX 100755
52
--- a/hw/arm/virt-acpi-build.c
28
--- a/tests/functional/test_aarch64_sbsaref.py
53
+++ b/hw/arm/virt-acpi-build.c
29
+++ b/tests/functional/test_aarch64_sbsaref.py
54
@@ -XXX,XX +XXX,XX @@ build_spcr(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
30
@@ -XXX,XX +XXX,XX @@ def fetch_firmware(test):
55
build_append_int_noprefix(table_data, 3, 1); /* ARM PL011 UART */
31
56
build_append_int_noprefix(table_data, 0, 3); /* Reserved */
32
Used components:
57
/* Base Address */
33
58
- build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 8, 0, 1,
34
- - Trusted Firmware v2.11.0
59
+ build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 32, 0, 3,
35
- - Tianocore EDK2 4d4f569924
60
vms->memmap[VIRT_UART].base);
36
- - Tianocore EDK2-platforms 3f08401
61
/* Interrupt Type */
37
+ - Trusted Firmware v2.12.0
62
build_append_int_noprefix(table_data,
38
+ - Tianocore EDK2 edk2-stable202411
63
@@ -XXX,XX +XXX,XX @@ build_dbg2(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
39
+ - Tianocore EDK2-platforms 4b3530d
64
build_append_int_noprefix(table_data, 34, 2);
40
65
41
"""
66
/* BaseAddressRegister[] */
42
67
- build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 8, 0, 1,
43
@@ -XXX,XX +XXX,XX @@ class Aarch64SbsarefMachine(QemuSystemTest):
68
+ build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 32, 0, 3,
44
69
vms->memmap[VIRT_UART].base);
45
ASSET_FLASH0 = Asset(
70
46
('https://artifacts.codelinaro.org/artifactory/linaro-419-sbsa-ref/'
71
/* AddressSize[] */
47
- '20240619-148232/edk2/SBSA_FLASH0.fd.xz'),
48
- '0c954842a590988f526984de22e21ae0ab9cb351a0c99a8a58e928f0c7359cf7')
49
+ '20241122-189881/edk2/SBSA_FLASH0.fd.xz'),
50
+ '76eb89d42eebe324e4395329f47447cda9ac920aabcf99aca85424609c3384a5')
51
52
ASSET_FLASH1 = Asset(
53
('https://artifacts.codelinaro.org/artifactory/linaro-419-sbsa-ref/'
54
- '20240619-148232/edk2/SBSA_FLASH1.fd.xz'),
55
- 'c6ec39374c4d79bb9e9cdeeb6db44732d90bb4a334cec92002b3f4b9cac4b5ee')
56
+ '20241122-189881/edk2/SBSA_FLASH1.fd.xz'),
57
+ 'f850f243bd8dbd49c51e061e0f79f1697546938f454aeb59ab7d93e5f0d412fc')
58
59
def test_sbsaref_edk2_firmware(self):
60
61
@@ -XXX,XX +XXX,XX @@ def test_sbsaref_edk2_firmware(self):
62
63
# AP Trusted ROM
64
wait_for_console_pattern(self, "Booting Trusted Firmware")
65
- wait_for_console_pattern(self, "BL1: v2.11.0(release):")
66
+ wait_for_console_pattern(self, "BL1: v2.12.0(release):")
67
wait_for_console_pattern(self, "BL1: Booting BL2")
68
69
# Trusted Boot Firmware
70
- wait_for_console_pattern(self, "BL2: v2.11.0(release)")
71
+ wait_for_console_pattern(self, "BL2: v2.12.0(release)")
72
wait_for_console_pattern(self, "Booting BL31")
73
74
# EL3 Runtime Software
75
- wait_for_console_pattern(self, "BL31: v2.11.0(release)")
76
+ wait_for_console_pattern(self, "BL31: v2.12.0(release)")
77
78
# Non-trusted Firmware
79
wait_for_console_pattern(self, "UEFI firmware (version 1.0")
72
--
80
--
73
2.34.1
81
2.34.1
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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