This patch series improves the set of packets that can short-circuit
the commit packet logic and write the results directly during the
execution of each instruction in the packet.

The key observation is that checking for overlap between register reads
and writes is different from read-after-write.  For example, this packet
    { R0 = add(R0,R1); R6 = add(R6,R7) }
has an overlap between the reads and writes without doing a read after a
write.  Therefore, it is safe to write directly into the destination
registers during instruction execution.

Another example is a .new register read.  These can read from either the
destination register or a temporary location.

HVX instructions with generated helpers require special handling.
The semantics of the helpers are pass-by-reference, so we still need the
overlap check for these.

Taylor Simpson (3):
  Hexagon (target/hexagon) Analyze reads before writes
  Hexagon (target/hexagon) Enable more short-circuit packets (scalar
    core)
  Hexagon (target/hexagon) Enable more short-circuit packets (HVX)

 target/hexagon/translate.h          | 117 ++++++++++---
 target/hexagon/translate.c          |  75 +--------
 target/hexagon/README               |   7 +-
 target/hexagon/gen_analyze_funcs.py | 252 ++++++++++++----------------
 target/hexagon/gen_tcg_funcs.py     |   2 +-
 target/hexagon/hex_common.py        |  10 ++
 6 files changed, 227 insertions(+), 236 deletions(-)

-- 
2.34.1