1
The following changes since commit d762bf97931b58839316b68a570eecc6143c9e3e:
1
The following changes since commit a5ba0a7e4e150d1350a041f0d0ef9ca6c8d7c307:
2
2
3
Merge tag 'pull-target-arm-20231102' of https://git.linaro.org/people/pmaydell/qemu-arm into staging (2023-11-03 10:04:12 +0800)
3
Merge tag 'pull-aspeed-20241211' of https://github.com/legoater/qemu into staging (2024-12-11 15:16:47 +0000)
4
4
5
are available in the Git repository at:
5
are available in the Git repository at:
6
6
7
https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20231103
7
https://gitlab.com/bibo-mao/qemu.git pull-loongarch-20241213
8
8
9
for you to fetch changes up to f7077737531b40aa879d4644837aeda0f7fc6aa8:
9
for you to fetch changes up to 78aa256571aa06f32001bd80635a1858187c609b:
10
10
11
linux-user/loongarch64: Add LASX sigcontext save/restore (2023-11-03 14:13:46 +0800)
11
hw/intc/loongarch_pch: Code cleanup about loongarch_pch_pic (2024-12-13 14:39:39 +0800)
12
12
13
----------------------------------------------------------------
13
----------------------------------------------------------------
14
pull-loongarch-20231103
14
pull-loongarch-20241213
15
15
16
----------------------------------------------------------------
16
----------------------------------------------------------------
17
Richard Henderson (1):
17
Bibo Mao (8):
18
linux-user/loongarch64: Use traps to track LSX/LASX usage
18
include: Add loongarch_pic_common header file
19
include: Move struct LoongArchPCHPIC to loongarch_pic_common header file
20
hw/intc/loongarch_pch: Merge instance_init() into realize()
21
hw/intc/loongarch_pch: Rename LoongArchPCHPIC with LoongArchPICCommonState
22
hw/intc/loongarch_pch: Move some functions to file loongarch_pic_common
23
hw/intc/loongarch_pch: Inherit from loongarch_pic_common
24
hw/intc/loongarch_pch: Add pre_save and post_load interfaces
25
hw/intc/loongarch_pch: Code cleanup about loongarch_pch_pic
19
26
20
Song Gao (9):
27
hw/intc/loongarch_pch_pic.c | 106 +++++++++++----------------------
21
target/loongarch: Add cpu model 'max'
28
hw/intc/loongarch_pic_common.c | 97 ++++++++++++++++++++++++++++++
22
target/loongarch: Allow user enable/disable LSX/LASX features
29
hw/intc/meson.build | 2 +-
23
target/loongarch: Implement query-cpu-model-expansion
30
hw/loongarch/virt.c | 2 +-
24
target/loongarch: Support 4K page size
31
include/hw/intc/loongarch_pch_pic.h | 70 +++++-----------------
25
linux-user/loongarch64: Fix setup_extcontext alloc wrong fpu_context size
32
include/hw/intc/loongarch_pic_common.h | 82 +++++++++++++++++++++++++
26
linux-user/loongarch64: setup_sigframe() set 'end' context size 0
33
6 files changed, 230 insertions(+), 129 deletions(-)
27
linux-user/loongarch64: Use abi_{ulong,uint} types
34
create mode 100644 hw/intc/loongarch_pic_common.c
28
linux-user/loongarch64: Add LSX sigcontext save/restore
35
create mode 100644 include/hw/intc/loongarch_pic_common.h
29
linux-user/loongarch64: Add LASX sigcontext save/restore
30
31
linux-user/loongarch64/cpu_loop.c | 13 ++
32
linux-user/loongarch64/signal.c | 189 +++++++++++++++++++++++-----
33
qapi/machine-target.json | 6 +-
34
target/loongarch/cpu-param.h | 2 +-
35
target/loongarch/cpu.c | 74 +++++++++++
36
target/loongarch/cpu.h | 2 +
37
target/loongarch/insn_trans/trans_vec.c.inc | 11 --
38
target/loongarch/loongarch-qmp-cmds.c | 64 ++++++++++
39
target/loongarch/tlb_helper.c | 9 +-
40
9 files changed, 318 insertions(+), 52 deletions(-)
diff view generated by jsdifflib
New patch
1
Add common header file hw/intc/loongarch_pic_common.h, and move
2
some macro definition from hw/intc/loongarch_pch_pic.h to the common
3
header file.
1
4
5
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
6
Reviewed-by: Song Gao <gaosong@loongson.cn>
7
---
8
include/hw/intc/loongarch_pch_pic.h | 36 +++-------------------
9
include/hw/intc/loongarch_pic_common.h | 42 ++++++++++++++++++++++++++
10
2 files changed, 47 insertions(+), 31 deletions(-)
11
create mode 100644 include/hw/intc/loongarch_pic_common.h
12
13
diff --git a/include/hw/intc/loongarch_pch_pic.h b/include/hw/intc/loongarch_pch_pic.h
14
index XXXXXXX..XXXXXXX 100644
15
--- a/include/hw/intc/loongarch_pch_pic.h
16
+++ b/include/hw/intc/loongarch_pch_pic.h
17
@@ -XXX,XX +XXX,XX @@
18
* Copyright (c) 2021 Loongson Technology Corporation Limited
19
*/
20
21
-#include "hw/sysbus.h"
22
+#ifndef HW_LOONGARCH_PCH_PIC_H
23
+#define HW_LOONGARCH_PCH_PIC_H
24
+
25
+#include "hw/intc/loongarch_pic_common.h"
26
27
#define TYPE_LOONGARCH_PCH_PIC "loongarch_pch_pic"
28
#define PCH_PIC_NAME(name) TYPE_LOONGARCH_PCH_PIC#name
29
OBJECT_DECLARE_SIMPLE_TYPE(LoongArchPCHPIC, LOONGARCH_PCH_PIC)
30
31
-#define PCH_PIC_INT_ID_VAL 0x7000000UL
32
-#define PCH_PIC_INT_ID_VER 0x1UL
33
-
34
-#define PCH_PIC_INT_ID_LO 0x00
35
-#define PCH_PIC_INT_ID_HI 0x04
36
-#define PCH_PIC_INT_MASK_LO 0x20
37
-#define PCH_PIC_INT_MASK_HI 0x24
38
-#define PCH_PIC_HTMSI_EN_LO 0x40
39
-#define PCH_PIC_HTMSI_EN_HI 0x44
40
-#define PCH_PIC_INT_EDGE_LO 0x60
41
-#define PCH_PIC_INT_EDGE_HI 0x64
42
-#define PCH_PIC_INT_CLEAR_LO 0x80
43
-#define PCH_PIC_INT_CLEAR_HI 0x84
44
-#define PCH_PIC_AUTO_CTRL0_LO 0xc0
45
-#define PCH_PIC_AUTO_CTRL0_HI 0xc4
46
-#define PCH_PIC_AUTO_CTRL1_LO 0xe0
47
-#define PCH_PIC_AUTO_CTRL1_HI 0xe4
48
-#define PCH_PIC_ROUTE_ENTRY_OFFSET 0x100
49
-#define PCH_PIC_ROUTE_ENTRY_END 0x13f
50
-#define PCH_PIC_HTMSI_VEC_OFFSET 0x200
51
-#define PCH_PIC_HTMSI_VEC_END 0x23f
52
-#define PCH_PIC_INT_STATUS_LO 0x3a0
53
-#define PCH_PIC_INT_STATUS_HI 0x3a4
54
-#define PCH_PIC_INT_POL_LO 0x3e0
55
-#define PCH_PIC_INT_POL_HI 0x3e4
56
-
57
-#define STATUS_LO_START 0
58
-#define STATUS_HI_START 0x4
59
-#define POL_LO_START 0x40
60
-#define POL_HI_START 0x44
61
struct LoongArchPCHPIC {
62
SysBusDevice parent_obj;
63
qemu_irq parent_irq[64];
64
@@ -XXX,XX +XXX,XX @@ struct LoongArchPCHPIC {
65
MemoryRegion iomem8;
66
unsigned int irq_num;
67
};
68
+#endif /* HW_LOONGARCH_PCH_PIC_H */
69
diff --git a/include/hw/intc/loongarch_pic_common.h b/include/hw/intc/loongarch_pic_common.h
70
new file mode 100644
71
index XXXXXXX..XXXXXXX
72
--- /dev/null
73
+++ b/include/hw/intc/loongarch_pic_common.h
74
@@ -XXX,XX +XXX,XX @@
75
+/* SPDX-License-Identifier: GPL-2.0-or-later */
76
+/*
77
+ * LoongArch 7A1000 I/O interrupt controller definitions
78
+ * Copyright (c) 2024 Loongson Technology Corporation Limited
79
+ */
80
+
81
+#ifndef HW_LOONGARCH_PIC_COMMON_H
82
+#define HW_LOONGARCH_PIC_COMMON_H
83
+
84
+#include "hw/pci-host/ls7a.h"
85
+#include "hw/sysbus.h"
86
+
87
+#define PCH_PIC_INT_ID_VAL 0x7000000UL
88
+#define PCH_PIC_INT_ID_VER 0x1UL
89
+#define PCH_PIC_INT_ID_LO 0x00
90
+#define PCH_PIC_INT_ID_HI 0x04
91
+#define PCH_PIC_INT_MASK_LO 0x20
92
+#define PCH_PIC_INT_MASK_HI 0x24
93
+#define PCH_PIC_HTMSI_EN_LO 0x40
94
+#define PCH_PIC_HTMSI_EN_HI 0x44
95
+#define PCH_PIC_INT_EDGE_LO 0x60
96
+#define PCH_PIC_INT_EDGE_HI 0x64
97
+#define PCH_PIC_INT_CLEAR_LO 0x80
98
+#define PCH_PIC_INT_CLEAR_HI 0x84
99
+#define PCH_PIC_AUTO_CTRL0_LO 0xc0
100
+#define PCH_PIC_AUTO_CTRL0_HI 0xc4
101
+#define PCH_PIC_AUTO_CTRL1_LO 0xe0
102
+#define PCH_PIC_AUTO_CTRL1_HI 0xe4
103
+#define PCH_PIC_ROUTE_ENTRY_OFFSET 0x100
104
+#define PCH_PIC_ROUTE_ENTRY_END 0x13f
105
+#define PCH_PIC_HTMSI_VEC_OFFSET 0x200
106
+#define PCH_PIC_HTMSI_VEC_END 0x23f
107
+#define PCH_PIC_INT_STATUS_LO 0x3a0
108
+#define PCH_PIC_INT_STATUS_HI 0x3a4
109
+#define PCH_PIC_INT_POL_LO 0x3e0
110
+#define PCH_PIC_INT_POL_HI 0x3e4
111
+
112
+#define STATUS_LO_START 0
113
+#define STATUS_HI_START 0x4
114
+#define POL_LO_START 0x40
115
+#define POL_HI_START 0x44
116
+#endif /* HW_LOONGARCH_PIC_COMMON_H */
117
--
118
2.43.5
diff view generated by jsdifflib
New patch
1
Move structure LoongArchPCHPIC from header file loongarch_pch_pic.h
2
to file loongarch_pic_common.h, and rename structure name with
3
LoongArchPICCommonState.
1
4
5
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
6
Reviewed-by: Song Gao <gaosong@loongson.cn>
7
---
8
include/hw/intc/loongarch_pch_pic.h | 27 +------------------------
9
include/hw/intc/loongarch_pic_common.h | 28 ++++++++++++++++++++++++++
10
2 files changed, 29 insertions(+), 26 deletions(-)
11
12
diff --git a/include/hw/intc/loongarch_pch_pic.h b/include/hw/intc/loongarch_pch_pic.h
13
index XXXXXXX..XXXXXXX 100644
14
--- a/include/hw/intc/loongarch_pch_pic.h
15
+++ b/include/hw/intc/loongarch_pch_pic.h
16
@@ -XXX,XX +XXX,XX @@
17
18
#include "hw/intc/loongarch_pic_common.h"
19
20
+#define LoongArchPCHPIC LoongArchPICCommonState
21
#define TYPE_LOONGARCH_PCH_PIC "loongarch_pch_pic"
22
#define PCH_PIC_NAME(name) TYPE_LOONGARCH_PCH_PIC#name
23
OBJECT_DECLARE_SIMPLE_TYPE(LoongArchPCHPIC, LOONGARCH_PCH_PIC)
24
25
-struct LoongArchPCHPIC {
26
- SysBusDevice parent_obj;
27
- qemu_irq parent_irq[64];
28
- uint64_t int_mask; /*0x020 interrupt mask register*/
29
- uint64_t htmsi_en; /*0x040 1=msi*/
30
- uint64_t intedge; /*0x060 edge=1 level =0*/
31
- uint64_t intclr; /*0x080 for clean edge int,set 1 clean,set 0 is noused*/
32
- uint64_t auto_crtl0; /*0x0c0*/
33
- uint64_t auto_crtl1; /*0x0e0*/
34
- uint64_t last_intirr; /* edge detection */
35
- uint64_t intirr; /* 0x380 interrupt request register */
36
- uint64_t intisr; /* 0x3a0 interrupt service register */
37
- /*
38
- * 0x3e0 interrupt level polarity selection
39
- * register 0 for high level trigger
40
- */
41
- uint64_t int_polarity;
42
-
43
- uint8_t route_entry[64]; /*0x100 - 0x138*/
44
- uint8_t htmsi_vector[64]; /*0x200 - 0x238*/
45
-
46
- MemoryRegion iomem32_low;
47
- MemoryRegion iomem32_high;
48
- MemoryRegion iomem8;
49
- unsigned int irq_num;
50
-};
51
#endif /* HW_LOONGARCH_PCH_PIC_H */
52
diff --git a/include/hw/intc/loongarch_pic_common.h b/include/hw/intc/loongarch_pic_common.h
53
index XXXXXXX..XXXXXXX 100644
54
--- a/include/hw/intc/loongarch_pic_common.h
55
+++ b/include/hw/intc/loongarch_pic_common.h
56
@@ -XXX,XX +XXX,XX @@
57
#define STATUS_HI_START 0x4
58
#define POL_LO_START 0x40
59
#define POL_HI_START 0x44
60
+
61
+struct LoongArchPICCommonState {
62
+ SysBusDevice parent_obj;
63
+
64
+ qemu_irq parent_irq[64];
65
+ uint64_t int_mask; /* 0x020 interrupt mask register */
66
+ uint64_t htmsi_en; /* 0x040 1=msi */
67
+ uint64_t intedge; /* 0x060 edge=1 level=0 */
68
+ uint64_t intclr; /* 0x080 clean edge int, set 1 clean, 0 noused */
69
+ uint64_t auto_crtl0; /* 0x0c0 */
70
+ uint64_t auto_crtl1; /* 0x0e0 */
71
+ uint64_t last_intirr; /* edge detection */
72
+ uint64_t intirr; /* 0x380 interrupt request register */
73
+ uint64_t intisr; /* 0x3a0 interrupt service register */
74
+ /*
75
+ * 0x3e0 interrupt level polarity selection
76
+ * register 0 for high level trigger
77
+ */
78
+ uint64_t int_polarity;
79
+
80
+ uint8_t route_entry[64]; /* 0x100 - 0x138 */
81
+ uint8_t htmsi_vector[64]; /* 0x200 - 0x238 */
82
+
83
+ MemoryRegion iomem32_low;
84
+ MemoryRegion iomem32_high;
85
+ MemoryRegion iomem8;
86
+ unsigned int irq_num;
87
+};
88
#endif /* HW_LOONGARCH_PIC_COMMON_H */
89
--
90
2.43.5
diff view generated by jsdifflib
1
Signed-off-by: Song Gao <gaosong@loongson.cn>
1
Memory region is created in instance_init(), merge it into function
2
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2
realize(). There is no special class_init() for loongarch_pch object.
3
Message-Id: <20231101030816.2353416-7-gaosong@loongson.cn>
3
4
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
5
Reviewed-by: Song Gao <gaosong@loongson.cn>
4
---
6
---
5
linux-user/loongarch64/signal.c | 68 ++++++++++++++++++++++++++++++---
7
hw/intc/loongarch_pch_pic.c | 15 ++++-----------
6
1 file changed, 62 insertions(+), 6 deletions(-)
8
1 file changed, 4 insertions(+), 11 deletions(-)
7
9
8
diff --git a/linux-user/loongarch64/signal.c b/linux-user/loongarch64/signal.c
10
diff --git a/hw/intc/loongarch_pch_pic.c b/hw/intc/loongarch_pch_pic.c
9
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
10
--- a/linux-user/loongarch64/signal.c
12
--- a/hw/intc/loongarch_pch_pic.c
11
+++ b/linux-user/loongarch64/signal.c
13
+++ b/hw/intc/loongarch_pch_pic.c
12
@@ -XXX,XX +XXX,XX @@ struct target_lsx_context {
14
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_reset(DeviceState *d)
13
abi_uint fcsr;
15
static void loongarch_pch_pic_realize(DeviceState *dev, Error **errp)
14
} QEMU_ALIGNED(LSX_CTX_ALIGN);
16
{
15
17
LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(dev);
16
+#define LASX_CTX_MAGIC 0x41535801
18
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
17
+#define LASX_CTX_ALIGN 32
19
18
+struct target_lasx_context {
20
if (!s->irq_num || s->irq_num > VIRT_PCH_PIC_IRQ_NUM) {
19
+ abi_ulong regs[4 * 32];
21
error_setg(errp, "Invalid 'pic_irq_num'");
20
+ abi_ulong fcc;
22
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_realize(DeviceState *dev, Error **errp)
21
+ abi_uint fcsr;
23
22
+} QEMU_ALIGNED(LASX_CTX_ALIGN);
24
qdev_init_gpio_out(dev, s->parent_irq, s->irq_num);
23
+
25
qdev_init_gpio_in(dev, pch_pic_irq_handler, s->irq_num);
24
#define CONTEXT_INFO_ALIGN 16
26
-}
25
struct target_sctx_info {
27
-
26
abi_uint magic;
28
-static void loongarch_pch_pic_init(Object *obj)
27
@@ -XXX,XX +XXX,XX @@ struct extctx_layout {
29
-{
28
unsigned int flags;
30
- LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(obj);
29
struct ctx_layout fpu;
31
- SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
30
struct ctx_layout lsx;
32
-
31
+ struct ctx_layout lasx;
33
- memory_region_init_io(&s->iomem32_low, obj,
32
struct ctx_layout end;
34
+ memory_region_init_io(&s->iomem32_low, OBJECT(dev),
35
&loongarch_pch_pic_reg32_low_ops,
36
s, PCH_PIC_NAME(.reg32_part1), 0x100);
37
- memory_region_init_io(&s->iomem8, obj, &loongarch_pch_pic_reg8_ops,
38
+ memory_region_init_io(&s->iomem8, OBJECT(dev), &loongarch_pch_pic_reg8_ops,
39
s, PCH_PIC_NAME(.reg8), 0x2a0);
40
- memory_region_init_io(&s->iomem32_high, obj,
41
+ memory_region_init_io(&s->iomem32_high, OBJECT(dev),
42
&loongarch_pch_pic_reg32_high_ops,
43
s, PCH_PIC_NAME(.reg32_part2), 0xc60);
44
sysbus_init_mmio(sbd, &s->iomem32_low);
45
@@ -XXX,XX +XXX,XX @@ static const TypeInfo loongarch_pch_pic_info = {
46
.name = TYPE_LOONGARCH_PCH_PIC,
47
.parent = TYPE_SYS_BUS_DEVICE,
48
.instance_size = sizeof(LoongArchPCHPIC),
49
- .instance_init = loongarch_pch_pic_init,
50
.class_init = loongarch_pch_pic_class_init,
33
};
51
};
34
52
35
@@ -XXX,XX +XXX,XX @@ static abi_ptr setup_extcontext(CPULoongArchState *env,
36
/* For qemu, there is no lazy fp context switch, so fp always present. */
37
extctx->flags = SC_USED_FP;
38
39
- if (FIELD_EX64(env->CSR_EUEN, CSR_EUEN, SXE)) {
40
+ if (FIELD_EX64(env->CSR_EUEN, CSR_EUEN, ASXE)) {
41
+ sp = extframe_alloc(extctx, &extctx->lasx,
42
+ sizeof(struct target_lasx_context), LASX_CTX_ALIGN, sp);
43
+ } else if (FIELD_EX64(env->CSR_EUEN, CSR_EUEN, SXE)) {
44
sp = extframe_alloc(extctx, &extctx->lsx,
45
sizeof(struct target_lsx_context), LSX_CTX_ALIGN, sp);
46
-
47
} else {
48
sp = extframe_alloc(extctx, &extctx->fpu,
49
sizeof(struct target_fpu_context), FPU_CTX_ALIGN, sp);
50
@@ -XXX,XX +XXX,XX @@ static void setup_sigframe(CPULoongArchState *env,
51
* Set extension context
52
*/
53
54
- if (FIELD_EX64(env->CSR_EUEN, CSR_EUEN, SXE)) {
55
+ if (FIELD_EX64(env->CSR_EUEN, CSR_EUEN, ASXE)) {
56
+ struct target_lasx_context *lasx_ctx;
57
+ info = extctx->lasx.haddr;
58
+
59
+ __put_user(LASX_CTX_MAGIC, &info->magic);
60
+ __put_user(extctx->lasx.size, &info->size);
61
+
62
+ lasx_ctx = (struct target_lasx_context *)(info + 1);
63
+
64
+ for (i = 0; i < 32; ++i) {
65
+ __put_user(env->fpr[i].vreg.UD(0), &lasx_ctx->regs[4 * i]);
66
+ __put_user(env->fpr[i].vreg.UD(1), &lasx_ctx->regs[4 * i + 1]);
67
+ __put_user(env->fpr[i].vreg.UD(2), &lasx_ctx->regs[4 * i + 2]);
68
+ __put_user(env->fpr[i].vreg.UD(3), &lasx_ctx->regs[4 * i + 3]);
69
+ }
70
+ __put_user(read_fcc(env), &lasx_ctx->fcc);
71
+ __put_user(env->fcsr0, &lasx_ctx->fcsr);
72
+ } else if (FIELD_EX64(env->CSR_EUEN, CSR_EUEN, SXE)) {
73
struct target_lsx_context *lsx_ctx;
74
info = extctx->lsx.haddr;
75
76
@@ -XXX,XX +XXX,XX @@ static bool parse_extcontext(struct extctx_layout *extctx, abi_ptr frame)
77
extctx->lsx.size = size;
78
extctx->size += size;
79
break;
80
+ case LASX_CTX_MAGIC:
81
+ if (size < (sizeof(struct target_sctx_info) +
82
+ sizeof(struct target_lasx_context))) {
83
+ return false;
84
+ }
85
+ extctx->lasx.gaddr = frame;
86
+ extctx->lasx.size = size;
87
+ extctx->size += size;
88
+ break;
89
default:
90
return false;
91
}
92
@@ -XXX,XX +XXX,XX @@ static void restore_sigframe(CPULoongArchState *env,
93
__get_user(env->gpr[i], &sc->sc_regs[i]);
94
}
95
96
- if (extctx->lsx.haddr) {
97
+ if (extctx->lasx.haddr) {
98
+ struct target_lasx_context *lasx_ctx =
99
+ extctx->lasx.haddr + sizeof(struct target_sctx_info);
100
+
101
+ for (i = 0; i < 32; ++i) {
102
+ __get_user(env->fpr[i].vreg.UD(0), &lasx_ctx->regs[4 * i]);
103
+ __get_user(env->fpr[i].vreg.UD(1), &lasx_ctx->regs[4 * i + 1]);
104
+ __get_user(env->fpr[i].vreg.UD(2), &lasx_ctx->regs[4 * i + 2]);
105
+ __get_user(env->fpr[i].vreg.UD(3), &lasx_ctx->regs[4 * i + 3]);
106
+ }
107
+ __get_user(fcc, &lasx_ctx->fcc);
108
+ write_fcc(env, fcc);
109
+ __get_user(env->fcsr0, &lasx_ctx->fcsr);
110
+ restore_fp_status(env);
111
+ } else if (extctx->lsx.haddr) {
112
struct target_lsx_context *lsx_ctx =
113
extctx->lsx.haddr + sizeof(struct target_sctx_info);
114
115
@@ -XXX,XX +XXX,XX @@ void setup_rt_frame(int sig, struct target_sigaction *ka,
116
return;
117
}
118
119
- if (FIELD_EX64(env->CSR_EUEN, CSR_EUEN, SXE)) {
120
+ if (FIELD_EX64(env->CSR_EUEN, CSR_EUEN, ASXE)) {
121
+ extctx.lasx.haddr = (void *)frame + (extctx.lasx.gaddr - frame_addr);
122
+ extctx.end.haddr = (void *)frame + (extctx.end.gaddr - frame_addr);
123
+ } else if (FIELD_EX64(env->CSR_EUEN, CSR_EUEN, SXE)) {
124
extctx.lsx.haddr = (void *)frame + (extctx.lsx.gaddr - frame_addr);
125
extctx.end.haddr = (void *)frame + (extctx.end.gaddr - frame_addr);
126
} else {
127
@@ -XXX,XX +XXX,XX @@ long do_rt_sigreturn(CPULoongArchState *env)
128
goto badframe;
129
}
130
131
- if (extctx.lsx.gaddr) {
132
+ if (extctx.lasx.gaddr) {
133
+ extctx.lasx.haddr = (void *)frame + (extctx.lasx.gaddr - frame_addr);
134
+ } else if (extctx.lsx.gaddr) {
135
extctx.lsx.haddr = (void *)frame + (extctx.lsx.gaddr - frame_addr);
136
} else if (extctx.fpu.gaddr) {
137
extctx.fpu.haddr = (void *)frame + (extctx.fpu.gaddr - frame_addr);
138
--
53
--
139
2.25.1
54
2.43.5
diff view generated by jsdifflib
1
We use cpu la464 for the 'max' cpu.
1
With pic vmstate, rename structure name vmstate_loongarch_pch_pic with
2
vmstate_loongarch_pic_common, and with pic property rename
3
loongarch_pch_pic_properties with loongarch_pic_common_properties.
2
4
3
Signed-off-by: Song Gao <gaosong@loongson.cn>
5
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Song Gao <gaosong@loongson.cn>
5
Message-Id: <20231020084925.3457084-2-gaosong@loongson.cn>
6
---
7
---
7
target/loongarch/cpu.c | 7 +++++++
8
hw/intc/loongarch_pch_pic.c | 52 +++++++++++++++++++++++--------------
8
1 file changed, 7 insertions(+)
9
1 file changed, 32 insertions(+), 20 deletions(-)
9
10
10
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
11
diff --git a/hw/intc/loongarch_pch_pic.c b/hw/intc/loongarch_pch_pic.c
11
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
12
--- a/target/loongarch/cpu.c
13
--- a/hw/intc/loongarch_pch_pic.c
13
+++ b/target/loongarch/cpu.c
14
+++ b/hw/intc/loongarch_pch_pic.c
14
@@ -XXX,XX +XXX,XX @@ static void loongarch_la132_initfn(Object *obj)
15
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_reset(DeviceState *d)
15
env->cpucfg[1] = data;
16
s->int_polarity = 0x0;
16
}
17
}
17
18
18
+static void loongarch_max_initfn(Object *obj)
19
+static void loongarch_pic_common_realize(DeviceState *dev, Error **errp)
19
+{
20
+{
20
+ /* '-cpu max' for TCG: we use cpu la464. */
21
+ LoongArchPICCommonState *s = LOONGARCH_PCH_PIC(dev);
21
+ loongarch_la464_initfn(obj);
22
+
23
+ if (!s->irq_num || s->irq_num > VIRT_PCH_PIC_IRQ_NUM) {
24
+ error_setg(errp, "Invalid 'pic_irq_num'");
25
+ return;
26
+ }
22
+}
27
+}
23
+
28
+
24
static void loongarch_cpu_list_entry(gpointer data, gpointer user_data)
29
static void loongarch_pch_pic_realize(DeviceState *dev, Error **errp)
25
{
30
{
26
const char *typename = object_class_get_name(OBJECT_CLASS(data));
31
LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(dev);
27
@@ -XXX,XX +XXX,XX @@ static const TypeInfo loongarch_cpu_type_infos[] = {
32
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
28
},
33
+ Error *local_err = NULL;
29
DEFINE_LOONGARCH_CPU_TYPE(64, "la464", loongarch_la464_initfn),
34
30
DEFINE_LOONGARCH_CPU_TYPE(32, "la132", loongarch_la132_initfn),
35
- if (!s->irq_num || s->irq_num > VIRT_PCH_PIC_IRQ_NUM) {
31
+ DEFINE_LOONGARCH_CPU_TYPE(64, "max", loongarch_max_initfn),
36
- error_setg(errp, "Invalid 'pic_irq_num'");
37
+ loongarch_pic_common_realize(dev, &local_err);
38
+ if (local_err) {
39
+ error_propagate(errp, local_err);
40
return;
41
}
42
43
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_realize(DeviceState *dev, Error **errp)
44
45
}
46
47
-static Property loongarch_pch_pic_properties[] = {
48
- DEFINE_PROP_UINT32("pch_pic_irq_num", LoongArchPCHPIC, irq_num, 0),
49
+static Property loongarch_pic_common_properties[] = {
50
+ DEFINE_PROP_UINT32("pch_pic_irq_num", LoongArchPICCommonState, irq_num, 0),
51
DEFINE_PROP_END_OF_LIST(),
32
};
52
};
33
53
34
DEFINE_TYPES(loongarch_cpu_type_infos)
54
-static const VMStateDescription vmstate_loongarch_pch_pic = {
55
- .name = TYPE_LOONGARCH_PCH_PIC,
56
+static const VMStateDescription vmstate_loongarch_pic_common = {
57
+ .name = "loongarch_pch_pic",
58
.version_id = 1,
59
.minimum_version_id = 1,
60
.fields = (const VMStateField[]) {
61
- VMSTATE_UINT64(int_mask, LoongArchPCHPIC),
62
- VMSTATE_UINT64(htmsi_en, LoongArchPCHPIC),
63
- VMSTATE_UINT64(intedge, LoongArchPCHPIC),
64
- VMSTATE_UINT64(intclr, LoongArchPCHPIC),
65
- VMSTATE_UINT64(auto_crtl0, LoongArchPCHPIC),
66
- VMSTATE_UINT64(auto_crtl1, LoongArchPCHPIC),
67
- VMSTATE_UINT8_ARRAY(route_entry, LoongArchPCHPIC, 64),
68
- VMSTATE_UINT8_ARRAY(htmsi_vector, LoongArchPCHPIC, 64),
69
- VMSTATE_UINT64(last_intirr, LoongArchPCHPIC),
70
- VMSTATE_UINT64(intirr, LoongArchPCHPIC),
71
- VMSTATE_UINT64(intisr, LoongArchPCHPIC),
72
- VMSTATE_UINT64(int_polarity, LoongArchPCHPIC),
73
+ VMSTATE_UINT64(int_mask, LoongArchPICCommonState),
74
+ VMSTATE_UINT64(htmsi_en, LoongArchPICCommonState),
75
+ VMSTATE_UINT64(intedge, LoongArchPICCommonState),
76
+ VMSTATE_UINT64(intclr, LoongArchPICCommonState),
77
+ VMSTATE_UINT64(auto_crtl0, LoongArchPICCommonState),
78
+ VMSTATE_UINT64(auto_crtl1, LoongArchPICCommonState),
79
+ VMSTATE_UINT8_ARRAY(route_entry, LoongArchPICCommonState, 64),
80
+ VMSTATE_UINT8_ARRAY(htmsi_vector, LoongArchPICCommonState, 64),
81
+ VMSTATE_UINT64(last_intirr, LoongArchPICCommonState),
82
+ VMSTATE_UINT64(intirr, LoongArchPICCommonState),
83
+ VMSTATE_UINT64(intisr, LoongArchPICCommonState),
84
+ VMSTATE_UINT64(int_polarity, LoongArchPICCommonState),
85
VMSTATE_END_OF_LIST()
86
}
87
};
88
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_class_init(ObjectClass *klass, void *data)
89
90
dc->realize = loongarch_pch_pic_realize;
91
device_class_set_legacy_reset(dc, loongarch_pch_pic_reset);
92
- dc->vmsd = &vmstate_loongarch_pch_pic;
93
- device_class_set_props(dc, loongarch_pch_pic_properties);
94
+ dc->vmsd = &vmstate_loongarch_pic_common;
95
+ device_class_set_props(dc, loongarch_pic_common_properties);
96
}
97
98
static const TypeInfo loongarch_pch_pic_info = {
35
--
99
--
36
2.25.1
100
2.43.5
diff view generated by jsdifflib
1
Some users may not need LSX/LASX, this patch allows the user
1
Move some common functions to file loongarch_pic_common.c, the common
2
enable/disable LSX/LASX features.
2
functions include loongarch_pic_common_realize(), property structure
3
loongarch_pic_common_properties and vmstate structure
4
vmstate_loongarch_pic_common.
3
5
4
e.g
6
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
5
'-cpu max,lsx=on,lasx=on' (default);
7
Reviewed-by: Song Gao <gaosong@loongson.cn>
6
'-cpu max,lsx=on,lasx=off' (enabled LSX);
8
---
7
'-cpu max,lsx=off,lasx=on' (enabled LASX, LSX);
9
hw/intc/loongarch_pch_pic.c | 37 +-----------------------------
8
'-cpu max,lsx=off' (disable LSX and LASX).
10
hw/intc/loongarch_pic_common.c | 41 ++++++++++++++++++++++++++++++++++
11
2 files changed, 42 insertions(+), 36 deletions(-)
12
create mode 100644 hw/intc/loongarch_pic_common.c
9
13
10
Signed-off-by: Song Gao <gaosong@loongson.cn>
14
diff --git a/hw/intc/loongarch_pch_pic.c b/hw/intc/loongarch_pch_pic.c
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-Id: <20231020084925.3457084-3-gaosong@loongson.cn>
13
---
14
target/loongarch/cpu.c | 67 ++++++++++++++++++++++++++++++++++++++++++
15
target/loongarch/cpu.h | 2 ++
16
2 files changed, 69 insertions(+)
17
18
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
19
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
20
--- a/target/loongarch/cpu.c
16
--- a/hw/intc/loongarch_pch_pic.c
21
+++ b/target/loongarch/cpu.c
17
+++ b/hw/intc/loongarch_pch_pic.c
22
@@ -XXX,XX +XXX,XX @@ static void loongarch_la464_initfn(Object *obj)
18
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_reset(DeviceState *d)
23
env->cpucfg[20] = data;
19
s->int_polarity = 0x0;
24
25
env->CSR_ASID = FIELD_DP64(0, CSR_ASID, ASIDBITS, 0xa);
26
+ loongarch_cpu_post_init(obj);
27
}
20
}
28
21
29
static void loongarch_la132_initfn(Object *obj)
22
-static void loongarch_pic_common_realize(DeviceState *dev, Error **errp)
30
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps loongarch_qemu_ops = {
23
-{
31
};
24
- LoongArchPICCommonState *s = LOONGARCH_PCH_PIC(dev);
32
#endif
25
-
33
26
- if (!s->irq_num || s->irq_num > VIRT_PCH_PIC_IRQ_NUM) {
34
+static bool loongarch_get_lsx(Object *obj, Error **errp)
27
- error_setg(errp, "Invalid 'pic_irq_num'");
28
- return;
29
- }
30
-}
31
-
32
+#include "loongarch_pic_common.c"
33
static void loongarch_pch_pic_realize(DeviceState *dev, Error **errp)
34
{
35
LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(dev);
36
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_realize(DeviceState *dev, Error **errp)
37
38
}
39
40
-static Property loongarch_pic_common_properties[] = {
41
- DEFINE_PROP_UINT32("pch_pic_irq_num", LoongArchPICCommonState, irq_num, 0),
42
- DEFINE_PROP_END_OF_LIST(),
43
-};
44
-
45
-static const VMStateDescription vmstate_loongarch_pic_common = {
46
- .name = "loongarch_pch_pic",
47
- .version_id = 1,
48
- .minimum_version_id = 1,
49
- .fields = (const VMStateField[]) {
50
- VMSTATE_UINT64(int_mask, LoongArchPICCommonState),
51
- VMSTATE_UINT64(htmsi_en, LoongArchPICCommonState),
52
- VMSTATE_UINT64(intedge, LoongArchPICCommonState),
53
- VMSTATE_UINT64(intclr, LoongArchPICCommonState),
54
- VMSTATE_UINT64(auto_crtl0, LoongArchPICCommonState),
55
- VMSTATE_UINT64(auto_crtl1, LoongArchPICCommonState),
56
- VMSTATE_UINT8_ARRAY(route_entry, LoongArchPICCommonState, 64),
57
- VMSTATE_UINT8_ARRAY(htmsi_vector, LoongArchPICCommonState, 64),
58
- VMSTATE_UINT64(last_intirr, LoongArchPICCommonState),
59
- VMSTATE_UINT64(intirr, LoongArchPICCommonState),
60
- VMSTATE_UINT64(intisr, LoongArchPICCommonState),
61
- VMSTATE_UINT64(int_polarity, LoongArchPICCommonState),
62
- VMSTATE_END_OF_LIST()
63
- }
64
-};
65
-
66
static void loongarch_pch_pic_class_init(ObjectClass *klass, void *data)
67
{
68
DeviceClass *dc = DEVICE_CLASS(klass);
69
diff --git a/hw/intc/loongarch_pic_common.c b/hw/intc/loongarch_pic_common.c
70
new file mode 100644
71
index XXXXXXX..XXXXXXX
72
--- /dev/null
73
+++ b/hw/intc/loongarch_pic_common.c
74
@@ -XXX,XX +XXX,XX @@
75
+/* SPDX-License-Identifier: GPL-2.0-or-later */
76
+/*
77
+ * QEMU Loongson 7A1000 I/O interrupt controller.
78
+ * Copyright (C) 2024 Loongson Technology Corporation Limited
79
+ */
80
+
81
+static void loongarch_pic_common_realize(DeviceState *dev, Error **errp)
35
+{
82
+{
36
+ LoongArchCPU *cpu = LOONGARCH_CPU(obj);
83
+ LoongArchPICCommonState *s = LOONGARCH_PCH_PIC(dev);
37
+ bool ret;
38
+
84
+
39
+ if (FIELD_EX32(cpu->env.cpucfg[2], CPUCFG2, LSX)) {
85
+ if (!s->irq_num || s->irq_num > VIRT_PCH_PIC_IRQ_NUM) {
40
+ ret = true;
86
+ error_setg(errp, "Invalid 'pic_irq_num'");
41
+ } else {
87
+ return;
42
+ ret = false;
43
+ }
44
+ return ret;
45
+}
46
+
47
+static void loongarch_set_lsx(Object *obj, bool value, Error **errp)
48
+{
49
+ LoongArchCPU *cpu = LOONGARCH_CPU(obj);
50
+
51
+ if (value) {
52
+ cpu->env.cpucfg[2] = FIELD_DP32(cpu->env.cpucfg[2], CPUCFG2, LSX, 1);
53
+ } else {
54
+ cpu->env.cpucfg[2] = FIELD_DP32(cpu->env.cpucfg[2], CPUCFG2, LSX, 0);
55
+ cpu->env.cpucfg[2] = FIELD_DP32(cpu->env.cpucfg[2], CPUCFG2, LASX, 0);
56
+ }
88
+ }
57
+}
89
+}
58
+
90
+
59
+static bool loongarch_get_lasx(Object *obj, Error **errp)
91
+static Property loongarch_pic_common_properties[] = {
60
+{
92
+ DEFINE_PROP_UINT32("pch_pic_irq_num", LoongArchPICCommonState, irq_num, 0),
61
+ LoongArchCPU *cpu = LOONGARCH_CPU(obj);
93
+ DEFINE_PROP_END_OF_LIST(),
62
+ bool ret;
94
+};
63
+
95
+
64
+ if (FIELD_EX32(cpu->env.cpucfg[2], CPUCFG2, LASX)) {
96
+static const VMStateDescription vmstate_loongarch_pic_common = {
65
+ ret = true;
97
+ .name = "loongarch_pch_pic",
66
+ } else {
98
+ .version_id = 1,
67
+ ret = false;
99
+ .minimum_version_id = 1,
100
+ .fields = (const VMStateField[]) {
101
+ VMSTATE_UINT64(int_mask, LoongArchPICCommonState),
102
+ VMSTATE_UINT64(htmsi_en, LoongArchPICCommonState),
103
+ VMSTATE_UINT64(intedge, LoongArchPICCommonState),
104
+ VMSTATE_UINT64(intclr, LoongArchPICCommonState),
105
+ VMSTATE_UINT64(auto_crtl0, LoongArchPICCommonState),
106
+ VMSTATE_UINT64(auto_crtl1, LoongArchPICCommonState),
107
+ VMSTATE_UINT8_ARRAY(route_entry, LoongArchPICCommonState, 64),
108
+ VMSTATE_UINT8_ARRAY(htmsi_vector, LoongArchPICCommonState, 64),
109
+ VMSTATE_UINT64(last_intirr, LoongArchPICCommonState),
110
+ VMSTATE_UINT64(intirr, LoongArchPICCommonState),
111
+ VMSTATE_UINT64(intisr, LoongArchPICCommonState),
112
+ VMSTATE_UINT64(int_polarity, LoongArchPICCommonState),
113
+ VMSTATE_END_OF_LIST()
68
+ }
114
+ }
69
+ return ret;
115
+};
70
+}
71
+
72
+static void loongarch_set_lasx(Object *obj, bool value, Error **errp)
73
+{
74
+ LoongArchCPU *cpu = LOONGARCH_CPU(obj);
75
+
76
+ if (value) {
77
+    if (!FIELD_EX32(cpu->env.cpucfg[2], CPUCFG2, LSX)) {
78
+ cpu->env.cpucfg[2] = FIELD_DP32(cpu->env.cpucfg[2], CPUCFG2, LSX, 1);
79
+    }
80
+ cpu->env.cpucfg[2] = FIELD_DP32(cpu->env.cpucfg[2], CPUCFG2, LASX, 1);
81
+ } else {
82
+ cpu->env.cpucfg[2] = FIELD_DP32(cpu->env.cpucfg[2], CPUCFG2, LASX, 0);
83
+ }
84
+}
85
+
86
+void loongarch_cpu_post_init(Object *obj)
87
+{
88
+ LoongArchCPU *cpu = LOONGARCH_CPU(obj);
89
+
90
+ if (FIELD_EX32(cpu->env.cpucfg[2], CPUCFG2, LSX)) {
91
+ object_property_add_bool(obj, "lsx", loongarch_get_lsx,
92
+ loongarch_set_lsx);
93
+ }
94
+ if (FIELD_EX32(cpu->env.cpucfg[2], CPUCFG2, LASX)) {
95
+ object_property_add_bool(obj, "lasx", loongarch_get_lasx,
96
+ loongarch_set_lasx);
97
+ }
98
+}
99
+
100
static void loongarch_cpu_init(Object *obj)
101
{
102
#ifndef CONFIG_USER_ONLY
103
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
104
index XXXXXXX..XXXXXXX 100644
105
--- a/target/loongarch/cpu.h
106
+++ b/target/loongarch/cpu.h
107
@@ -XXX,XX +XXX,XX @@ void loongarch_cpu_list(void);
108
#define LOONGARCH_CPU_TYPE_NAME(model) model LOONGARCH_CPU_TYPE_SUFFIX
109
#define CPU_RESOLVING_TYPE TYPE_LOONGARCH_CPU
110
111
+void loongarch_cpu_post_init(Object *obj);
112
+
113
#endif /* LOONGARCH_CPU_H */
114
--
116
--
115
2.25.1
117
2.43.5
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set TYPE_LOONGARCH_PIC inherit from TYPE_LOONGARCH_PIC_COMMON object,
2
it shares vmsate and property of TYPE_LOONGARCH_PIC_COMMON, and has
3
its own realize() function.
2
4
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
4
Message-Id: <20231101030816.2353416-2-gaosong@loongson.cn>
6
Reviewed-by: Song Gao <gaosong@loongson.cn>
5
Signed-off-by: Song Gao <gaosong@loongson.cn>
6
---
7
---
7
linux-user/loongarch64/cpu_loop.c | 13 +++++++++++++
8
hw/intc/loongarch_pch_pic.c | 38 ++++++++++++--------------
8
target/loongarch/insn_trans/trans_vec.c.inc | 11 -----------
9
hw/intc/loongarch_pic_common.c | 32 +++++++++++++++++++++-
9
2 files changed, 13 insertions(+), 11 deletions(-)
10
hw/intc/meson.build | 2 +-
11
include/hw/intc/loongarch_pch_pic.h | 21 +++++++++++---
12
include/hw/intc/loongarch_pic_common.h | 10 +++++++
13
5 files changed, 77 insertions(+), 26 deletions(-)
10
14
11
diff --git a/linux-user/loongarch64/cpu_loop.c b/linux-user/loongarch64/cpu_loop.c
15
diff --git a/hw/intc/loongarch_pch_pic.c b/hw/intc/loongarch_pch_pic.c
12
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
13
--- a/linux-user/loongarch64/cpu_loop.c
17
--- a/hw/intc/loongarch_pch_pic.c
14
+++ b/linux-user/loongarch64/cpu_loop.c
18
+++ b/hw/intc/loongarch_pch_pic.c
15
@@ -XXX,XX +XXX,XX @@ void cpu_loop(CPULoongArchState *env)
19
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_reset(DeviceState *d)
16
case EXCCODE_BCE:
20
s->int_polarity = 0x0;
17
force_sig_fault(TARGET_SIGSYS, TARGET_SI_KERNEL, env->pc);
21
}
18
break;
22
19
+
23
-#include "loongarch_pic_common.c"
20
+ /*
24
-static void loongarch_pch_pic_realize(DeviceState *dev, Error **errp)
21
+ * Begin with LSX and LASX disabled, then enable on the first trap.
25
+static void loongarch_pic_realize(DeviceState *dev, Error **errp)
22
+ * In this way we can tell if the unit is in use. This is used to
23
+ * choose the layout of any signal frame.
24
+ */
25
+ case EXCCODE_SXD:
26
+ env->CSR_EUEN |= R_CSR_EUEN_SXE_MASK;
27
+ break;
28
+ case EXCCODE_ASXD:
29
+ env->CSR_EUEN |= R_CSR_EUEN_ASXE_MASK;
30
+ break;
31
+
32
case EXCP_ATOMIC:
33
cpu_exec_step_atomic(cs);
34
break;
35
diff --git a/target/loongarch/insn_trans/trans_vec.c.inc b/target/loongarch/insn_trans/trans_vec.c.inc
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/loongarch/insn_trans/trans_vec.c.inc
38
+++ b/target/loongarch/insn_trans/trans_vec.c.inc
39
@@ -XXX,XX +XXX,XX @@
40
* Copyright (c) 2022-2023 Loongson Technology Corporation Limited
41
*/
42
43
-#ifndef CONFIG_USER_ONLY
44
-
45
static bool check_vec(DisasContext *ctx, uint32_t oprsz)
46
{
26
{
47
if ((oprsz == 16) && ((ctx->base.tb->flags & HW_FLAGS_EUEN_SXE) == 0)) {
27
- LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(dev);
48
@@ -XXX,XX +XXX,XX @@ static bool check_vec(DisasContext *ctx, uint32_t oprsz)
28
- SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
49
return true;
29
+ LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(dev);
30
+ LoongarchPICClass *lpc = LOONGARCH_PIC_GET_CLASS(dev);
31
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
32
Error *local_err = NULL;
33
34
- loongarch_pic_common_realize(dev, &local_err);
35
+ lpc->parent_realize(dev, &local_err);
36
if (local_err) {
37
error_propagate(errp, local_err);
38
return;
39
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_realize(DeviceState *dev, Error **errp)
40
50
}
41
}
51
42
52
-#else
43
-static void loongarch_pch_pic_class_init(ObjectClass *klass, void *data)
53
-
44
+static void loongarch_pic_class_init(ObjectClass *klass, void *data)
54
-static bool check_vec(DisasContext *ctx, uint32_t oprsz)
45
{
46
DeviceClass *dc = DEVICE_CLASS(klass);
47
+ LoongarchPICClass *lpc = LOONGARCH_PIC_CLASS(klass);
48
49
- dc->realize = loongarch_pch_pic_realize;
50
device_class_set_legacy_reset(dc, loongarch_pch_pic_reset);
51
- dc->vmsd = &vmstate_loongarch_pic_common;
52
- device_class_set_props(dc, loongarch_pic_common_properties);
53
+ device_class_set_parent_realize(dc, loongarch_pic_realize,
54
+ &lpc->parent_realize);
55
}
56
57
-static const TypeInfo loongarch_pch_pic_info = {
58
- .name = TYPE_LOONGARCH_PCH_PIC,
59
- .parent = TYPE_SYS_BUS_DEVICE,
60
- .instance_size = sizeof(LoongArchPCHPIC),
61
- .class_init = loongarch_pch_pic_class_init,
62
+static const TypeInfo loongarch_pic_types[] = {
63
+ {
64
+ .name = TYPE_LOONGARCH_PIC,
65
+ .parent = TYPE_LOONGARCH_PIC_COMMON,
66
+ .instance_size = sizeof(LoongarchPICState),
67
+ .class_size = sizeof(LoongarchPICClass),
68
+ .class_init = loongarch_pic_class_init,
69
+ }
70
};
71
72
-static void loongarch_pch_pic_register_types(void)
55
-{
73
-{
56
- return true;
74
- type_register_static(&loongarch_pch_pic_info);
57
-}
75
-}
58
-
76
-
59
-#endif
77
-type_init(loongarch_pch_pic_register_types)
60
-
78
+DEFINE_TYPES(loongarch_pic_types)
61
static bool gen_vvvv_ptr_vl(DisasContext *ctx, arg_vvvv *a, uint32_t oprsz,
79
diff --git a/hw/intc/loongarch_pic_common.c b/hw/intc/loongarch_pic_common.c
62
gen_helper_gvec_4_ptr *fn)
80
index XXXXXXX..XXXXXXX 100644
81
--- a/hw/intc/loongarch_pic_common.c
82
+++ b/hw/intc/loongarch_pic_common.c
83
@@ -XXX,XX +XXX,XX @@
84
* Copyright (C) 2024 Loongson Technology Corporation Limited
85
*/
86
87
+#include "qemu/osdep.h"
88
+#include "qapi/error.h"
89
+#include "hw/intc/loongarch_pic_common.h"
90
+#include "hw/qdev-properties.h"
91
+#include "migration/vmstate.h"
92
+
93
static void loongarch_pic_common_realize(DeviceState *dev, Error **errp)
63
{
94
{
95
- LoongArchPICCommonState *s = LOONGARCH_PCH_PIC(dev);
96
+ LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(dev);
97
98
if (!s->irq_num || s->irq_num > VIRT_PCH_PIC_IRQ_NUM) {
99
error_setg(errp, "Invalid 'pic_irq_num'");
100
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_loongarch_pic_common = {
101
VMSTATE_END_OF_LIST()
102
}
103
};
104
+
105
+static void loongarch_pic_common_class_init(ObjectClass *klass, void *data)
106
+{
107
+ DeviceClass *dc = DEVICE_CLASS(klass);
108
+ LoongArchPICCommonClass *lpcc = LOONGARCH_PIC_COMMON_CLASS(klass);
109
+
110
+ device_class_set_parent_realize(dc, loongarch_pic_common_realize,
111
+ &lpcc->parent_realize);
112
+ device_class_set_props(dc, loongarch_pic_common_properties);
113
+ dc->vmsd = &vmstate_loongarch_pic_common;
114
+}
115
+
116
+static const TypeInfo loongarch_pic_common_types[] = {
117
+ {
118
+ .name = TYPE_LOONGARCH_PIC_COMMON,
119
+ .parent = TYPE_SYS_BUS_DEVICE,
120
+ .instance_size = sizeof(LoongArchPICCommonState),
121
+ .class_size = sizeof(LoongArchPICCommonClass),
122
+ .class_init = loongarch_pic_common_class_init,
123
+ .abstract = true,
124
+ }
125
+};
126
+
127
+DEFINE_TYPES(loongarch_pic_common_types)
128
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
129
index XXXXXXX..XXXXXXX 100644
130
--- a/hw/intc/meson.build
131
+++ b/hw/intc/meson.build
132
@@ -XXX,XX +XXX,XX @@ specific_ss.add(when: 'CONFIG_M68K_IRQC', if_true: files('m68k_irqc.c'))
133
specific_ss.add(when: 'CONFIG_LOONGSON_IPI_COMMON', if_true: files('loongson_ipi_common.c'))
134
specific_ss.add(when: 'CONFIG_LOONGSON_IPI', if_true: files('loongson_ipi.c'))
135
specific_ss.add(when: 'CONFIG_LOONGARCH_IPI', if_true: files('loongarch_ipi.c'))
136
-specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_PIC', if_true: files('loongarch_pch_pic.c'))
137
+specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_PIC', if_true: files('loongarch_pch_pic.c', 'loongarch_pic_common.c'))
138
specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_MSI', if_true: files('loongarch_pch_msi.c'))
139
specific_ss.add(when: 'CONFIG_LOONGARCH_EXTIOI', if_true: files('loongarch_extioi.c'))
140
diff --git a/include/hw/intc/loongarch_pch_pic.h b/include/hw/intc/loongarch_pch_pic.h
141
index XXXXXXX..XXXXXXX 100644
142
--- a/include/hw/intc/loongarch_pch_pic.h
143
+++ b/include/hw/intc/loongarch_pch_pic.h
144
@@ -XXX,XX +XXX,XX @@
145
146
#include "hw/intc/loongarch_pic_common.h"
147
148
-#define LoongArchPCHPIC LoongArchPICCommonState
149
-#define TYPE_LOONGARCH_PCH_PIC "loongarch_pch_pic"
150
-#define PCH_PIC_NAME(name) TYPE_LOONGARCH_PCH_PIC#name
151
-OBJECT_DECLARE_SIMPLE_TYPE(LoongArchPCHPIC, LOONGARCH_PCH_PIC)
152
+#define TYPE_LOONGARCH_PIC "loongarch_pic"
153
+#define PCH_PIC_NAME(name) TYPE_LOONGARCH_PIC#name
154
+OBJECT_DECLARE_TYPE(LoongarchPICState, LoongarchPICClass, LOONGARCH_PIC)
155
+
156
+struct LoongarchPICState {
157
+ LoongArchPICCommonState parent_obj;
158
+};
159
+
160
+struct LoongarchPICClass {
161
+ LoongArchPICCommonClass parent_class;
162
+
163
+ DeviceRealize parent_realize;
164
+};
165
+
166
+#define TYPE_LOONGARCH_PCH_PIC TYPE_LOONGARCH_PIC
167
+typedef struct LoongArchPICCommonState LoongArchPCHPIC;
168
+#define LOONGARCH_PCH_PIC(obj) ((struct LoongArchPICCommonState *)(obj))
169
170
#endif /* HW_LOONGARCH_PCH_PIC_H */
171
diff --git a/include/hw/intc/loongarch_pic_common.h b/include/hw/intc/loongarch_pic_common.h
172
index XXXXXXX..XXXXXXX 100644
173
--- a/include/hw/intc/loongarch_pic_common.h
174
+++ b/include/hw/intc/loongarch_pic_common.h
175
@@ -XXX,XX +XXX,XX @@
176
#define POL_LO_START 0x40
177
#define POL_HI_START 0x44
178
179
+#define TYPE_LOONGARCH_PIC_COMMON "loongarch_pic_common"
180
+OBJECT_DECLARE_TYPE(LoongArchPICCommonState,
181
+ LoongArchPICCommonClass, LOONGARCH_PIC_COMMON)
182
+
183
struct LoongArchPICCommonState {
184
SysBusDevice parent_obj;
185
186
@@ -XXX,XX +XXX,XX @@ struct LoongArchPICCommonState {
187
MemoryRegion iomem8;
188
unsigned int irq_num;
189
};
190
+
191
+struct LoongArchPICCommonClass {
192
+ SysBusDeviceClass parent_class;
193
+
194
+ DeviceRealize parent_realize;
195
+};
196
#endif /* HW_LOONGARCH_PIC_COMMON_H */
64
--
197
--
65
2.25.1
198
2.43.5
diff view generated by jsdifflib
1
Add support for the query-cpu-model-expansion QMP command to LoongArch.
1
Add vmstate pre_save and post_load interfaces, which can be used
2
We support query the cpu features.
2
by pic kvm driver in future.
3
3
4
e.g
4
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
5
la464 and max cpu support LSX/LASX, default enable,
5
Reviewed-by: Song Gao <gaosong@loongson.cn>
6
la132 not support LSX/LASX.
6
---
7
hw/intc/loongarch_pic_common.c | 26 ++++++++++++++++++++++++++
8
include/hw/intc/loongarch_pic_common.h | 2 ++
9
2 files changed, 28 insertions(+)
7
10
8
1. start with '-cpu max,lasx=off'
11
diff --git a/hw/intc/loongarch_pic_common.c b/hw/intc/loongarch_pic_common.c
9
10
(QEMU) query-cpu-model-expansion type=static model={"name":"max"}
11
{"return": {"model": {"name": "max", "props": {"lasx": false, "lsx": true}}}}
12
13
2. start with '-cpu la464,lasx=off'
14
(QEMU) query-cpu-model-expansion type=static model={"name":"la464"}
15
{"return": {"model": {"name": "max", "props": {"lasx": false, "lsx": true}}}
16
17
3. start with '-cpu la132,lasx=off'
18
qemu-system-loongarch64: can't apply global la132-loongarch-cpu.lasx=off: Property 'la132-loongarch-cpu.lasx' not found
19
20
4. start with '-cpu max,lasx=off' or start with '-cpu la464,lasx=off' query cpu model la132
21
(QEMU) query-cpu-model-expansion type=static model={"name":"la132"}
22
{"return": {"model": {"name": "la132"}}}
23
24
Acked-by: Markus Armbruster <armbru@redhat.com>
25
Signed-off-by: Song Gao <gaosong@loongson.cn>
26
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
27
Message-Id: <20231020084925.3457084-4-gaosong@loongson.cn>
28
---
29
qapi/machine-target.json | 6 ++-
30
target/loongarch/loongarch-qmp-cmds.c | 64 +++++++++++++++++++++++++++
31
2 files changed, 68 insertions(+), 2 deletions(-)
32
33
diff --git a/qapi/machine-target.json b/qapi/machine-target.json
34
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
35
--- a/qapi/machine-target.json
13
--- a/hw/intc/loongarch_pic_common.c
36
+++ b/qapi/machine-target.json
14
+++ b/hw/intc/loongarch_pic_common.c
37
@@ -XXX,XX +XXX,XX @@
15
@@ -XXX,XX +XXX,XX @@
38
'data': { 'model': 'CpuModelInfo' },
16
#include "hw/qdev-properties.h"
39
'if': { 'any': [ 'TARGET_S390X',
17
#include "migration/vmstate.h"
40
'TARGET_I386',
18
41
- 'TARGET_ARM' ] } }
19
+static int loongarch_pic_pre_save(void *opaque)
42
+ 'TARGET_ARM',
20
+{
43
+ 'TARGET_LOONGARCH64' ] } }
21
+ LoongArchPICCommonState *s = (LoongArchPICCommonState *)opaque;
44
22
+ LoongArchPICCommonClass *lpcc = LOONGARCH_PIC_COMMON_GET_CLASS(s);
45
##
46
# @query-cpu-model-expansion:
47
@@ -XXX,XX +XXX,XX @@
48
'returns': 'CpuModelExpansionInfo',
49
'if': { 'any': [ 'TARGET_S390X',
50
'TARGET_I386',
51
- 'TARGET_ARM' ] } }
52
+ 'TARGET_ARM',
53
+ 'TARGET_LOONGARCH64' ] } }
54
55
##
56
# @CpuDefinitionInfo:
57
diff --git a/target/loongarch/loongarch-qmp-cmds.c b/target/loongarch/loongarch-qmp-cmds.c
58
index XXXXXXX..XXXXXXX 100644
59
--- a/target/loongarch/loongarch-qmp-cmds.c
60
+++ b/target/loongarch/loongarch-qmp-cmds.c
61
@@ -XXX,XX +XXX,XX @@
62
*/
63
64
#include "qemu/osdep.h"
65
+#include "qapi/error.h"
66
#include "qapi/qapi-commands-machine-target.h"
67
#include "cpu.h"
68
+#include "qapi/qmp/qerror.h"
69
+#include "qapi/qmp/qdict.h"
70
+#include "qapi/qobject-input-visitor.h"
71
+#include "qom/qom-qobject.h"
72
73
static void loongarch_cpu_add_definition(gpointer data, gpointer user_data)
74
{
75
@@ -XXX,XX +XXX,XX @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
76
77
return cpu_list;
78
}
79
+
23
+
80
+static const char *cpu_model_advertised_features[] = {
24
+ if (lpcc->pre_save) {
81
+ "lsx", "lasx", NULL
25
+ return lpcc->pre_save(s);
82
+};
83
+
84
+CpuModelExpansionInfo *qmp_query_cpu_model_expansion(CpuModelExpansionType type,
85
+ CpuModelInfo *model,
86
+ Error **errp)
87
+{
88
+ CpuModelExpansionInfo *expansion_info;
89
+ QDict *qdict_out;
90
+ ObjectClass *oc;
91
+ Object *obj;
92
+ const char *name;
93
+ int i;
94
+
95
+ if (type != CPU_MODEL_EXPANSION_TYPE_STATIC) {
96
+ error_setg(errp, "The requested expansion type is not supported");
97
+ return NULL;
98
+ }
26
+ }
99
+
27
+
100
+ oc = cpu_class_by_name(TYPE_LOONGARCH_CPU, model->name);
28
+ return 0;
101
+ if (!oc) {
29
+}
102
+ error_setg(errp, "The CPU type '%s' is not a recognized LoongArch CPU type",
30
+
103
+ model->name);
31
+static int loongarch_pic_post_load(void *opaque, int version_id)
104
+ return NULL;
32
+{
33
+ LoongArchPICCommonState *s = (LoongArchPICCommonState *)opaque;
34
+ LoongArchPICCommonClass *lpcc = LOONGARCH_PIC_COMMON_GET_CLASS(s);
35
+
36
+ if (lpcc->post_load) {
37
+ return lpcc->post_load(s, version_id);
105
+ }
38
+ }
106
+
39
+
107
+ obj = object_new(object_class_get_name(oc));
40
+ return 0;
41
+}
108
+
42
+
109
+ expansion_info = g_new0(CpuModelExpansionInfo, 1);
43
static void loongarch_pic_common_realize(DeviceState *dev, Error **errp)
110
+ expansion_info->model = g_malloc0(sizeof(*expansion_info->model));
44
{
111
+ expansion_info->model->name = g_strdup(model->name);
45
LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(dev);
112
+
46
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_loongarch_pic_common = {
113
+ qdict_out = qdict_new();
47
.name = "loongarch_pch_pic",
114
+
48
.version_id = 1,
115
+ i = 0;
49
.minimum_version_id = 1,
116
+ while ((name = cpu_model_advertised_features[i++]) != NULL) {
50
+ .pre_save = loongarch_pic_pre_save,
117
+ ObjectProperty *prop = object_property_find(obj, name);
51
+ .post_load = loongarch_pic_post_load,
118
+ if (prop) {
52
.fields = (const VMStateField[]) {
119
+ QObject *value;
53
VMSTATE_UINT64(int_mask, LoongArchPICCommonState),
120
+
54
VMSTATE_UINT64(htmsi_en, LoongArchPICCommonState),
121
+ assert(prop->get);
55
diff --git a/include/hw/intc/loongarch_pic_common.h b/include/hw/intc/loongarch_pic_common.h
122
+ value = object_property_get_qobject(obj, name, &error_abort);
56
index XXXXXXX..XXXXXXX 100644
123
+
57
--- a/include/hw/intc/loongarch_pic_common.h
124
+ qdict_put_obj(qdict_out, name, value);
58
+++ b/include/hw/intc/loongarch_pic_common.h
125
+ }
59
@@ -XXX,XX +XXX,XX @@ struct LoongArchPICCommonClass {
126
+ }
60
SysBusDeviceClass parent_class;
127
+
61
128
+ if (!qdict_size(qdict_out)) {
62
DeviceRealize parent_realize;
129
+ qobject_unref(qdict_out);
63
+ int (*pre_save)(LoongArchPICCommonState *s);
130
+ } else {
64
+ int (*post_load)(LoongArchPICCommonState *s, int version_id);
131
+ expansion_info->model->props = QOBJECT(qdict_out);
65
};
132
+ }
66
#endif /* HW_LOONGARCH_PIC_COMMON_H */
133
+
134
+ object_unref(obj);
135
+
136
+ return expansion_info;
137
+}
138
--
67
--
139
2.25.1
68
2.43.5
diff view generated by jsdifflib
1
Signed-off-by: Song Gao <gaosong@loongson.cn>
1
Remove definition about LoongArchPCHPIC and LOONGARCH_PCH_PIC, and
2
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2
replace them with LoongArchPICCommonState and LOONGARCH_PIC_COMMON
3
Message-Id: <20231101030816.2353416-5-gaosong@loongson.cn>
3
separately. Also remove unnecessary header files.
4
5
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
6
Reviewed-by: Song Gao <gaosong@loongson.cn>
4
---
7
---
5
linux-user/loongarch64/signal.c | 24 ++++++++++++------------
8
hw/intc/loongarch_pch_pic.c | 24 ++++++++++--------------
6
1 file changed, 12 insertions(+), 12 deletions(-)
9
hw/loongarch/virt.c | 2 +-
10
include/hw/intc/loongarch_pch_pic.h | 4 ----
11
3 files changed, 11 insertions(+), 19 deletions(-)
7
12
8
diff --git a/linux-user/loongarch64/signal.c b/linux-user/loongarch64/signal.c
13
diff --git a/hw/intc/loongarch_pch_pic.c b/hw/intc/loongarch_pch_pic.c
9
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
10
--- a/linux-user/loongarch64/signal.c
15
--- a/hw/intc/loongarch_pch_pic.c
11
+++ b/linux-user/loongarch64/signal.c
16
+++ b/hw/intc/loongarch_pch_pic.c
12
@@ -XXX,XX +XXX,XX @@
17
@@ -XXX,XX +XXX,XX @@
13
#define SC_USED_FP (1 << 0)
18
14
19
#include "qemu/osdep.h"
15
struct target_sigcontext {
20
#include "qemu/bitops.h"
16
- uint64_t sc_pc;
21
-#include "hw/sysbus.h"
17
- uint64_t sc_regs[32];
22
-#include "hw/loongarch/virt.h"
18
- uint32_t sc_flags;
23
-#include "hw/pci-host/ls7a.h"
19
- uint64_t sc_extcontext[0] QEMU_ALIGNED(16);
24
#include "hw/irq.h"
20
+ abi_ulong sc_pc;
25
#include "hw/intc/loongarch_pch_pic.h"
21
+ abi_ulong sc_regs[32];
26
-#include "hw/qdev-properties.h"
22
+ abi_uint sc_flags;
27
-#include "migration/vmstate.h"
23
+ abi_ulong sc_extcontext[0] QEMU_ALIGNED(16);
28
#include "trace.h"
29
#include "qapi/error.h"
30
31
-static void pch_pic_update_irq(LoongArchPCHPIC *s, uint64_t mask, int level)
32
+static void pch_pic_update_irq(LoongArchPICCommonState *s, uint64_t mask,
33
+ int level)
34
{
35
uint64_t val;
36
int irq;
37
@@ -XXX,XX +XXX,XX @@ static void pch_pic_update_irq(LoongArchPCHPIC *s, uint64_t mask, int level)
38
39
static void pch_pic_irq_handler(void *opaque, int irq, int level)
40
{
41
- LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
42
+ LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(opaque);
43
uint64_t mask = 1ULL << irq;
44
45
assert(irq < s->irq_num);
46
@@ -XXX,XX +XXX,XX @@ static void pch_pic_irq_handler(void *opaque, int irq, int level)
47
static uint64_t loongarch_pch_pic_low_readw(void *opaque, hwaddr addr,
48
unsigned size)
49
{
50
- LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
51
+ LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(opaque);
52
uint64_t val = 0;
53
uint32_t offset = addr & 0xfff;
54
55
@@ -XXX,XX +XXX,XX @@ static uint64_t get_writew_val(uint64_t value, uint32_t target, bool hi)
56
static void loongarch_pch_pic_low_writew(void *opaque, hwaddr addr,
57
uint64_t value, unsigned size)
58
{
59
- LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
60
+ LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(opaque);
61
uint32_t offset, old_valid, data = (uint32_t)value;
62
uint64_t old, int_mask;
63
offset = addr & 0xfff;
64
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_low_writew(void *opaque, hwaddr addr,
65
static uint64_t loongarch_pch_pic_high_readw(void *opaque, hwaddr addr,
66
unsigned size)
67
{
68
- LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
69
+ LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(opaque);
70
uint64_t val = 0;
71
uint32_t offset = addr & 0xfff;
72
73
@@ -XXX,XX +XXX,XX @@ static uint64_t loongarch_pch_pic_high_readw(void *opaque, hwaddr addr,
74
static void loongarch_pch_pic_high_writew(void *opaque, hwaddr addr,
75
uint64_t value, unsigned size)
76
{
77
- LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
78
+ LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(opaque);
79
uint32_t offset, data = (uint32_t)value;
80
offset = addr & 0xfff;
81
82
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_high_writew(void *opaque, hwaddr addr,
83
static uint64_t loongarch_pch_pic_readb(void *opaque, hwaddr addr,
84
unsigned size)
85
{
86
- LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
87
+ LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(opaque);
88
uint64_t val = 0;
89
uint32_t offset = (addr & 0xfff) + PCH_PIC_ROUTE_ENTRY_OFFSET;
90
int64_t offset_tmp;
91
@@ -XXX,XX +XXX,XX @@ static uint64_t loongarch_pch_pic_readb(void *opaque, hwaddr addr,
92
static void loongarch_pch_pic_writeb(void *opaque, hwaddr addr,
93
uint64_t data, unsigned size)
94
{
95
- LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
96
+ LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(opaque);
97
int32_t offset_tmp;
98
uint32_t offset = (addr & 0xfff) + PCH_PIC_ROUTE_ENTRY_OFFSET;
99
100
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps loongarch_pch_pic_reg8_ops = {
101
102
static void loongarch_pch_pic_reset(DeviceState *d)
103
{
104
- LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(d);
105
+ LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(d);
106
int i;
107
108
s->int_mask = -1;
109
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
110
index XXXXXXX..XXXXXXX 100644
111
--- a/hw/loongarch/virt.c
112
+++ b/hw/loongarch/virt.c
113
@@ -XXX,XX +XXX,XX @@ static void virt_irq_init(LoongArchVirtMachineState *lvms)
114
/* Add Extend I/O Interrupt Controller node */
115
fdt_add_eiointc_node(lvms, &cpuintc_phandle, &eiointc_phandle);
116
117
- pch_pic = qdev_new(TYPE_LOONGARCH_PCH_PIC);
118
+ pch_pic = qdev_new(TYPE_LOONGARCH_PIC);
119
num = VIRT_PCH_PIC_IRQ_NUM;
120
qdev_prop_set_uint32(pch_pic, "pch_pic_irq_num", num);
121
d = SYS_BUS_DEVICE(pch_pic);
122
diff --git a/include/hw/intc/loongarch_pch_pic.h b/include/hw/intc/loongarch_pch_pic.h
123
index XXXXXXX..XXXXXXX 100644
124
--- a/include/hw/intc/loongarch_pch_pic.h
125
+++ b/include/hw/intc/loongarch_pch_pic.h
126
@@ -XXX,XX +XXX,XX @@ struct LoongarchPICClass {
127
DeviceRealize parent_realize;
24
};
128
};
25
129
26
QEMU_BUILD_BUG_ON(sizeof(struct target_sigcontext) != sizeof_sigcontext);
130
-#define TYPE_LOONGARCH_PCH_PIC TYPE_LOONGARCH_PIC
27
@@ -XXX,XX +XXX,XX @@ QEMU_BUILD_BUG_ON(offsetof(struct target_sigcontext, sc_regs)
131
-typedef struct LoongArchPICCommonState LoongArchPCHPIC;
28
#define FPU_CTX_MAGIC 0x46505501
132
-#define LOONGARCH_PCH_PIC(obj) ((struct LoongArchPICCommonState *)(obj))
29
#define FPU_CTX_ALIGN 8
133
-
30
struct target_fpu_context {
134
#endif /* HW_LOONGARCH_PCH_PIC_H */
31
- uint64_t regs[32];
32
- uint64_t fcc;
33
- uint32_t fcsr;
34
+ abi_ulong regs[32];
35
+ abi_ulong fcc;
36
+ abi_uint fcsr;
37
} QEMU_ALIGNED(FPU_CTX_ALIGN);
38
39
QEMU_BUILD_BUG_ON(offsetof(struct target_fpu_context, regs)
40
@@ -XXX,XX +XXX,XX @@ QEMU_BUILD_BUG_ON(offsetof(struct target_fpu_context, regs)
41
42
#define CONTEXT_INFO_ALIGN 16
43
struct target_sctx_info {
44
- uint32_t magic;
45
- uint32_t size;
46
- uint64_t padding;
47
+ abi_uint magic;
48
+ abi_uint size;
49
+ abi_ulong padding;
50
} QEMU_ALIGNED(CONTEXT_INFO_ALIGN);
51
52
QEMU_BUILD_BUG_ON(sizeof(struct target_sctx_info) != sizeof_sctx_info);
53
@@ -XXX,XX +XXX,XX @@ static bool parse_extcontext(struct extctx_layout *extctx, abi_ptr frame)
54
memset(extctx, 0, sizeof(*extctx));
55
56
while (1) {
57
- uint32_t magic, size;
58
+ abi_uint magic, size;
59
60
if (get_user_u32(magic, frame) || get_user_u32(size, frame + 4)) {
61
return false;
62
@@ -XXX,XX +XXX,XX @@ static void restore_sigframe(CPULoongArchState *env,
63
if (extctx->fpu.haddr) {
64
struct target_fpu_context *fpu_ctx =
65
extctx->fpu.haddr + sizeof(struct target_sctx_info);
66
- uint64_t fcc;
67
+ abi_ulong fcc;
68
69
for (i = 0; i < 32; ++i) {
70
__get_user(env->fpr[i].vreg.D(0), &fpu_ctx->regs[i]);
71
--
135
--
72
2.25.1
136
2.43.5
diff view generated by jsdifflib
1
See:
1
Add common header file include/hw/intc/loongarch_extioi_common.h, and
2
https://github.com/torvalds/linux/blob/master/arch/loongarch/kernel/signal.c
2
move some macro definition from include/hw/intc/loongarch_extioi.h to
3
the common header file.
3
4
4
The kernel setup_sigcontext() set end context size 0.
5
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
6
Reviewed-by: Song Gao <gaosong@loongson.cn>
7
---
8
include/hw/intc/loongarch_extioi.h | 50 +------------------
9
include/hw/intc/loongarch_extioi_common.h | 58 +++++++++++++++++++++++
10
2 files changed, 59 insertions(+), 49 deletions(-)
11
create mode 100644 include/hw/intc/loongarch_extioi_common.h
5
12
6
Signed-off-by: Song Gao <gaosong@loongson.cn>
13
diff --git a/include/hw/intc/loongarch_extioi.h b/include/hw/intc/loongarch_extioi.h
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-Id: <20231101030816.2353416-4-gaosong@loongson.cn>
9
---
10
linux-user/loongarch64/signal.c | 2 +-
11
1 file changed, 1 insertion(+), 1 deletion(-)
12
13
diff --git a/linux-user/loongarch64/signal.c b/linux-user/loongarch64/signal.c
14
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
15
--- a/linux-user/loongarch64/signal.c
15
--- a/include/hw/intc/loongarch_extioi.h
16
+++ b/linux-user/loongarch64/signal.c
16
+++ b/include/hw/intc/loongarch_extioi.h
17
@@ -XXX,XX +XXX,XX @@ static void setup_sigframe(CPULoongArchState *env,
17
@@ -XXX,XX +XXX,XX @@
18
*/
18
* Copyright (C) 2021 Loongson Technology Corporation Limited
19
info = extctx->end.haddr;
19
*/
20
__put_user(0, &info->magic);
20
21
- __put_user(extctx->end.size, &info->size);
21
-#include "hw/sysbus.h"
22
+ __put_user(0, &info->size);
22
-#include "hw/loongarch/virt.h"
23
}
23
-
24
24
#ifndef LOONGARCH_EXTIOI_H
25
static bool parse_extcontext(struct extctx_layout *extctx, abi_ptr frame)
25
#define LOONGARCH_EXTIOI_H
26
27
-#define LS3A_INTC_IP 8
28
-#define EXTIOI_IRQS (256)
29
-#define EXTIOI_IRQS_BITMAP_SIZE (256 / 8)
30
-/* irq from EXTIOI is routed to no more than 4 cpus */
31
-#define EXTIOI_CPUS (4)
32
-/* map to ipnum per 32 irqs */
33
-#define EXTIOI_IRQS_IPMAP_SIZE (256 / 32)
34
-#define EXTIOI_IRQS_COREMAP_SIZE 256
35
-#define EXTIOI_IRQS_NODETYPE_COUNT 16
36
-#define EXTIOI_IRQS_GROUP_COUNT 8
37
-
38
-#define APIC_OFFSET 0x400
39
-#define APIC_BASE (0x1000ULL + APIC_OFFSET)
40
-
41
-#define EXTIOI_NODETYPE_START (0x4a0 - APIC_OFFSET)
42
-#define EXTIOI_NODETYPE_END (0x4c0 - APIC_OFFSET)
43
-#define EXTIOI_IPMAP_START (0x4c0 - APIC_OFFSET)
44
-#define EXTIOI_IPMAP_END (0x4c8 - APIC_OFFSET)
45
-#define EXTIOI_ENABLE_START (0x600 - APIC_OFFSET)
46
-#define EXTIOI_ENABLE_END (0x620 - APIC_OFFSET)
47
-#define EXTIOI_BOUNCE_START (0x680 - APIC_OFFSET)
48
-#define EXTIOI_BOUNCE_END (0x6a0 - APIC_OFFSET)
49
-#define EXTIOI_ISR_START (0x700 - APIC_OFFSET)
50
-#define EXTIOI_ISR_END (0x720 - APIC_OFFSET)
51
-#define EXTIOI_COREISR_START (0x800 - APIC_OFFSET)
52
-#define EXTIOI_COREISR_END (0xB20 - APIC_OFFSET)
53
-#define EXTIOI_COREMAP_START (0xC00 - APIC_OFFSET)
54
-#define EXTIOI_COREMAP_END (0xD00 - APIC_OFFSET)
55
-#define EXTIOI_SIZE 0x800
56
-
57
-#define EXTIOI_VIRT_BASE (0x40000000)
58
-#define EXTIOI_VIRT_SIZE (0x1000)
59
-#define EXTIOI_VIRT_FEATURES (0x0)
60
-#define EXTIOI_HAS_VIRT_EXTENSION (0)
61
-#define EXTIOI_HAS_ENABLE_OPTION (1)
62
-#define EXTIOI_HAS_INT_ENCODE (2)
63
-#define EXTIOI_HAS_CPU_ENCODE (3)
64
-#define EXTIOI_VIRT_HAS_FEATURES (BIT(EXTIOI_HAS_VIRT_EXTENSION) \
65
- | BIT(EXTIOI_HAS_ENABLE_OPTION) \
66
- | BIT(EXTIOI_HAS_CPU_ENCODE))
67
-#define EXTIOI_VIRT_CONFIG (0x4)
68
-#define EXTIOI_ENABLE (1)
69
-#define EXTIOI_ENABLE_INT_ENCODE (2)
70
-#define EXTIOI_ENABLE_CPU_ENCODE (3)
71
-#define EXTIOI_VIRT_COREMAP_START (0x40)
72
-#define EXTIOI_VIRT_COREMAP_END (0x240)
73
+#include "hw/intc/loongarch_extioi_common.h"
74
75
typedef struct ExtIOICore {
76
uint32_t coreisr[EXTIOI_IRQS_GROUP_COUNT];
77
diff --git a/include/hw/intc/loongarch_extioi_common.h b/include/hw/intc/loongarch_extioi_common.h
78
new file mode 100644
79
index XXXXXXX..XXXXXXX
80
--- /dev/null
81
+++ b/include/hw/intc/loongarch_extioi_common.h
82
@@ -XXX,XX +XXX,XX @@
83
+/* SPDX-License-Identifier: GPL-2.0-or-later */
84
+/*
85
+ * LoongArch 3A5000 ext interrupt controller definitions
86
+ * Copyright (C) 2024 Loongson Technology Corporation Limited
87
+ */
88
+
89
+#ifndef LOONGARCH_EXTIOI_COMMON_H
90
+#define LOONGARCH_EXTIOI_COMMON_H
91
+
92
+#include "hw/sysbus.h"
93
+#include "hw/loongarch/virt.h"
94
+
95
+#define LS3A_INTC_IP 8
96
+#define EXTIOI_IRQS (256)
97
+#define EXTIOI_IRQS_BITMAP_SIZE (256 / 8)
98
+/* irq from EXTIOI is routed to no more than 4 cpus */
99
+#define EXTIOI_CPUS (4)
100
+/* map to ipnum per 32 irqs */
101
+#define EXTIOI_IRQS_IPMAP_SIZE (256 / 32)
102
+#define EXTIOI_IRQS_COREMAP_SIZE 256
103
+#define EXTIOI_IRQS_NODETYPE_COUNT 16
104
+#define EXTIOI_IRQS_GROUP_COUNT 8
105
+
106
+#define APIC_OFFSET 0x400
107
+#define APIC_BASE (0x1000ULL + APIC_OFFSET)
108
+#define EXTIOI_NODETYPE_START (0x4a0 - APIC_OFFSET)
109
+#define EXTIOI_NODETYPE_END (0x4c0 - APIC_OFFSET)
110
+#define EXTIOI_IPMAP_START (0x4c0 - APIC_OFFSET)
111
+#define EXTIOI_IPMAP_END (0x4c8 - APIC_OFFSET)
112
+#define EXTIOI_ENABLE_START (0x600 - APIC_OFFSET)
113
+#define EXTIOI_ENABLE_END (0x620 - APIC_OFFSET)
114
+#define EXTIOI_BOUNCE_START (0x680 - APIC_OFFSET)
115
+#define EXTIOI_BOUNCE_END (0x6a0 - APIC_OFFSET)
116
+#define EXTIOI_ISR_START (0x700 - APIC_OFFSET)
117
+#define EXTIOI_ISR_END (0x720 - APIC_OFFSET)
118
+#define EXTIOI_COREISR_START (0x800 - APIC_OFFSET)
119
+#define EXTIOI_COREISR_END (0xB20 - APIC_OFFSET)
120
+#define EXTIOI_COREMAP_START (0xC00 - APIC_OFFSET)
121
+#define EXTIOI_COREMAP_END (0xD00 - APIC_OFFSET)
122
+#define EXTIOI_SIZE 0x800
123
+
124
+#define EXTIOI_VIRT_BASE (0x40000000)
125
+#define EXTIOI_VIRT_SIZE (0x1000)
126
+#define EXTIOI_VIRT_FEATURES (0x0)
127
+#define EXTIOI_HAS_VIRT_EXTENSION (0)
128
+#define EXTIOI_HAS_ENABLE_OPTION (1)
129
+#define EXTIOI_HAS_INT_ENCODE (2)
130
+#define EXTIOI_HAS_CPU_ENCODE (3)
131
+#define EXTIOI_VIRT_HAS_FEATURES (BIT(EXTIOI_HAS_VIRT_EXTENSION) \
132
+ | BIT(EXTIOI_HAS_ENABLE_OPTION) \
133
+ | BIT(EXTIOI_HAS_CPU_ENCODE))
134
+#define EXTIOI_VIRT_CONFIG (0x4)
135
+#define EXTIOI_ENABLE (1)
136
+#define EXTIOI_ENABLE_INT_ENCODE (2)
137
+#define EXTIOI_ENABLE_CPU_ENCODE (3)
138
+#define EXTIOI_VIRT_COREMAP_START (0x40)
139
+#define EXTIOI_VIRT_COREMAP_END (0x240)
140
+#endif /* LOONGARCH_EXTIOI_H */
26
--
141
--
27
2.25.1
142
2.43.5
diff view generated by jsdifflib
1
See:
1
Move definiton of structure LoongArchExtIOI from header file loongarch_extioi.h
2
https://github.com/torvalds/linux/blob/master/arch/loongarch/kernel/signal.c
2
to file loongarch_extioi_common.h.
3
3
4
The alloc size is sizeof(struct target_fpu_context).
4
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
5
Reviewed-by: Song Gao <gaosong@loongson.cn>
6
---
7
include/hw/intc/loongarch_extioi.h | 26 ----------------------
8
include/hw/intc/loongarch_extioi_common.h | 27 +++++++++++++++++++++++
9
2 files changed, 27 insertions(+), 26 deletions(-)
5
10
6
Signed-off-by: Song Gao <gaosong@loongson.cn>
11
diff --git a/include/hw/intc/loongarch_extioi.h b/include/hw/intc/loongarch_extioi.h
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-Id: <20231101030816.2353416-3-gaosong@loongson.cn>
9
---
10
linux-user/loongarch64/signal.c | 2 +-
11
1 file changed, 1 insertion(+), 1 deletion(-)
12
13
diff --git a/linux-user/loongarch64/signal.c b/linux-user/loongarch64/signal.c
14
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
15
--- a/linux-user/loongarch64/signal.c
13
--- a/include/hw/intc/loongarch_extioi.h
16
+++ b/linux-user/loongarch64/signal.c
14
+++ b/include/hw/intc/loongarch_extioi.h
17
@@ -XXX,XX +XXX,XX @@ static abi_ptr setup_extcontext(struct extctx_layout *extctx, abi_ptr sp)
15
@@ -XXX,XX +XXX,XX @@
18
/* For qemu, there is no lazy fp context switch, so fp always present. */
16
19
extctx->flags = SC_USED_FP;
17
#include "hw/intc/loongarch_extioi_common.h"
20
sp = extframe_alloc(extctx, &extctx->fpu,
18
21
- sizeof(struct target_rt_sigframe), FPU_CTX_ALIGN, sp);
19
-typedef struct ExtIOICore {
22
+ sizeof(struct target_fpu_context), FPU_CTX_ALIGN, sp);
20
- uint32_t coreisr[EXTIOI_IRQS_GROUP_COUNT];
23
21
- DECLARE_BITMAP(sw_isr[LS3A_INTC_IP], EXTIOI_IRQS);
24
return sp;
22
- qemu_irq parent_irq[LS3A_INTC_IP];
25
}
23
-} ExtIOICore;
24
-
25
#define TYPE_LOONGARCH_EXTIOI "loongarch.extioi"
26
OBJECT_DECLARE_SIMPLE_TYPE(LoongArchExtIOI, LOONGARCH_EXTIOI)
27
-struct LoongArchExtIOI {
28
- SysBusDevice parent_obj;
29
- uint32_t num_cpu;
30
- uint32_t features;
31
- uint32_t status;
32
- /* hardware state */
33
- uint32_t nodetype[EXTIOI_IRQS_NODETYPE_COUNT / 2];
34
- uint32_t bounce[EXTIOI_IRQS_GROUP_COUNT];
35
- uint32_t isr[EXTIOI_IRQS / 32];
36
- uint32_t enable[EXTIOI_IRQS / 32];
37
- uint32_t ipmap[EXTIOI_IRQS_IPMAP_SIZE / 4];
38
- uint32_t coremap[EXTIOI_IRQS / 4];
39
- uint32_t sw_pending[EXTIOI_IRQS / 32];
40
- uint8_t sw_ipmap[EXTIOI_IRQS_IPMAP_SIZE];
41
- uint8_t sw_coremap[EXTIOI_IRQS];
42
- qemu_irq irq[EXTIOI_IRQS];
43
- ExtIOICore *cpu;
44
- MemoryRegion extioi_system_mem;
45
- MemoryRegion virt_extend;
46
-};
47
#endif /* LOONGARCH_EXTIOI_H */
48
diff --git a/include/hw/intc/loongarch_extioi_common.h b/include/hw/intc/loongarch_extioi_common.h
49
index XXXXXXX..XXXXXXX 100644
50
--- a/include/hw/intc/loongarch_extioi_common.h
51
+++ b/include/hw/intc/loongarch_extioi_common.h
52
@@ -XXX,XX +XXX,XX @@
53
#define EXTIOI_ENABLE_CPU_ENCODE (3)
54
#define EXTIOI_VIRT_COREMAP_START (0x40)
55
#define EXTIOI_VIRT_COREMAP_END (0x240)
56
+
57
+typedef struct ExtIOICore {
58
+ uint32_t coreisr[EXTIOI_IRQS_GROUP_COUNT];
59
+ DECLARE_BITMAP(sw_isr[LS3A_INTC_IP], EXTIOI_IRQS);
60
+ qemu_irq parent_irq[LS3A_INTC_IP];
61
+} ExtIOICore;
62
+
63
+struct LoongArchExtIOI {
64
+ SysBusDevice parent_obj;
65
+ uint32_t num_cpu;
66
+ uint32_t features;
67
+ uint32_t status;
68
+ /* hardware state */
69
+ uint32_t nodetype[EXTIOI_IRQS_NODETYPE_COUNT / 2];
70
+ uint32_t bounce[EXTIOI_IRQS_GROUP_COUNT];
71
+ uint32_t isr[EXTIOI_IRQS / 32];
72
+ uint32_t enable[EXTIOI_IRQS / 32];
73
+ uint32_t ipmap[EXTIOI_IRQS_IPMAP_SIZE / 4];
74
+ uint32_t coremap[EXTIOI_IRQS / 4];
75
+ uint32_t sw_pending[EXTIOI_IRQS / 32];
76
+ uint8_t sw_ipmap[EXTIOI_IRQS_IPMAP_SIZE];
77
+ uint8_t sw_coremap[EXTIOI_IRQS];
78
+ qemu_irq irq[EXTIOI_IRQS];
79
+ ExtIOICore *cpu;
80
+ MemoryRegion extioi_system_mem;
81
+ MemoryRegion virt_extend;
82
+};
83
#endif /* LOONGARCH_EXTIOI_H */
26
--
84
--
27
2.25.1
85
2.43.5
diff view generated by jsdifflib
1
The LoongArch kernel supports 4K page size.
1
Rename structure LoongArchExtIOI with LoongArchExtIOICommonState,
2
Change TARGET_PAGE_BITS to 12.
2
since it is defined in file loongarch_extioi_common.h
3
3
4
Signed-off-by: Song Gao <gaosong@loongson.cn>
4
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
5
Message-Id: <20231023024059.3858349-1-gaosong@loongson.cn>
5
Reviewed-by: Song Gao <gaosong@loongson.cn>
6
---
6
---
7
target/loongarch/cpu-param.h | 2 +-
7
include/hw/intc/loongarch_extioi.h | 1 +
8
target/loongarch/tlb_helper.c | 9 ++++-----
8
include/hw/intc/loongarch_extioi_common.h | 2 +-
9
2 files changed, 5 insertions(+), 6 deletions(-)
9
2 files changed, 2 insertions(+), 1 deletion(-)
10
10
11
diff --git a/target/loongarch/cpu-param.h b/target/loongarch/cpu-param.h
11
diff --git a/include/hw/intc/loongarch_extioi.h b/include/hw/intc/loongarch_extioi.h
12
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/loongarch/cpu-param.h
13
--- a/include/hw/intc/loongarch_extioi.h
14
+++ b/target/loongarch/cpu-param.h
14
+++ b/include/hw/intc/loongarch_extioi.h
15
@@ -XXX,XX +XXX,XX @@
15
@@ -XXX,XX +XXX,XX @@
16
#define TARGET_PHYS_ADDR_SPACE_BITS 48
16
17
#define TARGET_VIRT_ADDR_SPACE_BITS 48
17
#include "hw/intc/loongarch_extioi_common.h"
18
18
19
-#define TARGET_PAGE_BITS 14
19
+#define LoongArchExtIOI LoongArchExtIOICommonState
20
+#define TARGET_PAGE_BITS 12
20
#define TYPE_LOONGARCH_EXTIOI "loongarch.extioi"
21
21
OBJECT_DECLARE_SIMPLE_TYPE(LoongArchExtIOI, LOONGARCH_EXTIOI)
22
#endif
22
#endif /* LOONGARCH_EXTIOI_H */
23
diff --git a/target/loongarch/tlb_helper.c b/target/loongarch/tlb_helper.c
23
diff --git a/include/hw/intc/loongarch_extioi_common.h b/include/hw/intc/loongarch_extioi_common.h
24
index XXXXXXX..XXXXXXX 100644
24
index XXXXXXX..XXXXXXX 100644
25
--- a/target/loongarch/tlb_helper.c
25
--- a/include/hw/intc/loongarch_extioi_common.h
26
+++ b/target/loongarch/tlb_helper.c
26
+++ b/include/hw/intc/loongarch_extioi_common.h
27
@@ -XXX,XX +XXX,XX @@ static int loongarch_map_tlb_entry(CPULoongArchState *env, hwaddr *physical,
27
@@ -XXX,XX +XXX,XX @@ typedef struct ExtIOICore {
28
tlb_rplv = 0;
28
qemu_irq parent_irq[LS3A_INTC_IP];
29
}
29
} ExtIOICore;
30
30
31
+ /* Remove sw bit between bit12 -- bit PS*/
31
-struct LoongArchExtIOI {
32
+ tlb_ppn = tlb_ppn & ~(((0x1UL << (tlb_ps - 12)) -1));
32
+struct LoongArchExtIOICommonState {
33
+
33
SysBusDevice parent_obj;
34
/* Check access rights */
34
uint32_t num_cpu;
35
if (!tlb_v) {
35
uint32_t features;
36
return TLBRET_INVALID;
37
@@ -XXX,XX +XXX,XX @@ static int loongarch_map_tlb_entry(CPULoongArchState *env, hwaddr *physical,
38
return TLBRET_DIRTY;
39
}
40
41
- /*
42
- * tlb_entry contains ppn[47:12] while 16KiB ppn is [47:15]
43
- * need adjust.
44
- */
45
*physical = (tlb_ppn << R_TLBENTRY_64_PPN_SHIFT) |
46
(address & MAKE_64BIT_MASK(0, tlb_ps));
47
*prot = PAGE_READ;
48
@@ -XXX,XX +XXX,XX @@ void helper_ldpte(CPULoongArchState *env, target_ulong base, target_ulong odd,
49
/* Move Global bit */
50
tmp0 = ((tmp0 & (1 << LOONGARCH_HGLOBAL_SHIFT)) >>
51
LOONGARCH_HGLOBAL_SHIFT) << R_TLBENTRY_G_SHIFT |
52
- (tmp0 & (~(1 << R_TLBENTRY_G_SHIFT)));
53
+ (tmp0 & (~(1 << LOONGARCH_HGLOBAL_SHIFT)));
54
ps = ptbase + ptwidth - 1;
55
if (odd) {
56
tmp0 += MAKE_64BIT_MASK(ps, 1);
57
--
36
--
58
2.25.1
37
2.43.5
diff view generated by jsdifflib
1
Signed-off-by: Song Gao <gaosong@loongson.cn>
1
With some structure such as vmstate and property, rename LoongArchExtIOI
2
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2
with LoongArchExtIOICommonState, these common structure will be moved
3
Message-Id: <20231101030816.2353416-6-gaosong@loongson.cn>
3
to common file.
4
5
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
6
Reviewed-by: Song Gao <gaosong@loongson.cn>
4
---
7
---
5
linux-user/loongarch64/signal.c | 107 ++++++++++++++++++++++++++------
8
hw/intc/loongarch_extioi.c | 41 +++++++++++++++++++++++---------------
6
1 file changed, 87 insertions(+), 20 deletions(-)
9
1 file changed, 25 insertions(+), 16 deletions(-)
7
10
8
diff --git a/linux-user/loongarch64/signal.c b/linux-user/loongarch64/signal.c
11
diff --git a/hw/intc/loongarch_extioi.c b/hw/intc/loongarch_extioi.c
9
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
10
--- a/linux-user/loongarch64/signal.c
13
--- a/hw/intc/loongarch_extioi.c
11
+++ b/linux-user/loongarch64/signal.c
14
+++ b/hw/intc/loongarch_extioi.c
12
@@ -XXX,XX +XXX,XX @@ struct target_fpu_context {
15
@@ -XXX,XX +XXX,XX @@ static int vmstate_extioi_post_load(void *opaque, int version_id)
13
QEMU_BUILD_BUG_ON(offsetof(struct target_fpu_context, regs)
16
return 0;
14
!= offsetof_fpucontext_fr);
17
}
15
18
16
+#define LSX_CTX_MAGIC 0x53580001
19
+static int loongarch_extioi_common_post_load(void *opaque, int version_id)
17
+#define LSX_CTX_ALIGN 16
20
+{
18
+struct target_lsx_context {
21
+ return vmstate_extioi_post_load(opaque, version_id);
19
+ abi_ulong regs[2 * 32];
22
+}
20
+ abi_ulong fcc;
21
+ abi_uint fcsr;
22
+} QEMU_ALIGNED(LSX_CTX_ALIGN);
23
+
23
+
24
#define CONTEXT_INFO_ALIGN 16
24
static const VMStateDescription vmstate_extioi_core = {
25
struct target_sctx_info {
25
.name = "extioi-core",
26
abi_uint magic;
26
.version_id = 1,
27
@@ -XXX,XX +XXX,XX @@ struct ctx_layout {
27
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_extioi_core = {
28
};
28
};
29
29
30
struct extctx_layout {
30
static const VMStateDescription vmstate_loongarch_extioi = {
31
- unsigned int size;
31
- .name = TYPE_LOONGARCH_EXTIOI,
32
+ unsigned long size;
32
+ .name = "loongarch.extioi",
33
unsigned int flags;
33
.version_id = 3,
34
struct ctx_layout fpu;
34
.minimum_version_id = 3,
35
+ struct ctx_layout lsx;
35
- .post_load = vmstate_extioi_post_load,
36
struct ctx_layout end;
36
+ .post_load = loongarch_extioi_common_post_load,
37
.fields = (const VMStateField[]) {
38
- VMSTATE_UINT32_ARRAY(bounce, LoongArchExtIOI, EXTIOI_IRQS_GROUP_COUNT),
39
- VMSTATE_UINT32_ARRAY(nodetype, LoongArchExtIOI,
40
+ VMSTATE_UINT32_ARRAY(bounce, LoongArchExtIOICommonState,
41
+ EXTIOI_IRQS_GROUP_COUNT),
42
+ VMSTATE_UINT32_ARRAY(nodetype, LoongArchExtIOICommonState,
43
EXTIOI_IRQS_NODETYPE_COUNT / 2),
44
- VMSTATE_UINT32_ARRAY(enable, LoongArchExtIOI, EXTIOI_IRQS / 32),
45
- VMSTATE_UINT32_ARRAY(isr, LoongArchExtIOI, EXTIOI_IRQS / 32),
46
- VMSTATE_UINT32_ARRAY(ipmap, LoongArchExtIOI, EXTIOI_IRQS_IPMAP_SIZE / 4),
47
- VMSTATE_UINT32_ARRAY(coremap, LoongArchExtIOI, EXTIOI_IRQS / 4),
48
-
49
- VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, LoongArchExtIOI, num_cpu,
50
- vmstate_extioi_core, ExtIOICore),
51
- VMSTATE_UINT32(features, LoongArchExtIOI),
52
- VMSTATE_UINT32(status, LoongArchExtIOI),
53
+ VMSTATE_UINT32_ARRAY(enable, LoongArchExtIOICommonState,
54
+ EXTIOI_IRQS / 32),
55
+ VMSTATE_UINT32_ARRAY(isr, LoongArchExtIOICommonState,
56
+ EXTIOI_IRQS / 32),
57
+ VMSTATE_UINT32_ARRAY(ipmap, LoongArchExtIOICommonState,
58
+ EXTIOI_IRQS_IPMAP_SIZE / 4),
59
+ VMSTATE_UINT32_ARRAY(coremap, LoongArchExtIOICommonState,
60
+ EXTIOI_IRQS / 4),
61
+ VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, LoongArchExtIOICommonState,
62
+ num_cpu, vmstate_extioi_core, ExtIOICore),
63
+ VMSTATE_UINT32(features, LoongArchExtIOICommonState),
64
+ VMSTATE_UINT32(status, LoongArchExtIOICommonState),
65
VMSTATE_END_OF_LIST()
66
}
37
};
67
};
38
68
39
@@ -XXX,XX +XXX,XX @@ static abi_ptr extframe_alloc(struct extctx_layout *extctx,
69
static Property extioi_properties[] = {
40
return sp;
70
- DEFINE_PROP_UINT32("num-cpu", LoongArchExtIOI, num_cpu, 1),
41
}
71
- DEFINE_PROP_BIT("has-virtualization-extension", LoongArchExtIOI, features,
42
72
- EXTIOI_HAS_VIRT_EXTENSION, 0),
43
-static abi_ptr setup_extcontext(struct extctx_layout *extctx, abi_ptr sp)
73
+ DEFINE_PROP_UINT32("num-cpu", LoongArchExtIOICommonState, num_cpu, 1),
44
+static abi_ptr setup_extcontext(CPULoongArchState *env,
74
+ DEFINE_PROP_BIT("has-virtualization-extension", LoongArchExtIOICommonState,
45
+ struct extctx_layout *extctx, abi_ptr sp)
75
+ features, EXTIOI_HAS_VIRT_EXTENSION, 0),
46
{
76
DEFINE_PROP_END_OF_LIST(),
47
memset(extctx, 0, sizeof(struct extctx_layout));
77
};
48
49
@@ -XXX,XX +XXX,XX @@ static abi_ptr setup_extcontext(struct extctx_layout *extctx, abi_ptr sp)
50
51
/* For qemu, there is no lazy fp context switch, so fp always present. */
52
extctx->flags = SC_USED_FP;
53
- sp = extframe_alloc(extctx, &extctx->fpu,
54
+
55
+ if (FIELD_EX64(env->CSR_EUEN, CSR_EUEN, SXE)) {
56
+ sp = extframe_alloc(extctx, &extctx->lsx,
57
+ sizeof(struct target_lsx_context), LSX_CTX_ALIGN, sp);
58
+
59
+ } else {
60
+ sp = extframe_alloc(extctx, &extctx->fpu,
61
sizeof(struct target_fpu_context), FPU_CTX_ALIGN, sp);
62
+ }
63
64
return sp;
65
}
66
@@ -XXX,XX +XXX,XX @@ static void setup_sigframe(CPULoongArchState *env,
67
struct extctx_layout *extctx)
68
{
69
struct target_sctx_info *info;
70
- struct target_fpu_context *fpu_ctx;
71
int i;
72
73
__put_user(extctx->flags, &sc->sc_flags);
74
@@ -XXX,XX +XXX,XX @@ static void setup_sigframe(CPULoongArchState *env,
75
}
76
77
/*
78
- * Set fpu context
79
+ * Set extension context
80
*/
81
- info = extctx->fpu.haddr;
82
- __put_user(FPU_CTX_MAGIC, &info->magic);
83
- __put_user(extctx->fpu.size, &info->size);
84
85
- fpu_ctx = (struct target_fpu_context *)(info + 1);
86
- for (i = 0; i < 32; ++i) {
87
- __put_user(env->fpr[i].vreg.D(0), &fpu_ctx->regs[i]);
88
+ if (FIELD_EX64(env->CSR_EUEN, CSR_EUEN, SXE)) {
89
+ struct target_lsx_context *lsx_ctx;
90
+ info = extctx->lsx.haddr;
91
+
92
+ __put_user(LSX_CTX_MAGIC, &info->magic);
93
+ __put_user(extctx->lsx.size, &info->size);
94
+
95
+ lsx_ctx = (struct target_lsx_context *)(info + 1);
96
+
97
+ for (i = 0; i < 32; ++i) {
98
+ __put_user(env->fpr[i].vreg.UD(0), &lsx_ctx->regs[2 * i]);
99
+ __put_user(env->fpr[i].vreg.UD(1), &lsx_ctx->regs[2 * i + 1]);
100
+ }
101
+ __put_user(read_fcc(env), &lsx_ctx->fcc);
102
+ __put_user(env->fcsr0, &lsx_ctx->fcsr);
103
+ } else {
104
+ struct target_fpu_context *fpu_ctx;
105
+ info = extctx->fpu.haddr;
106
+
107
+ __put_user(FPU_CTX_MAGIC, &info->magic);
108
+ __put_user(extctx->fpu.size, &info->size);
109
+
110
+ fpu_ctx = (struct target_fpu_context *)(info + 1);
111
+
112
+ for (i = 0; i < 32; ++i) {
113
+ __put_user(env->fpr[i].vreg.UD(0), &fpu_ctx->regs[i]);
114
+ }
115
+ __put_user(read_fcc(env), &fpu_ctx->fcc);
116
+ __put_user(env->fcsr0, &fpu_ctx->fcsr);
117
}
118
- __put_user(read_fcc(env), &fpu_ctx->fcc);
119
- __put_user(env->fcsr0, &fpu_ctx->fcsr);
120
121
/*
122
* Set end context
123
@@ -XXX,XX +XXX,XX @@ static bool parse_extcontext(struct extctx_layout *extctx, abi_ptr frame)
124
extctx->fpu.size = size;
125
extctx->size += size;
126
break;
127
+ case LSX_CTX_MAGIC:
128
+ if (size < (sizeof(struct target_sctx_info) +
129
+ sizeof(struct target_lsx_context))) {
130
+ return false;
131
+ }
132
+ extctx->lsx.gaddr = frame;
133
+ extctx->lsx.size = size;
134
+ extctx->size += size;
135
+ break;
136
default:
137
return false;
138
}
139
@@ -XXX,XX +XXX,XX @@ static void restore_sigframe(CPULoongArchState *env,
140
struct extctx_layout *extctx)
141
{
142
int i;
143
+ abi_ulong fcc;
144
145
__get_user(env->pc, &sc->sc_pc);
146
for (i = 1; i < 32; ++i) {
147
__get_user(env->gpr[i], &sc->sc_regs[i]);
148
}
149
150
- if (extctx->fpu.haddr) {
151
+ if (extctx->lsx.haddr) {
152
+ struct target_lsx_context *lsx_ctx =
153
+ extctx->lsx.haddr + sizeof(struct target_sctx_info);
154
+
155
+ for (i = 0; i < 32; ++i) {
156
+ __get_user(env->fpr[i].vreg.UD(0), &lsx_ctx->regs[2 * i]);
157
+ __get_user(env->fpr[i].vreg.UD(1), &lsx_ctx->regs[2 * i + 1]);
158
+ }
159
+ __get_user(fcc, &lsx_ctx->fcc);
160
+ write_fcc(env, fcc);
161
+ __get_user(env->fcsr0, &lsx_ctx->fcsr);
162
+ restore_fp_status(env);
163
+ } else if (extctx->fpu.haddr) {
164
struct target_fpu_context *fpu_ctx =
165
extctx->fpu.haddr + sizeof(struct target_sctx_info);
166
- abi_ulong fcc;
167
168
for (i = 0; i < 32; ++i) {
169
- __get_user(env->fpr[i].vreg.D(0), &fpu_ctx->regs[i]);
170
+ __get_user(env->fpr[i].vreg.UD(0), &fpu_ctx->regs[i]);
171
}
172
__get_user(fcc, &fpu_ctx->fcc);
173
write_fcc(env, fcc);
174
@@ -XXX,XX +XXX,XX @@ static abi_ptr get_sigframe(struct target_sigaction *ka,
175
176
sp = target_sigsp(get_sp_from_cpustate(env), ka);
177
sp = ROUND_DOWN(sp, 16);
178
- sp = setup_extcontext(extctx, sp);
179
+ sp = setup_extcontext(env, extctx, sp);
180
sp -= sizeof(struct target_rt_sigframe);
181
182
assert(QEMU_IS_ALIGNED(sp, 16));
183
@@ -XXX,XX +XXX,XX @@ void setup_rt_frame(int sig, struct target_sigaction *ka,
184
force_sigsegv(sig);
185
return;
186
}
187
- extctx.fpu.haddr = (void *)frame + (extctx.fpu.gaddr - frame_addr);
188
- extctx.end.haddr = (void *)frame + (extctx.end.gaddr - frame_addr);
189
+
190
+ if (FIELD_EX64(env->CSR_EUEN, CSR_EUEN, SXE)) {
191
+ extctx.lsx.haddr = (void *)frame + (extctx.lsx.gaddr - frame_addr);
192
+ extctx.end.haddr = (void *)frame + (extctx.end.gaddr - frame_addr);
193
+ } else {
194
+ extctx.fpu.haddr = (void *)frame + (extctx.fpu.gaddr - frame_addr);
195
+ extctx.end.haddr = (void *)frame + (extctx.end.gaddr - frame_addr);
196
+ }
197
198
tswap_siginfo(&frame->rs_info, info);
199
200
@@ -XXX,XX +XXX,XX @@ long do_rt_sigreturn(CPULoongArchState *env)
201
if (!frame) {
202
goto badframe;
203
}
204
- if (extctx.fpu.gaddr) {
205
+
206
+ if (extctx.lsx.gaddr) {
207
+ extctx.lsx.haddr = (void *)frame + (extctx.lsx.gaddr - frame_addr);
208
+ } else if (extctx.fpu.gaddr) {
209
extctx.fpu.haddr = (void *)frame + (extctx.fpu.gaddr - frame_addr);
210
}
211
78
212
--
79
--
213
2.25.1
80
2.43.5
diff view generated by jsdifflib