Hi,

In this version two new patches were added, both while discussing v6
with Alistair:

- new 'rva22u64' CPU. This is a CPU suggested by Alistair and others to
  allow users to use a profile without having to deal with profile
  enablement. This is done in patch 18;

- 'max' CPU profile restriction. There's no user benefit to have profile
  support in a CPU that has all extensions enabled. This is done in
  patch 19.

Other changes were done based on Drew's feedback on v8:

- patch 3: handle RVH priv_ver bump if it's user enabled, and put some
  comments explaining how it interacts with the 'priv_spec' user option.

- patch 4: rv64i cpu_init() now sets max setp_mode to SV64, and
  we're returning 'MBARE' as default satp_mode for all 'bare' CPUs
  if the user doesn't set a satp_mode in the command line. This will do
  what we want without having to change cpu_riscv_set_satp() and
  satp_finalize(), so patches 3 and 4 from v8 were dropped. Drew saw the
  diff of this patch and decided to keep his ack from v8;

Patches based on riscv-to-apply.next.

Patches missing acks: 3, 18, 19

Changes from v8:
- patches 3 and 4 from v8: dropped
- patch 3 (patch 5 from v8):
  - bump priv_ver when RVH is enabled
  - add a disclaimer when bumping priv_ver about the priv_spec option
    having precedence
- patch 4 (patch 6 from v8):
  - set set_satp_mode_max_supported() to SV64 in rv64i_bare_cpu_init()
  - set PRIV_VERSION_1_10_0 in rv64i_bare_cpu_init()
  - change set_satp_mode_default_map() to set MBARE for 'bare' CPUs
- patch 18 (new):
  - add rva22u64 CPU
- patch 19 (new):
  - forbid profile support for 'max' CPU
- v8 link: https://lore.kernel.org/qemu-riscv/20231101204204.345470-1-dbarboza@ventanamicro.com/

Daniel Henrique Barboza (19):
  target/riscv: create TYPE_RISCV_VENDOR_CPU
  target/riscv/tcg: do not use "!generic" CPU checks
  target/riscv/tcg: update priv_ver on user_set extensions
  target/riscv: add rv64i CPU
  target/riscv: add zicbop extension flag
  target/riscv/tcg: add 'zic64b' support
  riscv-qmp-cmds.c: expose named features in cpu_model_expansion
  target/riscv: add rva22u64 profile definition
  target/riscv/kvm: add 'rva22u64' flag as unavailable
  target/riscv/tcg: add user flag for profile support
  target/riscv/tcg: add MISA user options hash
  target/riscv/tcg: add riscv_cpu_write_misa_bit()
  target/riscv/tcg: handle profile MISA bits
  target/riscv/tcg: add hash table insert helpers
  target/riscv/tcg: honor user choice for G MISA bits
  target/riscv/tcg: validate profiles during finalize
  riscv-qmp-cmds.c: add profile flags in cpu-model-expansion
  target/riscv: add 'rva22u64' CPU
  target/riscv/tcg: do not support profiles for 'max' CPU

 hw/riscv/virt.c               |   5 +
 target/riscv/cpu-qom.h        |   4 +
 target/riscv/cpu.c            | 130 +++++++++++-
 target/riscv/cpu.h            |  13 ++
 target/riscv/cpu_cfg.h        |   3 +
 target/riscv/kvm/kvm-cpu.c    |   7 +-
 target/riscv/riscv-qmp-cmds.c |  44 +++-
 target/riscv/tcg/tcg-cpu.c    | 370 ++++++++++++++++++++++++++++++----
 8 files changed, 518 insertions(+), 58 deletions(-)

-- 
2.41.0