[PATCH v2 0/4] Support RISC-V IOPMP
[PATCH v9 0/8] Support RISC-V IOPMP
1
This series implements IOPMP specification v1.0.0-draft4 rapid-k model.
1
When IOPMP is enabled, memory access to system memory from devices and
2
the CPU will be checked by the IOPMP.
2
3
3
When IOPMP is enabled, a DMA device ATCDMAC300 is added to RISC-V virt
4
The issue of CPU access to non-CPU address space via IOMMU was previously
4
platform. This DMA devce is connected to the IOPMP and has the functionalities
5
mentioned by Jim Shu, who provided a patch[1] to fix it. IOPMP also requires
5
required by IOPMP, including:
6
this patch.
6
- Support specify source-id (SID)
7
- Support asynchronous I/O to handle stall transcations
8
7
9
IOPMP takes a transaction which partially match an entry as a partially hit
8
You can use a customized QEMU[2] to run bare-metal demo[3] to show IOPMP
10
error. The transaction size is depending on source device, destination device
9
functionality. The modifications involve applying patch[1] and adding a simple
11
and bus.
10
DMA device along with a second IOPMP device to the virt machine. These
11
additional devices are intended to demonstrate more complex scenarios for IOPMP.
12
12
13
As v1 disccussion, new iommu translate_size() function is not suitable because
13
[1] accel/tcg: Store section pointer in CPUTLBEntryFull
14
the size may be modified in previos stage.
14
https://patchew.org/QEMU/20240612081416.29704-1-jim.shu@sifive.com/20240612081416.29704-2-jim.shu@sifive.com/
15
[2] https://github.com/zhanyangch/qemu/tree/iopmp_patch_v9_test
16
[3] https://github.com/zhanyangch/iopmp-test
15
17
16
In addtion to SID, start address and end address are also added to MemTxAttrs
18
Ethan Chen (8):
17
in v2. IOPMP matches transaction to an entry with those attributes.
19
hw/core: Add config stream
18
20
memory: Introduce memory region fetch operation
19
21
system/physmem: Support IOMMU granularity smaller than TARGET_PAGE
20
Changes for v2:
22
size
21
23
target/riscv: Add support for IOPMP
22
- Add iopmp_start_addr and iopmp_end_addr to MemTxAttrs.
24
hw/misc/riscv_iopmp_txn_info: Add struct for transaction infomation
23
- Remove translate_size().
25
hw/misc/riscv_iopmp: Add RISC-V IOPMP device
24
- IOPMP: Get transaction info in attrs_to_index instead of using
26
hw/misc/riscv_iopmp_dispatcher: Device for redirect IOPMP transaction
25
translate_size().
27
infomation
26
- IOPMP: Fix some partially hit transactions are not detected.
27
- ATCDMAC300: Fix write stall is not resumed correctly.
28
- ATCDMAC300: Fix some partially hit errors are not detected.
29
30
Ethan Chen (4):
31
exec/memattrs: Add iopmp source id, start address, end address to
32
MemTxAttrs
33
Add RISC-V IOPMP support
34
hw/dma: Add Andes ATCDMAC300 support
35
hw/riscv/virt: Add IOPMP support
28
hw/riscv/virt: Add IOPMP support
36
29
37
hw/dma/Kconfig | 3 +
30
accel/tcg/cputlb.c | 29 +-
38
hw/dma/atcdmac300.c | 460 +++++++++++++++++
31
docs/system/riscv/virt.rst | 7 +
39
hw/dma/meson.build | 1 +
32
hw/Kconfig | 1 +
40
hw/misc/Kconfig | 3 +
33
hw/core/Kconfig | 3 +
41
hw/misc/meson.build | 1 +
34
hw/core/meson.build | 2 +-
42
hw/misc/riscv_iopmp.c | 902 ++++++++++++++++++++++++++++++++++
35
hw/misc/Kconfig | 4 +
43
hw/riscv/Kconfig | 2 +
36
hw/misc/meson.build | 2 +
44
hw/riscv/virt.c | 68 +++
37
hw/misc/riscv_iopmp.c | 2180 ++++++++++++++++++++++
45
include/exec/memattrs.h | 6 +
38
hw/misc/riscv_iopmp_dispatcher.c | 136 ++
46
include/hw/dma/atcdmac300.h | 171 +++++++
39
hw/misc/trace-events | 4 +
47
include/hw/misc/riscv_iopmp.h | 330 +++++++++++++
40
hw/riscv/Kconfig | 1 +
48
include/hw/riscv/virt.h | 10 +-
41
hw/riscv/virt.c | 75 +
49
12 files changed, 1956 insertions(+), 1 deletion(-)
42
include/exec/memory.h | 27 +
50
create mode 100644 hw/dma/atcdmac300.c
43
include/hw/misc/riscv_iopmp.h | 191 ++
44
include/hw/misc/riscv_iopmp_dispatcher.h | 61 +
45
include/hw/misc/riscv_iopmp_txn_info.h | 38 +
46
include/hw/riscv/virt.h | 4 +
47
system/memory.c | 104 ++
48
system/physmem.c | 4 +
49
system/trace-events | 2 +
50
target/riscv/cpu.c | 3 +
51
target/riscv/cpu_cfg.h | 2 +
52
target/riscv/cpu_helper.c | 18 +-
53
23 files changed, 2888 insertions(+), 10 deletions(-)
51
create mode 100644 hw/misc/riscv_iopmp.c
54
create mode 100644 hw/misc/riscv_iopmp.c
52
create mode 100644 include/hw/dma/atcdmac300.h
55
create mode 100644 hw/misc/riscv_iopmp_dispatcher.c
53
create mode 100644 include/hw/misc/riscv_iopmp.h
56
create mode 100644 include/hw/misc/riscv_iopmp.h
57
create mode 100644 include/hw/misc/riscv_iopmp_dispatcher.h
58
create mode 100644 include/hw/misc/riscv_iopmp_txn_info.h
54
59
55
--
60
--
56
2.34.1
61
2.34.1
diff view generated by jsdifflib
New patch
[PATCH v9 1/8] hw/core: Add config stream
1
Make other device can use /hw/core/stream.c by select this config.
1
2
3
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
4
Signed-off-by: Ethan Chen <ethan84@andestech.com>
5
---
6
hw/Kconfig | 1 +
7
hw/core/Kconfig | 3 +++
8
hw/core/meson.build | 2 +-
9
3 files changed, 5 insertions(+), 1 deletion(-)
10
11
diff --git a/hw/Kconfig b/hw/Kconfig
12
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/Kconfig
14
+++ b/hw/Kconfig
15
@@ -XXX,XX +XXX,XX @@ config XILINX
16
config XILINX_AXI
17
bool
18
select PTIMER # for hw/dma/xilinx_axidma.c
19
+ select STREAM
20
21
config XLNX_ZYNQMP
22
bool
23
diff --git a/hw/core/Kconfig b/hw/core/Kconfig
24
index XXXXXXX..XXXXXXX 100644
25
--- a/hw/core/Kconfig
26
+++ b/hw/core/Kconfig
27
@@ -XXX,XX +XXX,XX @@ config SPLIT_IRQ
28
config EIF
29
bool
30
depends on LIBCBOR && GNUTLS
31
+
32
+config STREAM
33
+ bool
34
diff --git a/hw/core/meson.build b/hw/core/meson.build
35
index XXXXXXX..XXXXXXX 100644
36
--- a/hw/core/meson.build
37
+++ b/hw/core/meson.build
38
@@ -XXX,XX +XXX,XX @@ system_ss.add(when: 'CONFIG_PLATFORM_BUS', if_true: files('platform-bus.c'))
39
system_ss.add(when: 'CONFIG_PTIMER', if_true: files('ptimer.c'))
40
system_ss.add(when: 'CONFIG_REGISTER', if_true: files('register.c'))
41
system_ss.add(when: 'CONFIG_SPLIT_IRQ', if_true: files('split-irq.c'))
42
-system_ss.add(when: 'CONFIG_XILINX_AXI', if_true: files('stream.c'))
43
+system_ss.add(when: 'CONFIG_STREAM', if_true: files('stream.c'))
44
system_ss.add(when: 'CONFIG_PLATFORM_BUS', if_true: files('sysbus-fdt.c'))
45
system_ss.add(when: 'CONFIG_EIF', if_true: [files('eif.c'), zlib, libcbor, gnutls])
46
47
--
48
2.34.1
diff view generated by jsdifflib
New patch
[PATCH v9 2/8] memory: Introduce memory region fetch operation
1
1
Allow memory regions to have different behaviors for read and fetch
2
operations.
3
4
For example, the RISC-V IOPMP could raise an interrupt when the CPU
5
tries to fetch from a non-executable region.
6
7
If the fetch operation for a memory region is not implemented, the read
8
operation will still be used for fetch operations.
9
10
Signed-off-by: Ethan Chen <ethan84@andestech.com>
11
---
12
accel/tcg/cputlb.c | 9 +++-
13
include/exec/memory.h | 27 +++++++++++
14
system/memory.c | 104 ++++++++++++++++++++++++++++++++++++++++++
15
system/trace-events | 2 +
16
4 files changed, 140 insertions(+), 2 deletions(-)
17
18
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/accel/tcg/cputlb.c
21
+++ b/accel/tcg/cputlb.c
22
@@ -XXX,XX +XXX,XX @@ static uint64_t int_ld_mmio_beN(CPUState *cpu, CPUTLBEntryFull *full,
23
this_size = 1 << this_mop;
24
this_mop |= MO_BE;
25
26
- r = memory_region_dispatch_read(mr, mr_offset, &val,
27
- this_mop, full->attrs);
28
+ if (type == MMU_INST_FETCH) {
29
+ r = memory_region_dispatch_fetch(mr, mr_offset, &val,
30
+ this_mop, full->attrs);
31
+ } else {
32
+ r = memory_region_dispatch_read(mr, mr_offset, &val,
33
+ this_mop, full->attrs);
34
+ }
35
if (unlikely(r != MEMTX_OK)) {
36
io_failed(cpu, full, addr, this_size, type, mmu_idx, r, ra);
37
}
38
diff --git a/include/exec/memory.h b/include/exec/memory.h
39
index XXXXXXX..XXXXXXX 100644
40
--- a/include/exec/memory.h
41
+++ b/include/exec/memory.h
42
@@ -XXX,XX +XXX,XX @@ struct MemoryRegionOps {
43
hwaddr addr,
44
uint64_t data,
45
unsigned size);
46
+ /* Fetch from the memory region. @addr is relative to @mr; @size is
47
+ * in bytes. */
48
+ uint64_t (*fetch)(void *opaque,
49
+ hwaddr addr,
50
+ unsigned size);
51
52
MemTxResult (*read_with_attrs)(void *opaque,
53
hwaddr addr,
54
@@ -XXX,XX +XXX,XX @@ struct MemoryRegionOps {
55
uint64_t data,
56
unsigned size,
57
MemTxAttrs attrs);
58
+ MemTxResult (*fetch_with_attrs)(void *opaque,
59
+ hwaddr addr,
60
+ uint64_t *data,
61
+ unsigned size,
62
+ MemTxAttrs attrs);
63
64
enum device_endian endianness;
65
/* Guest-visible constraints: */
66
@@ -XXX,XX +XXX,XX @@ MemTxResult memory_region_dispatch_write(MemoryRegion *mr,
67
MemOp op,
68
MemTxAttrs attrs);
69
70
+
71
+/**
72
+ * memory_region_dispatch_fetch: perform a fetch directly to the specified
73
+ * MemoryRegion.
74
+ *
75
+ * @mr: #MemoryRegion to access
76
+ * @addr: address within that region
77
+ * @pval: pointer to uint64_t which the data is written to
78
+ * @op: size, sign, and endianness of the memory operation
79
+ * @attrs: memory transaction attributes to use for the access
80
+ */
81
+MemTxResult memory_region_dispatch_fetch(MemoryRegion *mr,
82
+ hwaddr addr,
83
+ uint64_t *pval,
84
+ MemOp op,
85
+ MemTxAttrs attrs);
86
+
87
/**
88
* address_space_init: initializes an address space
89
*
90
diff --git a/system/memory.c b/system/memory.c
91
index XXXXXXX..XXXXXXX 100644
92
--- a/system/memory.c
93
+++ b/system/memory.c
94
@@ -XXX,XX +XXX,XX @@ static MemTxResult memory_region_read_with_attrs_accessor(MemoryRegion *mr,
95
return r;
96
}
97
98
+static MemTxResult memory_region_fetch_accessor(MemoryRegion *mr,
99
+ hwaddr addr,
100
+ uint64_t *value,
101
+ unsigned size,
102
+ signed shift,
103
+ uint64_t mask,
104
+ MemTxAttrs attrs)
105
+{
106
+ uint64_t tmp;
107
+
108
+ tmp = mr->ops->fetch(mr->opaque, addr, size);
109
+ if (mr->subpage) {
110
+ trace_memory_region_subpage_fetch(get_cpu_index(), mr, addr, tmp, size);
111
+ } else if (trace_event_get_state_backends(TRACE_MEMORY_REGION_OPS_FETCH)) {
112
+ hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
113
+ trace_memory_region_ops_fetch(get_cpu_index(), mr, abs_addr, tmp, size,
114
+ memory_region_name(mr));
115
+ }
116
+ memory_region_shift_read_access(value, shift, mask, tmp);
117
+ return MEMTX_OK;
118
+}
119
+
120
+static MemTxResult memory_region_fetch_with_attrs_accessor(MemoryRegion *mr,
121
+ hwaddr addr,
122
+ uint64_t *value,
123
+ unsigned size,
124
+ signed shift,
125
+ uint64_t mask,
126
+ MemTxAttrs attrs)
127
+{
128
+ uint64_t tmp = 0;
129
+ MemTxResult r;
130
+
131
+ r = mr->ops->fetch_with_attrs(mr->opaque, addr, &tmp, size, attrs);
132
+ if (mr->subpage) {
133
+ trace_memory_region_subpage_fetch(get_cpu_index(), mr, addr, tmp, size);
134
+ } else if (trace_event_get_state_backends(TRACE_MEMORY_REGION_OPS_FETCH)) {
135
+ hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
136
+ trace_memory_region_ops_fetch(get_cpu_index(), mr, abs_addr, tmp, size,
137
+ memory_region_name(mr));
138
+ }
139
+ memory_region_shift_read_access(value, shift, mask, tmp);
140
+ return r;
141
+}
142
+
143
static MemTxResult memory_region_write_accessor(MemoryRegion *mr,
144
hwaddr addr,
145
uint64_t *value,
146
@@ -XXX,XX +XXX,XX @@ MemTxResult memory_region_dispatch_read(MemoryRegion *mr,
147
return r;
148
}
149
150
+static MemTxResult memory_region_dispatch_fetch1(MemoryRegion *mr,
151
+ hwaddr addr,
152
+ uint64_t *pval,
153
+ unsigned size,
154
+ MemTxAttrs attrs)
155
+{
156
+ *pval = 0;
157
+
158
+ if (mr->ops->fetch) {
159
+ return access_with_adjusted_size(addr, pval, size,
160
+ mr->ops->impl.min_access_size,
161
+ mr->ops->impl.max_access_size,
162
+ memory_region_fetch_accessor,
163
+ mr, attrs);
164
+ } else if (mr->ops->fetch_with_attrs) {
165
+ return access_with_adjusted_size(addr, pval, size,
166
+ mr->ops->impl.min_access_size,
167
+ mr->ops->impl.max_access_size,
168
+ memory_region_fetch_with_attrs_accessor,
169
+ mr, attrs);
170
+ } else if (mr->ops->read) {
171
+ return access_with_adjusted_size(addr, pval, size,
172
+ mr->ops->impl.min_access_size,
173
+ mr->ops->impl.max_access_size,
174
+ memory_region_read_accessor,
175
+ mr, attrs);
176
+ } else {
177
+ return access_with_adjusted_size(addr, pval, size,
178
+ mr->ops->impl.min_access_size,
179
+ mr->ops->impl.max_access_size,
180
+ memory_region_read_with_attrs_accessor,
181
+ mr, attrs);
182
+ }
183
+}
184
+
185
+MemTxResult memory_region_dispatch_fetch(MemoryRegion *mr,
186
+ hwaddr addr,
187
+ uint64_t *pval,
188
+ MemOp op,
189
+ MemTxAttrs attrs)
190
+{
191
+ unsigned size = memop_size(op);
192
+ MemTxResult r;
193
+
194
+ if (mr->alias) {
195
+ return memory_region_dispatch_fetch(mr->alias,
196
+ mr->alias_offset + addr,
197
+ pval, op, attrs);
198
+ }
199
+ if (!memory_region_access_valid(mr, addr, size, false, attrs)) {
200
+ *pval = unassigned_mem_read(mr, addr, size);
201
+ return MEMTX_DECODE_ERROR;
202
+ }
203
+
204
+ r = memory_region_dispatch_fetch1(mr, addr, pval, size, attrs);
205
+ adjust_endianness(mr, pval, op);
206
+ return r;
207
+}
208
+
209
/* Return true if an eventfd was signalled */
210
static bool memory_region_dispatch_write_eventfds(MemoryRegion *mr,
211
hwaddr addr,
212
diff --git a/system/trace-events b/system/trace-events
213
index XXXXXXX..XXXXXXX 100644
214
--- a/system/trace-events
215
+++ b/system/trace-events
216
@@ -XXX,XX +XXX,XX @@ cpu_out(unsigned int addr, char size, unsigned int val) "addr 0x%x(%c) value %u"
217
# memory.c
218
memory_region_ops_read(int cpu_index, void *mr, uint64_t addr, uint64_t value, unsigned size, const char *name) "cpu %d mr %p addr 0x%"PRIx64" value 0x%"PRIx64" size %u name '%s'"
219
memory_region_ops_write(int cpu_index, void *mr, uint64_t addr, uint64_t value, unsigned size, const char *name) "cpu %d mr %p addr 0x%"PRIx64" value 0x%"PRIx64" size %u name '%s'"
220
+memory_region_ops_fetch(int cpu_index, void *mr, uint64_t addr, uint64_t value, unsigned size, const char *name) "cpu %d mr %p addr 0x%"PRIx64" value 0x%"PRIx64" size %u name '%s'"
221
memory_region_subpage_read(int cpu_index, void *mr, uint64_t offset, uint64_t value, unsigned size) "cpu %d mr %p offset 0x%"PRIx64" value 0x%"PRIx64" size %u"
222
memory_region_subpage_write(int cpu_index, void *mr, uint64_t offset, uint64_t value, unsigned size) "cpu %d mr %p offset 0x%"PRIx64" value 0x%"PRIx64" size %u"
223
+memory_region_subpage_fetch(int cpu_index, void *mr, uint64_t offset, uint64_t value, unsigned size) "cpu %d mr %p offset 0x%"PRIx64" value 0x%"PRIx64" size %u"
224
memory_region_ram_device_read(int cpu_index, void *mr, uint64_t addr, uint64_t value, unsigned size) "cpu %d mr %p addr 0x%"PRIx64" value 0x%"PRIx64" size %u"
225
memory_region_ram_device_write(int cpu_index, void *mr, uint64_t addr, uint64_t value, unsigned size) "cpu %d mr %p addr 0x%"PRIx64" value 0x%"PRIx64" size %u"
226
memory_region_sync_dirty(const char *mr, const char *listener, int global) "mr '%s' listener '%s' synced (global=%d)"
227
--
228
2.34.1
diff view generated by jsdifflib
New patch
[PATCH v9 3/8] system/physmem: Support IOMMU granularity smaller than TARGET_PAGE size
1
If the IOMMU granularity is smaller than the TARGET_PAGE size, there may be
2
multiple entries within the same page. To obtain the correct result, pass
3
the original address to the IOMMU.
1
4
5
Similar to the RISC-V PMP solution, the TLB_INVALID_MASK will be set when
6
there are multiple entries in the same page, ensuring that the IOMMU is
7
checked on every access.
8
9
Signed-off-by: Ethan Chen <ethan84@andestech.com>
10
Acked-by: Alistair Francis <alistair.francis@wdc.com>
11
---
12
accel/tcg/cputlb.c | 20 ++++++++++++++++----
13
system/physmem.c | 4 ++++
14
2 files changed, 20 insertions(+), 4 deletions(-)
15
16
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/accel/tcg/cputlb.c
19
+++ b/accel/tcg/cputlb.c
20
@@ -XXX,XX +XXX,XX @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx,
21
22
prot = full->prot;
23
asidx = cpu_asidx_from_attrs(cpu, full->attrs);
24
- section = address_space_translate_for_iotlb(cpu, asidx, paddr_page,
25
+ section = address_space_translate_for_iotlb(cpu, asidx, full->phys_addr,
26
&xlat, &sz, full->attrs, &prot);
27
+ /* Update page size */
28
+ full->lg_page_size = ctz64(sz);
29
+ if (full->lg_page_size > TARGET_PAGE_BITS) {
30
+ full->lg_page_size = TARGET_PAGE_BITS;
31
+ } else {
32
+ sz = TARGET_PAGE_SIZE;
33
+ }
34
+
35
+ is_ram = memory_region_is_ram(section->mr);
36
+ is_romd = memory_region_is_romd(section->mr);
37
+ /* If the translated mr is ram/rom, make xlat align the TARGET_PAGE */
38
+ if (is_ram || is_romd) {
39
+ xlat &= TARGET_PAGE_MASK;
40
+ }
41
+
42
assert(sz >= TARGET_PAGE_SIZE);
43
44
tlb_debug("vaddr=%016" VADDR_PRIx " paddr=0x" HWADDR_FMT_plx
45
@@ -XXX,XX +XXX,XX @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx,
46
read_flags |= TLB_INVALID_MASK;
47
}
48
49
- is_ram = memory_region_is_ram(section->mr);
50
- is_romd = memory_region_is_romd(section->mr);
51
-
52
if (is_ram || is_romd) {
53
/* RAM and ROMD both have associated host memory. */
54
addend = (uintptr_t)memory_region_get_ram_ptr(section->mr) + xlat;
55
diff --git a/system/physmem.c b/system/physmem.c
56
index XXXXXXX..XXXXXXX 100644
57
--- a/system/physmem.c
58
+++ b/system/physmem.c
59
@@ -XXX,XX +XXX,XX @@ address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr orig_addr,
60
iotlb = imrc->translate(iommu_mr, addr, IOMMU_NONE, iommu_idx);
61
addr = ((iotlb.translated_addr & ~iotlb.addr_mask)
62
| (addr & iotlb.addr_mask));
63
+ /* Update size */
64
+ if (iotlb.addr_mask != -1 && *plen > iotlb.addr_mask + 1) {
65
+ *plen = iotlb.addr_mask + 1;
66
+ }
67
/* Update the caller's prot bits to remove permissions the IOMMU
68
* is giving us a failure response for. If we get down to no
69
* permissions left at all we can give up now.
70
--
71
2.34.1
diff view generated by jsdifflib
New patch
[PATCH v9 4/8] target/riscv: Add support for IOPMP
1
Signed-off-by: Ethan Chen <ethan84@andestech.com>
2
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
3
---
4
target/riscv/cpu.c | 3 +++
5
target/riscv/cpu_cfg.h | 2 ++
6
target/riscv/cpu_helper.c | 18 +++++++++++++++---
7
3 files changed, 20 insertions(+), 3 deletions(-)
1
8
9
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
10
index XXXXXXX..XXXXXXX 100644
11
--- a/target/riscv/cpu.c
12
+++ b/target/riscv/cpu.c
13
@@ -XXX,XX +XXX,XX @@ static const Property riscv_cpu_properties[] = {
14
* it with -x and default to 'false'.
15
*/
16
DEFINE_PROP_BOOL("x-misa-w", RISCVCPU, cfg.misa_w, false),
17
+
18
+ DEFINE_PROP_BOOL("iopmp", RISCVCPU, cfg.iopmp, false),
19
+ DEFINE_PROP_UINT32("iopmp_rrid", RISCVCPU, cfg.iopmp_rrid, 0),
20
};
21
22
#if defined(TARGET_RISCV64)
23
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
24
index XXXXXXX..XXXXXXX 100644
25
--- a/target/riscv/cpu_cfg.h
26
+++ b/target/riscv/cpu_cfg.h
27
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
28
bool pmp;
29
bool debug;
30
bool misa_w;
31
+ bool iopmp;
32
+ uint32_t iopmp_rrid;
33
34
bool short_isa_string;
35
36
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
37
index XXXXXXX..XXXXXXX 100644
38
--- a/target/riscv/cpu_helper.c
39
+++ b/target/riscv/cpu_helper.c
40
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
41
}
42
43
if (ret == TRANSLATE_SUCCESS) {
44
- tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1),
45
- prot, mmu_idx, tlb_size);
46
- return true;
47
+ if (cpu->cfg.iopmp) {
48
+ /*
49
+ * Do not align address on early stage because IOPMP needs origin
50
+ * address for permission check.
51
+ */
52
+ tlb_set_page_with_attrs(cs, address, pa,
53
+ (MemTxAttrs)
54
+ {
55
+ .requester_id = cpu->cfg.iopmp_rrid,
56
+ },
57
+ prot, mmu_idx, tlb_size);
58
+ } else {
59
+ tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1),
60
+ prot, mmu_idx, tlb_size);
61
+ }
62
} else if (probe) {
63
return false;
64
} else {
65
--
66
2.34.1
diff view generated by jsdifflib
New patch
[PATCH v9 5/8] hw/misc/riscv_iopmp_txn_info: Add struct for transaction infomation
1
The entire valid transaction must fit within a single IOPMP entry.
2
However, during IOMMU translation, the transaction size is not
3
available. This structure defines the transaction information required
4
by the IOPMP.
1
5
6
Signed-off-by: Ethan Chen <ethan84@andestech.com>
7
---
8
include/hw/misc/riscv_iopmp_txn_info.h | 38 ++++++++++++++++++++++++++
9
1 file changed, 38 insertions(+)
10
create mode 100644 include/hw/misc/riscv_iopmp_txn_info.h
11
12
diff --git a/include/hw/misc/riscv_iopmp_txn_info.h b/include/hw/misc/riscv_iopmp_txn_info.h
13
new file mode 100644
14
index XXXXXXX..XXXXXXX
15
--- /dev/null
16
+++ b/include/hw/misc/riscv_iopmp_txn_info.h
17
@@ -XXX,XX +XXX,XX @@
18
+/*
19
+ * QEMU RISC-V IOPMP transaction information
20
+ *
21
+ * The transaction information structure provides the complete transaction
22
+ * length to the IOPMP device
23
+ *
24
+ * Copyright (c) 2023-2025 Andes Tech. Corp.
25
+ *
26
+ * SPDX-License-Identifier: GPL-2.0-or-later
27
+ *
28
+ * This program is free software; you can redistribute it and/or modify it
29
+ * under the terms and conditions of the GNU General Public License,
30
+ * version 2 or later, as published by the Free Software Foundation.
31
+ *
32
+ * This program is distributed in the hope it will be useful, but WITHOUT
33
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
34
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
35
+ * more details.
36
+ *
37
+ * You should have received a copy of the GNU General Public License along with
38
+ * this program. If not, see <http://www.gnu.org/licenses/>.
39
+ */
40
+
41
+#ifndef RISCV_IOPMP_TXN_INFO_H
42
+#define RISCV_IOPMP_TXN_INFO_H
43
+
44
+typedef struct {
45
+ /* The id of requestor */
46
+ uint32_t rrid:16;
47
+ /* The start address of transaction */
48
+ uint64_t start_addr;
49
+ /* The end address of transaction */
50
+ uint64_t end_addr;
51
+ /* The stage of cascading IOPMP */
52
+ uint32_t stage;
53
+} riscv_iopmp_txn_info;
54
+
55
+#endif
56
--
57
2.34.1
diff view generated by jsdifflib
New patch
[PATCH v9 6/8] hw/misc/riscv_iopmp: Add RISC-V IOPMP device
1
Support IOPMP specification v0.9.2RC3.
2
The specification url:
3
https://github.com/riscv-non-isa/iopmp-spec/releases/tag/v0.9.2-RC3
1
4
5
The IOPMP checks whether memory access from a device or CPU is valid.
6
This implementation uses an IOMMU to modify the address space accessed
7
by the device.
8
9
For device access with IOMMUAccessFlags specifying read or write
10
(IOMMU_RO or IOMMU_WO), the IOPMP checks the permission in
11
iopmp_translate. If the access is valid, the target address space is
12
downstream_as. If the access is blocked, it will be redirected to
13
blocked_rwx_as.
14
15
For CPU access with IOMMUAccessFlags not specifying read or write
16
(IOMMU_NONE), the IOPMP translates the access to the corresponding
17
address space based on the permission. If the access has full permission
18
(rwx), the target address space is downstream_as. If the access has
19
limited permission, the target address space is blocked_ followed by
20
the lacked permissions.
21
22
The operation of a blocked region can trigger an IOPMP interrupt, a bus
23
error, or it can respond with success and fabricated data, depending on
24
the value of the IOPMP ERR_CFG register.
25
26
Support Properties and Default Values of the IOPMP Device
27
The following are the supported properties and their default values for the
28
IOPMP device. If a property has no description here, please refer to the
29
IOPMP specification for details:
30
31
* mdcfg_fmt: 1 (Options: 0/1/2)
32
* srcmd_fmt: 0 (Options: 0/1/2)
33
* tor_en: true (Options: true/false)
34
* sps_en: false (Options: true/false)
35
* prient_prog: true (Options: true/false)
36
* rrid_transl_en: false (Options: true/false)
37
* rrid_transl_prog: false (Options: true/false)
38
* chk_x: true (Options: true/false)
39
* no_x: false (Options: true/false)
40
* no_w: false (Options: true/false)
41
* stall_en: false (Options: true/false)
42
* peis: true (Options: true/false)
43
* pees: true (Options: true/false)
44
* mfr_en: true (Options: true/false)
45
* md_entry_num: 5 (IMP: Valid only for mdcfg_fmt 1/2)
46
* md_num: 8 (Range: 0-63)
47
* rrid_num: 16 (Range: srcmd_fmt ≠ 2: 0-65535, srcmd_fmt = 2: 0-32)
48
* entry_num: 48
49
(Range: 0-IMP. For mdcfg_fmt = 1, it is fixed as md_num * (md_entry_num + 1).
50
Entry registers must not overlap with other registers.)
51
* prio_entry: 65535
52
(Range: 0-IMP. If prio_entry > entry_num, it will be set to entry_num.)
53
* rrid_transl: 0x0 (Range: 0-65535)
54
* entry_offset: 0x4000
55
(IMP: Entry registers must not overlap with other registers.)
56
* err_rdata: 0x0
57
(uint32. Specifies the value used in responses to read transactions when
58
errors are suppressed)
59
* msi_en: false (Options: true/false)
60
* msidata: 12 (Range: 1-1023)
61
* stall_violation_en: true (Options: true/false)
62
* err_msiaddr: 0x24000000 (low-part 32-bit address)
63
* err_msiaddrh: 0x0 (high-part 32-bit address)
64
* msi_rrid: 0
65
(Range: 0-65535. Specifies the rrid used by the IOPMP to send the MSI.)
66
67
Signed-off-by: Ethan Chen <ethan84@andestech.com>
68
---
69
hw/misc/Kconfig | 4 +
70
hw/misc/meson.build | 1 +
71
hw/misc/riscv_iopmp.c | 2180 +++++++++++++++++++++++++++++++++
72
hw/misc/trace-events | 4 +
73
include/hw/misc/riscv_iopmp.h | 191 +++
74
5 files changed, 2380 insertions(+)
75
create mode 100644 hw/misc/riscv_iopmp.c
76
create mode 100644 include/hw/misc/riscv_iopmp.h
77
78
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
79
index XXXXXXX..XXXXXXX 100644
80
--- a/hw/misc/Kconfig
81
+++ b/hw/misc/Kconfig
82
@@ -XXX,XX +XXX,XX @@ config IOSB
83
config XLNX_VERSAL_TRNG
84
bool
85
86
+config RISCV_IOPMP
87
+ bool
88
+ select STREAM
89
+
90
source macio/Kconfig
91
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
92
index XXXXXXX..XXXXXXX 100644
93
--- a/hw/misc/meson.build
94
+++ b/hw/misc/meson.build
95
@@ -XXX,XX +XXX,XX @@ system_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c'))
96
system_ss.add(when: 'CONFIG_SIFIVE_E_AON', if_true: files('sifive_e_aon.c'))
97
system_ss.add(when: 'CONFIG_SIFIVE_U_OTP', if_true: files('sifive_u_otp.c'))
98
system_ss.add(when: 'CONFIG_SIFIVE_U_PRCI', if_true: files('sifive_u_prci.c'))
99
+specific_ss.add(when: 'CONFIG_RISCV_IOPMP', if_true: files('riscv_iopmp.c'))
100
101
subdir('macio')
102
103
diff --git a/hw/misc/riscv_iopmp.c b/hw/misc/riscv_iopmp.c
104
new file mode 100644
105
index XXXXXXX..XXXXXXX
106
--- /dev/null
107
+++ b/hw/misc/riscv_iopmp.c
108
@@ -XXX,XX +XXX,XX @@
109
+/*
110
+ * QEMU RISC-V IOPMP (Input Output Physical Memory Protection)
111
+ *
112
+ * Copyright (c) 2023-2025 Andes Tech. Corp.
113
+ *
114
+ * SPDX-License-Identifier: GPL-2.0-or-later
115
+ *
116
+ * This program is free software; you can redistribute it and/or modify it
117
+ * under the terms and conditions of the GNU General Public License,
118
+ * version 2 or later, as published by the Free Software Foundation.
119
+ *
120
+ * This program is distributed in the hope it will be useful, but WITHOUT
121
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
122
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
123
+ * more details.
124
+ *
125
+ * You should have received a copy of the GNU General Public License along with
126
+ * this program. If not, see <http://www.gnu.org/licenses/>.
127
+ */
128
+
129
+#include "qemu/osdep.h"
130
+#include "qemu/log.h"
131
+#include "qapi/error.h"
132
+#include "trace.h"
133
+#include "exec/exec-all.h"
134
+#include "exec/address-spaces.h"
135
+#include "hw/qdev-properties.h"
136
+#include "hw/sysbus.h"
137
+#include "hw/misc/riscv_iopmp.h"
138
+#include "memory.h"
139
+#include "hw/irq.h"
140
+#include "hw/registerfields.h"
141
+#include "trace.h"
142
+#include "qemu/main-loop.h"
143
+#include "hw/stream.h"
144
+#include "hw/misc/riscv_iopmp_txn_info.h"
145
+
146
+#define TYPE_RISCV_IOPMP_IOMMU_MEMORY_REGION "riscv-iopmp-iommu-memory-region"
147
+
148
+REG32(VERSION, 0x00)
149
+ FIELD(VERSION, VENDOR, 0, 24)
150
+ FIELD(VERSION, SPECVER , 24, 8)
151
+REG32(IMPLEMENTATION, 0x04)
152
+ FIELD(IMPLEMENTATION, IMPID, 0, 32)
153
+REG32(HWCFG0, 0x08)
154
+ FIELD(HWCFG0, MDCFG_FMT, 0, 2)
155
+ FIELD(HWCFG0, SRCMD_FMT, 2, 2)
156
+ FIELD(HWCFG0, TOR_EN, 4, 1)
157
+ FIELD(HWCFG0, SPS_EN, 5, 1)
158
+ FIELD(HWCFG0, USER_CFG_EN, 6, 1)
159
+ FIELD(HWCFG0, PRIENT_PROG, 7, 1)
160
+ FIELD(HWCFG0, RRID_TRANSL_EN, 8, 1)
161
+ FIELD(HWCFG0, RRID_TRANSL_PROG, 9, 1)
162
+ FIELD(HWCFG0, CHK_X, 10, 1)
163
+ FIELD(HWCFG0, NO_X, 11, 1)
164
+ FIELD(HWCFG0, NO_W, 12, 1)
165
+ FIELD(HWCFG0, STALL_EN, 13, 1)
166
+ FIELD(HWCFG0, PEIS, 14, 1)
167
+ FIELD(HWCFG0, PEES, 15, 1)
168
+ FIELD(HWCFG0, MFR_EN, 16, 1)
169
+ FIELD(HWCFG0, MD_ENTRY_NUM, 17, 7)
170
+ FIELD(HWCFG0, MD_NUM, 24, 6)
171
+ FIELD(HWCFG0, ADDRH_EN, 30, 1)
172
+ FIELD(HWCFG0, ENABLE, 31, 1)
173
+REG32(HWCFG1, 0x0C)
174
+ FIELD(HWCFG1, RRID_NUM, 0, 16)
175
+ FIELD(HWCFG1, ENTRY_NUM, 16, 16)
176
+REG32(HWCFG2, 0x10)
177
+ FIELD(HWCFG2, PRIO_ENTRY, 0, 16)
178
+ FIELD(HWCFG2, RRID_TRANSL, 16, 16)
179
+REG32(ENTRYOFFSET, 0x14)
180
+ FIELD(ENTRYOFFSET, OFFSET, 0, 32)
181
+REG32(MDSTALL, 0x30)
182
+ FIELD(MDSTALL, EXEMPT, 0, 1)
183
+ FIELD(MDSTALL, MD, 1, 31)
184
+REG32(MDSTALLH, 0x34)
185
+ FIELD(MDSTALLH, MD, 0, 32)
186
+REG32(RRIDSCP, 0x38)
187
+ FIELD(RRIDSCP, RRID, 0, 16)
188
+ FIELD(RRIDSCP, OP, 30, 2)
189
+ FIELD(RRIDSCP, STAT, 30, 2)
190
+REG32(MDLCK, 0x40)
191
+ FIELD(MDLCK, L, 0, 1)
192
+ FIELD(MDLCK, MD, 1, 31)
193
+REG32(MDLCKH, 0x44)
194
+ FIELD(MDLCKH, MDH, 0, 32)
195
+REG32(MDCFGLCK, 0x48)
196
+ FIELD(MDCFGLCK, L, 0, 1)
197
+ FIELD(MDCFGLCK, F, 1, 7)
198
+REG32(ENTRYLCK, 0x4C)
199
+ FIELD(ENTRYLCK, L, 0, 1)
200
+ FIELD(ENTRYLCK, F, 1, 16)
201
+REG32(ERR_CFG, 0x60)
202
+ FIELD(ERR_CFG, L, 0, 1)
203
+ FIELD(ERR_CFG, IE, 1, 1)
204
+ FIELD(ERR_CFG, RS, 2, 1)
205
+ FIELD(ERR_CFG, MSI_EN, 3, 1)
206
+ FIELD(ERR_CFG, STALL_VIOLATION_EN, 4, 1)
207
+ FIELD(ERR_CFG, MSIDATA, 8, 11)
208
+REG32(ERR_INFO, 0x64)
209
+ FIELD(ERR_INFO, V, 0, 1)
210
+ FIELD(ERR_INFO, TTYPE, 1, 2)
211
+ FIELD(ERR_INFO, MSI_WERR, 3, 1)
212
+ FIELD(ERR_INFO, ETYPE, 4, 4)
213
+ FIELD(ERR_INFO, SVC, 8, 1)
214
+REG32(ERR_REQADDR, 0x68)
215
+ FIELD(ERR_REQADDR, ADDR, 0, 32)
216
+REG32(ERR_REQADDRH, 0x6C)
217
+ FIELD(ERR_REQADDRH, ADDRH, 0, 32)
218
+REG32(ERR_REQID, 0x70)
219
+ FIELD(ERR_REQID, RRID, 0, 16)
220
+ FIELD(ERR_REQID, EID, 16, 16)
221
+REG32(ERR_MFR, 0x74)
222
+ FIELD(ERR_MFR, SVW, 0, 16)
223
+ FIELD(ERR_MFR, SVI, 16, 12)
224
+ FIELD(ERR_MFR, SVS, 31, 1)
225
+REG32(ERR_MSIADDR, 0x78)
226
+REG32(ERR_MSIADDRH, 0x7C)
227
+REG32(MDCFG0, 0x800)
228
+ FIELD(MDCFG0, T, 0, 16)
229
+REG32(SRCMD_EN0, 0x1000)
230
+ FIELD(SRCMD_EN0, L, 0, 1)
231
+ FIELD(SRCMD_EN0, MD, 1, 31)
232
+REG32(SRCMD_ENH0, 0x1004)
233
+ FIELD(SRCMD_ENH0, MDH, 0, 32)
234
+REG32(SRCMD_R0, 0x1008)
235
+ FIELD(SRCMD_R0, MD, 1, 31)
236
+REG32(SRCMD_RH0, 0x100C)
237
+ FIELD(SRCMD_RH0, MDH, 0, 32)
238
+REG32(SRCMD_W0, 0x1010)
239
+ FIELD(SRCMD_W0, MD, 1, 31)
240
+REG32(SRCMD_WH0, 0x1014)
241
+ FIELD(SRCMD_WH0, MDH, 0, 32)
242
+REG32(SRCMD_PERM0, 0x1000)
243
+REG32(SRCMD_PERMH0, 0x1004)
244
+
245
+FIELD(ENTRY_ADDR, ADDR, 0, 32)
246
+FIELD(ENTRY_ADDRH, ADDRH, 0, 32)
247
+
248
+FIELD(ENTRY_CFG, R, 0, 1)
249
+FIELD(ENTRY_CFG, W, 1, 1)
250
+FIELD(ENTRY_CFG, X, 2, 1)
251
+FIELD(ENTRY_CFG, A, 3, 2)
252
+FIELD(ENTRY_CFG, SIE, 5, 3)
253
+FIELD(ENTRY_CFG, SIRE, 5, 1)
254
+FIELD(ENTRY_CFG, SIWE, 6, 1)
255
+FIELD(ENTRY_CFG, SIXE, 7, 1)
256
+FIELD(ENTRY_CFG, SEE, 8, 3)
257
+FIELD(ENTRY_CFG, SERE, 8, 1)
258
+FIELD(ENTRY_CFG, SEWE, 9, 1)
259
+FIELD(ENTRY_CFG, SEXE, 10, 1)
260
+
261
+FIELD(ENTRY_USER_CFG, IM, 0, 32)
262
+
263
+/* Offsets to SRCMD_EN(i) */
264
+#define SRCMD_EN_OFFSET 0x0
265
+#define SRCMD_ENH_OFFSET 0x4
266
+#define SRCMD_R_OFFSET 0x8
267
+#define SRCMD_RH_OFFSET 0xC
268
+#define SRCMD_W_OFFSET 0x10
269
+#define SRCMD_WH_OFFSET 0x14
270
+
271
+/* Offsets to SRCMD_PERM(i) */
272
+#define SRCMD_PERM_OFFSET 0x0
273
+#define SRCMD_PERMH_OFFSET 0x4
274
+
275
+/* Offsets to ENTRY_ADDR(i) */
276
+#define ENTRY_ADDR_OFFSET 0x0
277
+#define ENTRY_ADDRH_OFFSET 0x4
278
+#define ENTRY_CFG_OFFSET 0x8
279
+#define ENTRY_USER_CFG_OFFSET 0xC
280
+
281
+#define IOPMP_MAX_MD_NUM 63
282
+#define IOPMP_MAX_RRID_NUM 32
283
+#define IOPMP_SRCMDFMT0_MAX_RRID_NUM 65535
284
+#define IOPMP_SRCMDFMT2_MAX_RRID_NUM 32
285
+#define IOPMP_MAX_ENTRY_NUM 65535
286
+
287
+/* The ids of iopmp are temporary */
288
+#define VENDER_VIRT 0
289
+#define SPECVER_0_9_2 92
290
+#define IMPID_0_9_2 92
291
+
292
+typedef enum {
293
+ RS_ERROR,
294
+ RS_SUCCESS,
295
+} iopmp_reaction;
296
+
297
+typedef enum {
298
+ RWE_ERROR,
299
+ RWE_SUCCESS,
300
+} iopmp_write_reaction;
301
+
302
+typedef enum {
303
+ RXE_ERROR,
304
+ RXE_SUCCESS_VALUE,
305
+} iopmp_exec_reaction;
306
+
307
+typedef enum {
308
+ ERR_INFO_TTYPE_NOERROR,
309
+ ERR_INFO_TTYPE_READ,
310
+ ERR_INFO_TTYPE_WRITE,
311
+ ERR_INFO_TTYPE_FETCH
312
+} iopmp_err_info_ttype;
313
+
314
+typedef enum {
315
+ ERR_INFO_ETYPE_NOERROR,
316
+ ERR_INFO_ETYPE_READ,
317
+ ERR_INFO_ETYPE_WRITE,
318
+ ERR_INFO_ETYPE_FETCH,
319
+ ERR_INFO_ETYPE_PARHIT,
320
+ ERR_INFO_ETYPE_NOHIT,
321
+ ERR_INFO_ETYPE_RRID,
322
+ ERR_INFO_ETYPE_USER,
323
+ ERR_INFO_ETYPE_STALL
324
+} iopmp_err_info_etype;
325
+
326
+typedef enum {
327
+ IOPMP_ENTRY_NO_HIT,
328
+ IOPMP_ENTRY_PAR_HIT,
329
+ IOPMP_ENTRY_HIT
330
+} iopmp_entry_hit;
331
+
332
+typedef enum {
333
+ IOPMP_AMATCH_OFF, /* Null (off) */
334
+ IOPMP_AMATCH_TOR, /* Top of Range */
335
+ IOPMP_AMATCH_NA4, /* Naturally aligned four-byte region */
336
+ IOPMP_AMATCH_NAPOT /* Naturally aligned power-of-two region */
337
+} iopmp_am_t;
338
+
339
+typedef enum {
340
+ IOPMP_ACCESS_READ = 1,
341
+ IOPMP_ACCESS_WRITE = 2,
342
+ IOPMP_ACCESS_FETCH = 3
343
+} iopmp_access_type;
344
+
345
+typedef enum {
346
+ IOPMP_NONE = 0,
347
+ IOPMP_RO = 1,
348
+ IOPMP_WO = 2,
349
+ IOPMP_RW = 3,
350
+ IOPMP_XO = 4,
351
+ IOPMP_RX = 5,
352
+ IOPMP_WX = 6,
353
+ IOPMP_RWX = 7,
354
+} iopmp_permission;
355
+
356
+typedef enum {
357
+ RRIDSCP_OP_QUERY = 0,
358
+ RRIDSCP_OP_STALL = 1,
359
+ RRIDSCP_OP_NO_STALL = 2,
360
+ RRIDSCP_OP_RESERVED = 3,
361
+} rridscp_op;
362
+
363
+typedef enum {
364
+ RRIDSCP_STAT_NOT_IMPL = 0,
365
+ RRIDSCP_STAT_STALL = 1,
366
+ RRIDSCP_STAT_NO_STALL = 2,
367
+ RRIDSCP_STAT_RRID_NO_IMPL = 3,
368
+} rridscp_stat;
369
+
370
+typedef struct entry_range {
371
+ int md;
372
+ /* Index of entry array */
373
+ int start_idx;
374
+ int end_idx;
375
+} entry_range;
376
+
377
+static void iopmp_iommu_notify(RISCVIOPMPState *s)
378
+{
379
+ IOMMUTLBEvent event = {
380
+ .entry = {
381
+ .iova = 0,
382
+ .translated_addr = 0,
383
+ .addr_mask = -1ULL,
384
+ .perm = IOMMU_NONE,
385
+ },
386
+ .type = IOMMU_NOTIFIER_UNMAP,
387
+ };
388
+
389
+ for (int i = 0; i < s->rrid_num; i++) {
390
+ memory_region_notify_iommu(&s->iommu, i, event);
391
+ }
392
+}
393
+
394
+static void iopmp_msi_send(RISCVIOPMPState *s)
395
+{
396
+ MemTxResult result;
397
+ uint64_t addr = ((uint64_t)(s->regs.err_msiaddrh) << 32) |
398
+ s->regs.err_msiaddr;
399
+ address_space_stl_le(&address_space_memory, addr,
400
+ FIELD_EX32(s->regs.err_cfg, ERR_CFG, MSIDATA),
401
+ (MemTxAttrs){.requester_id = s->msi_rrid}, &result);
402
+ if (result != MEMTX_OK) {
403
+ s->regs.err_info = FIELD_DP32(s->regs.err_info, ERR_INFO, MSI_WERR, 1);
404
+ }
405
+}
406
+
407
+static void iopmp_decode_napot(uint64_t a, uint64_t *sa,
408
+ uint64_t *ea)
409
+{
410
+ /*
411
+ * aaaa...aaa0 8-byte NAPOT range
412
+ * aaaa...aa01 16-byte NAPOT range
413
+ * aaaa...a011 32-byte NAPOT range
414
+ * ...
415
+ * aa01...1111 2^XLEN-byte NAPOT range
416
+ * a011...1111 2^(XLEN+1)-byte NAPOT range
417
+ * 0111...1111 2^(XLEN+2)-byte NAPOT range
418
+ * 1111...1111 Reserved
419
+ */
420
+
421
+ a = (a << 2) | 0x3;
422
+ *sa = a & (a + 1);
423
+ *ea = a | (a + 1);
424
+}
425
+
426
+static void iopmp_update_rule(RISCVIOPMPState *s, uint32_t entry_index)
427
+{
428
+ uint8_t this_cfg = s->regs.entry[entry_index].cfg_reg;
429
+ uint64_t this_addr = s->regs.entry[entry_index].addr_reg |
430
+ ((uint64_t)s->regs.entry[entry_index].addrh_reg << 32);
431
+ uint64_t prev_addr = 0u;
432
+ uint64_t sa = 0u;
433
+ uint64_t ea = 0u;
434
+
435
+ if (entry_index >= 1u) {
436
+ prev_addr = s->regs.entry[entry_index - 1].addr_reg |
437
+ ((uint64_t)s->regs.entry[entry_index - 1].addrh_reg << 32);
438
+ }
439
+
440
+ switch (FIELD_EX32(this_cfg, ENTRY_CFG, A)) {
441
+ case IOPMP_AMATCH_OFF:
442
+ sa = 0u;
443
+ ea = -1;
444
+ break;
445
+
446
+ case IOPMP_AMATCH_TOR:
447
+ sa = (prev_addr) << 2; /* shift up from [xx:0] to [xx+2:2] */
448
+ ea = ((this_addr) << 2) - 1u;
449
+ if (sa > ea) {
450
+ sa = ea = 0u;
451
+ }
452
+ break;
453
+
454
+ case IOPMP_AMATCH_NA4:
455
+ sa = this_addr << 2; /* shift up from [xx:0] to [xx+2:2] */
456
+ ea = (sa + 4u) - 1u;
457
+ break;
458
+
459
+ case IOPMP_AMATCH_NAPOT:
460
+ iopmp_decode_napot(this_addr, &sa, &ea);
461
+ break;
462
+
463
+ default:
464
+ sa = 0u;
465
+ ea = 0u;
466
+ break;
467
+ }
468
+
469
+ s->entry_addr[entry_index].sa = sa;
470
+ s->entry_addr[entry_index].ea = ea;
471
+ iopmp_iommu_notify(s);
472
+}
473
+
474
+static uint64_t iopmp_read(void *opaque, hwaddr addr, unsigned size)
475
+{
476
+ RISCVIOPMPState *s = RISCV_IOPMP(opaque);
477
+ uint32_t rz = 0;
478
+ uint32_t offset, idx;
479
+ /* Start value for ERR_MFR.svi */
480
+ uint16_t svi_s;
481
+
482
+ switch (addr) {
483
+ case A_VERSION:
484
+ rz = FIELD_DP32(rz, VERSION, VENDOR, VENDER_VIRT);
485
+ rz = FIELD_DP32(rz, VERSION, SPECVER, SPECVER_0_9_2);
486
+ break;
487
+ case A_IMPLEMENTATION:
488
+ rz = IMPID_0_9_2;
489
+ break;
490
+ case A_HWCFG0:
491
+ rz = FIELD_DP32(rz, HWCFG0, MDCFG_FMT, s->mdcfg_fmt);
492
+ rz = FIELD_DP32(rz, HWCFG0, SRCMD_FMT, s->srcmd_fmt);
493
+ rz = FIELD_DP32(rz, HWCFG0, TOR_EN, s->tor_en);
494
+ rz = FIELD_DP32(rz, HWCFG0, SPS_EN, s->sps_en);
495
+ rz = FIELD_DP32(rz, HWCFG0, USER_CFG_EN, 0);
496
+ rz = FIELD_DP32(rz, HWCFG0, PRIENT_PROG, s->prient_prog);
497
+ rz = FIELD_DP32(rz, HWCFG0, RRID_TRANSL_EN, s->rrid_transl_en);
498
+ rz = FIELD_DP32(rz, HWCFG0, RRID_TRANSL_PROG, s->rrid_transl_prog);
499
+ rz = FIELD_DP32(rz, HWCFG0, CHK_X, s->chk_x);
500
+ rz = FIELD_DP32(rz, HWCFG0, NO_X, s->no_x);
501
+ rz = FIELD_DP32(rz, HWCFG0, NO_W, s->no_w);
502
+ rz = FIELD_DP32(rz, HWCFG0, STALL_EN, s->stall_en);
503
+ rz = FIELD_DP32(rz, HWCFG0, PEIS, s->peis);
504
+ rz = FIELD_DP32(rz, HWCFG0, PEES, s->pees);
505
+ rz = FIELD_DP32(rz, HWCFG0, MFR_EN, s->mfr_en);
506
+ rz = FIELD_DP32(rz, HWCFG0, MD_ENTRY_NUM, s->md_entry_num);
507
+ rz = FIELD_DP32(rz, HWCFG0, MD_NUM, s->md_num);
508
+ rz = FIELD_DP32(rz, HWCFG0, ADDRH_EN, 1);
509
+ rz = FIELD_DP32(rz, HWCFG0, ENABLE, s->enable);
510
+ break;
511
+ case A_HWCFG1:
512
+ rz = FIELD_DP32(rz, HWCFG1, RRID_NUM, s->rrid_num);
513
+ rz = FIELD_DP32(rz, HWCFG1, ENTRY_NUM, s->entry_num);
514
+ break;
515
+ case A_HWCFG2:
516
+ rz = FIELD_DP32(rz, HWCFG2, PRIO_ENTRY, s->prio_entry);
517
+ rz = FIELD_DP32(rz, HWCFG2, RRID_TRANSL, s->rrid_transl);
518
+ break;
519
+ case A_ENTRYOFFSET:
520
+ rz = s->entry_offset;
521
+ break;
522
+ case A_MDSTALL:
523
+ if (s->stall_en) {
524
+ rz = s->regs.mdstall;
525
+ } else {
526
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad addr %x\n",
527
+ __func__, (int)addr);
528
+ }
529
+ break;
530
+ case A_MDSTALLH:
531
+ if (s->stall_en && s->md_num > 31) {
532
+ rz = s->regs.mdstallh;
533
+ } else {
534
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad addr %x\n",
535
+ __func__, (int)addr);
536
+ }
537
+ break;
538
+ case A_RRIDSCP:
539
+ if (s->stall_en) {
540
+ rz = s->regs.rridscp;
541
+ } else {
542
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad addr %x\n",
543
+ __func__, (int)addr);
544
+ }
545
+ break;
546
+ case A_ERR_CFG:
547
+ rz = s->regs.err_cfg;
548
+ break;
549
+ case A_MDLCK:
550
+ if (s->srcmd_fmt == 1) {
551
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad addr %x\n",
552
+ __func__, (int)addr);
553
+ } else {
554
+ rz = s->regs.mdlck;
555
+ }
556
+ break;
557
+ case A_MDLCKH:
558
+ if (s->md_num < 31 || s->srcmd_fmt == 1) {
559
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad addr %x\n",
560
+ __func__, (int)addr);
561
+ } else {
562
+ rz = s->regs.mdlckh;
563
+ }
564
+ break;
565
+ case A_MDCFGLCK:
566
+ if (s->mdcfg_fmt != 0) {
567
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad addr %x\n",
568
+ __func__, (int)addr);
569
+ break;
570
+ }
571
+ rz = s->regs.mdcfglck;
572
+ break;
573
+ case A_ENTRYLCK:
574
+ rz = s->regs.entrylck;
575
+ break;
576
+ case A_ERR_REQADDR:
577
+ rz = s->regs.err_reqaddr & UINT32_MAX;
578
+ break;
579
+ case A_ERR_REQADDRH:
580
+ rz = s->regs.err_reqaddr >> 32;
581
+ break;
582
+ case A_ERR_REQID:
583
+ rz = s->regs.err_reqid;
584
+ break;
585
+ case A_ERR_INFO:
586
+ rz = s->regs.err_info;
587
+ break;
588
+ case A_ERR_MFR:
589
+ if (!s->mfr_en) {
590
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad addr %x\n",
591
+ __func__, (int)addr);
592
+ break;
593
+ }
594
+ svi_s = s->svi;
595
+ s->regs.err_info = FIELD_DP32(s->regs.err_info, ERR_INFO, SVC, 0);
596
+ while (1) {
597
+ if (s->svw[s->svi]) {
598
+ if (rz == 0) {
599
+ /* First svw is found */
600
+ rz = FIELD_DP32(rz, ERR_MFR, SVW, s->svw[s->svi]);
601
+ rz = FIELD_DP32(rz, ERR_MFR, SVI, s->svi);
602
+ rz = FIELD_DP32(rz, ERR_MFR, SVS, 1);
603
+ /* Clear svw after read */
604
+ s->svw[s->svi] = 0;
605
+ } else {
606
+ /* Other subsequent violation exists */
607
+ s->regs.err_info = FIELD_DP32(s->regs.err_info, ERR_INFO,
608
+ SVC, 1);
609
+ break;
610
+ }
611
+ }
612
+ s->svi++;
613
+ if (s->svi > (s->rrid_num / 16) + 1) {
614
+ s->svi = 0;
615
+ }
616
+ if (svi_s == s->svi) {
617
+ /* rounded back to the same value */
618
+ break;
619
+ }
620
+ }
621
+ /* Set svi for next read */
622
+ s->svi = FIELD_DP32(rz, ERR_MFR, SVI, s->svi);
623
+ break;
624
+ case A_ERR_MSIADDR:
625
+ rz = s->regs.err_msiaddr;
626
+ break;
627
+ case A_ERR_MSIADDRH:
628
+ rz = s->regs.err_msiaddrh;
629
+ break;
630
+
631
+ default:
632
+ if (s->mdcfg_fmt == 0 &&
633
+ addr >= A_MDCFG0 &&
634
+ addr <= A_MDCFG0 + 4 * (s->md_num - 1)) {
635
+ offset = addr - A_MDCFG0;
636
+ if (offset % 4) {
637
+ rz = 0;
638
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad addr %x\n",
639
+ __func__, (int)addr);
640
+ } else {
641
+ idx = offset >> 2;
642
+ rz = s->regs.mdcfg[idx];
643
+ }
644
+ } else if (s->srcmd_fmt == 0 &&
645
+ addr >= A_SRCMD_EN0 &&
646
+ addr <= A_SRCMD_WH0 + 32 * (s->rrid_num - 1)) {
647
+ offset = addr - A_SRCMD_EN0;
648
+ idx = offset >> 5;
649
+ offset &= 0x1f;
650
+
651
+ if (s->sps_en || offset <= SRCMD_ENH_OFFSET) {
652
+ switch (offset) {
653
+ case SRCMD_EN_OFFSET:
654
+ rz = s->regs.srcmd_en[idx];
655
+ break;
656
+ case SRCMD_ENH_OFFSET:
657
+ if (s->md_num > 31) {
658
+ rz = s->regs.srcmd_enh[idx];
659
+ } else {
660
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad addr %x\n",
661
+ __func__, (int)addr);
662
+ }
663
+ break;
664
+ case SRCMD_R_OFFSET:
665
+ rz = s->regs.srcmd_r[idx];
666
+ break;
667
+ case SRCMD_RH_OFFSET:
668
+ if (s->md_num > 31) {
669
+ rz = s->regs.srcmd_rh[idx];
670
+ } else {
671
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad addr %x\n",
672
+ __func__, (int)addr);
673
+ }
674
+ break;
675
+ case SRCMD_W_OFFSET:
676
+ rz = s->regs.srcmd_w[idx];
677
+ break;
678
+ case SRCMD_WH_OFFSET:
679
+ if (s->md_num > 31) {
680
+ rz = s->regs.srcmd_wh[idx];
681
+ } else {
682
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad addr %x\n",
683
+ __func__, (int)addr);
684
+ }
685
+ break;
686
+ default:
687
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad addr %x\n",
688
+ __func__, (int)addr);
689
+ break;
690
+ }
691
+ } else {
692
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad addr %x\n",
693
+ __func__, (int)addr);
694
+ }
695
+ } else if (s->srcmd_fmt == 2 &&
696
+ addr >= A_SRCMD_PERM0 &&
697
+ addr <= A_SRCMD_PERMH0 + 32 * (s->md_num - 1)) {
698
+ offset = addr - A_SRCMD_PERM0;
699
+ idx = offset >> 5;
700
+ offset &= 0x1f;
701
+ switch (offset) {
702
+ case SRCMD_PERM_OFFSET:
703
+ rz = s->regs.srcmd_perm[idx];
704
+ break;
705
+ case SRCMD_PERMH_OFFSET:
706
+ if (s->rrid_num > 16) {
707
+ rz = s->regs.srcmd_permh[idx];
708
+ } else {
709
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad addr %x\n",
710
+ __func__, (int)addr);
711
+ }
712
+ break;
713
+ default:
714
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad addr %x\n",
715
+ __func__, (int)addr);
716
+ break;
717
+ }
718
+ } else if (addr >= s->entry_offset &&
719
+ addr <= s->entry_offset + ENTRY_USER_CFG_OFFSET +
720
+ 16 * (s->entry_num - 1)) {
721
+ offset = addr - s->entry_offset;
722
+ idx = offset >> 4;
723
+ offset &= 0xf;
724
+
725
+ switch (offset) {
726
+ case ENTRY_ADDR_OFFSET:
727
+ rz = s->regs.entry[idx].addr_reg;
728
+ break;
729
+ case ENTRY_ADDRH_OFFSET:
730
+ rz = s->regs.entry[idx].addrh_reg;
731
+ break;
732
+ case ENTRY_CFG_OFFSET:
733
+ rz = s->regs.entry[idx].cfg_reg;
734
+ break;
735
+ default:
736
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad addr %x\n",
737
+ __func__, (int)addr);
738
+ break;
739
+ }
740
+ } else {
741
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad addr %x\n",
742
+ __func__, (int)addr);
743
+ }
744
+ break;
745
+ }
746
+ trace_iopmp_read(addr, rz);
747
+ return rz;
748
+}
749
+
750
+static void update_rrid_stall(RISCVIOPMPState *s)
751
+{
752
+ bool exempt = FIELD_EX32(s->regs.mdstall, MDSTALL, EXEMPT);
753
+ uint64_t stall_by_md = ((uint64_t)s->regs.mdstall |
754
+ ((uint64_t)s->regs.mdstallh << 32)) >> 1;
755
+ uint64_t srcmd_en;
756
+ bool reduction_or;
757
+ if (s->srcmd_fmt != 2) {
758
+ for (int rrid = 0; rrid < s->rrid_num; rrid++) {
759
+ srcmd_en = ((uint64_t)s->regs.srcmd_en[rrid] |
760
+ ((uint64_t)s->regs.srcmd_enh[rrid] << 32)) >> 1;
761
+ reduction_or = 0;
762
+ if (srcmd_en & stall_by_md) {
763
+ reduction_or = 1;
764
+ }
765
+ s->rrid_stall[rrid] = exempt ^ reduction_or;
766
+ }
767
+ } else {
768
+ for (int rrid = 0; rrid < s->rrid_num; rrid++) {
769
+ if (stall_by_md) {
770
+ s->rrid_stall[rrid] = 1;
771
+ } else {
772
+ s->rrid_stall[rrid] = 0;
773
+ }
774
+ }
775
+ }
776
+ iopmp_iommu_notify(s);
777
+}
778
+
779
+static inline void resume_stall(RISCVIOPMPState *s)
780
+{
781
+ for (int rrid = 0; rrid < s->rrid_num; rrid++) {
782
+ s->rrid_stall[rrid] = 0;
783
+ }
784
+ iopmp_iommu_notify(s);
785
+}
786
+
787
+static void
788
+iopmp_write(void *opaque, hwaddr addr, uint64_t value, unsigned size)
789
+{
790
+ RISCVIOPMPState *s = RISCV_IOPMP(opaque);
791
+ uint32_t offset, idx;
792
+ uint32_t value32 = value;
793
+ uint64_t mdlck;
794
+ uint32_t value_f;
795
+ uint32_t rrid;
796
+ uint32_t op;
797
+ trace_iopmp_write(addr, value32);
798
+
799
+ switch (addr) {
800
+ case A_VERSION: /* RO */
801
+ break;
802
+ case A_IMPLEMENTATION: /* RO */
803
+ break;
804
+ case A_HWCFG0:
805
+ if (FIELD_EX32(value32, HWCFG0, RRID_TRANSL_PROG)) {
806
+ /* W1C */
807
+ s->rrid_transl_prog = 0;
808
+ }
809
+ if (FIELD_EX32(value32, HWCFG0, PRIENT_PROG)) {
810
+ /* W1C */
811
+ s->prient_prog = 0;
812
+ }
813
+ if (!s->enable && s->mdcfg_fmt == 2) {
814
+ /* Locked by enable bit */
815
+ s->md_entry_num = FIELD_EX32(value32, HWCFG0, MD_ENTRY_NUM);
816
+ }
817
+ if (FIELD_EX32(value32, HWCFG0, ENABLE)) {
818
+ /* W1S */
819
+ s->enable = 1;
820
+ iopmp_iommu_notify(s);
821
+ }
822
+ break;
823
+ case A_HWCFG1: /* RO */
824
+ break;
825
+ case A_HWCFG2:
826
+ if (s->prient_prog) {
827
+ s->prio_entry = FIELD_EX32(value32, HWCFG2, PRIO_ENTRY);
828
+ iopmp_iommu_notify(s);
829
+ }
830
+ if (s->rrid_transl_prog) {
831
+ s->rrid_transl = FIELD_EX32(value32, HWCFG2, RRID_TRANSL);
832
+ iopmp_iommu_notify(s);
833
+ }
834
+ break;
835
+ case A_ENTRYOFFSET:
836
+ break;
837
+ case A_MDSTALL:
838
+ if (s->stall_en) {
839
+ s->regs.mdstall = value32;
840
+ if (value32) {
841
+ s->is_stalled = 1;
842
+ } else {
843
+ /* Resume if stall, stallh == 0 */
844
+ if (s->regs.mdstallh == 0) {
845
+ s->is_stalled = 0;
846
+ }
847
+ }
848
+ update_rrid_stall(s);
849
+ } else {
850
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad addr %x\n",
851
+ __func__, (int)addr);
852
+ }
853
+ break;
854
+ case A_MDSTALLH:
855
+ if (s->stall_en) {
856
+ s->regs.mdstallh = value32;
857
+ } else {
858
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad addr %x\n",
859
+ __func__, (int)addr);
860
+ }
861
+ break;
862
+ case A_RRIDSCP:
863
+ if (s->stall_en) {
864
+ rrid = FIELD_EX32(value32, RRIDSCP, RRID);
865
+ op = FIELD_EX32(value32, RRIDSCP, OP);
866
+ if (op == RRIDSCP_OP_RESERVED) {
867
+ break;
868
+ }
869
+ s->regs.rridscp = value32;
870
+ if (rrid > s->rrid_num) {
871
+ s->regs.rridscp = FIELD_DP32(s->regs.rridscp, RRIDSCP, STAT,
872
+ RRIDSCP_STAT_RRID_NO_IMPL);
873
+ break;
874
+ }
875
+ switch (op) {
876
+ case RRIDSCP_OP_QUERY:
877
+ if (s->is_stalled) {
878
+ s->regs.rridscp =
879
+ FIELD_DP32(s->regs.rridscp, RRIDSCP, STAT,
880
+ 0x2 >> s->rrid_stall[rrid]);
881
+ } else {
882
+ s->regs.rridscp = FIELD_DP32(s->regs.rridscp, RRIDSCP,
883
+ STAT,
884
+ RRIDSCP_STAT_NO_STALL);
885
+ }
886
+ break;
887
+ case RRIDSCP_OP_STALL:
888
+ s->rrid_stall[rrid] = 1;
889
+ break;
890
+ case RRIDSCP_OP_NO_STALL:
891
+ s->rrid_stall[rrid] = 0;
892
+ break;
893
+ default:
894
+ break;
895
+ }
896
+ if (s->is_stalled) {
897
+ iopmp_iommu_notify(s);
898
+ }
899
+ } else {
900
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad addr %x\n",
901
+ __func__, (int)addr);
902
+ }
903
+ break;
904
+ case A_ERR_CFG:
905
+ if (!FIELD_EX32(s->regs.err_cfg, ERR_CFG, L)) {
906
+ s->regs.err_cfg = FIELD_DP32(s->regs.err_cfg, ERR_CFG, L,
907
+ FIELD_EX32(value32, ERR_CFG, L));
908
+ s->regs.err_cfg = FIELD_DP32(s->regs.err_cfg, ERR_CFG, IE,
909
+ FIELD_EX32(value32, ERR_CFG, IE));
910
+ s->regs.err_cfg = FIELD_DP32(s->regs.err_cfg, ERR_CFG, RS,
911
+ FIELD_EX32(value32, ERR_CFG, RS));
912
+ s->regs.err_cfg = FIELD_DP32(s->regs.err_cfg, ERR_CFG, MSI_EN,
913
+ FIELD_EX32(value32, ERR_CFG, MSI_EN));
914
+ s->regs.err_cfg = FIELD_DP32(s->regs.err_cfg, ERR_CFG,
915
+ STALL_VIOLATION_EN, FIELD_EX32(value32, ERR_CFG,
916
+ STALL_VIOLATION_EN));
917
+ s->regs.err_cfg = FIELD_DP32(s->regs.err_cfg, ERR_CFG, MSIDATA,
918
+ FIELD_EX32(value32, ERR_CFG, MSIDATA));
919
+ }
920
+ break;
921
+ case A_MDLCK:
922
+ if (s->srcmd_fmt == 1) {
923
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad addr %x\n",
924
+ __func__, (int)addr);
925
+ } else if (!FIELD_EX32(s->regs.mdlck, MDLCK, L)) {
926
+ /* sticky to 1 */
927
+ s->regs.mdlck |= value32;
928
+ if (s->md_num <= 31) {
929
+ s->regs.mdlck = extract32(s->regs.mdlck, 0, s->md_num + 1);
930
+ }
931
+ }
932
+ break;
933
+ case A_MDLCKH:
934
+ if (s->md_num < 31 || s->srcmd_fmt == 1) {
935
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad addr %x\n",
936
+ __func__, (int)addr);
937
+ } else if (!FIELD_EX32(s->regs.mdlck, MDLCK, L)) {
938
+ /* sticky to 1 */
939
+ s->regs.mdlckh |= value32;
940
+ s->regs.mdlck = extract32(s->regs.mdlck, 0, s->md_num - 31);
941
+ }
942
+ break;
943
+ case A_MDCFGLCK:
944
+ if (s->mdcfg_fmt != 0) {
945
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad addr %x\n",
946
+ __func__, (int)addr);
947
+ break;
948
+ }
949
+ if (!FIELD_EX32(s->regs.mdcfglck, MDCFGLCK, L)) {
950
+ value_f = FIELD_EX32(value32, MDCFGLCK, F);
951
+ if (value_f > FIELD_EX32(s->regs.mdcfglck, MDCFGLCK, F)) {
952
+ s->regs.mdcfglck = FIELD_DP32(s->regs.mdcfglck, MDCFGLCK, F,
953
+ value_f);
954
+ }
955
+ s->regs.mdcfglck = FIELD_DP32(s->regs.mdcfglck, MDCFGLCK, L,
956
+ FIELD_EX32(value32, MDCFGLCK, L));
957
+ }
958
+ break;
959
+ case A_ENTRYLCK:
960
+ if (!(FIELD_EX32(s->regs.entrylck, ENTRYLCK, L))) {
961
+ value_f = FIELD_EX32(value32, ENTRYLCK, F);
962
+ if (value_f > FIELD_EX32(s->regs.entrylck, ENTRYLCK, F)) {
963
+ s->regs.entrylck = FIELD_DP32(s->regs.entrylck, ENTRYLCK, F,
964
+ value_f);
965
+ }
966
+ s->regs.entrylck = FIELD_DP32(s->regs.entrylck, ENTRYLCK, L,
967
+ FIELD_EX32(value32, ENTRYLCK, L));
968
+ }
969
+ case A_ERR_REQADDR: /* RO */
970
+ break;
971
+ case A_ERR_REQADDRH: /* RO */
972
+ break;
973
+ case A_ERR_REQID: /* RO */
974
+ break;
975
+ case A_ERR_INFO:
976
+ if (FIELD_EX32(value32, ERR_INFO, V)) {
977
+ s->regs.err_info = FIELD_DP32(s->regs.err_info, ERR_INFO, V, 0);
978
+ qemu_set_irq(s->irq, 0);
979
+ }
980
+ if (FIELD_EX32(value32, ERR_INFO, MSI_WERR)) {
981
+ s->regs.err_info = FIELD_DP32(s->regs.err_info, ERR_INFO, MSI_WERR,
982
+ 0);
983
+ }
984
+ break;
985
+ case A_ERR_MFR:
986
+ s->svi = FIELD_EX32(value32, ERR_MFR, SVI);
987
+ break;
988
+ case A_ERR_MSIADDR:
989
+ if (!FIELD_EX32(s->regs.err_cfg, ERR_CFG, L)) {
990
+ s->regs.err_msiaddr = value32;
991
+ }
992
+ break;
993
+
994
+ case A_ERR_MSIADDRH:
995
+ if (!FIELD_EX32(s->regs.err_cfg, ERR_CFG, L)) {
996
+ s->regs.err_msiaddrh = value32;
997
+ }
998
+ break;
999
+
1000
+ default:
1001
+ if (s->mdcfg_fmt == 0 &&
1002
+ addr >= A_MDCFG0 &&
1003
+ addr <= A_MDCFG0 + 4 * (s->md_num - 1)) {
1004
+ offset = addr - A_MDCFG0;
1005
+ if (offset % 4) {
1006
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad addr %x\n",
1007
+ __func__, (int)addr);
1008
+ } else {
1009
+ idx = offset >> 2;
1010
+ s->regs.mdcfg[idx] = FIELD_EX32(value32, MDCFG0, T);
1011
+ iopmp_iommu_notify(s);
1012
+ }
1013
+ } else if (s->srcmd_fmt == 0 &&
1014
+ addr >= A_SRCMD_EN0 &&
1015
+ addr <= A_SRCMD_WH0 + 32 * (s->rrid_num - 1)) {
1016
+ offset = addr - A_SRCMD_EN0;
1017
+ idx = offset >> 5;
1018
+ offset &= 0x1f;
1019
+
1020
+ if (offset % 4 || (!s->sps_en && offset > SRCMD_ENH_OFFSET)) {
1021
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad addr %x\n",
1022
+ __func__, (int)addr);
1023
+ } else if (FIELD_EX32(s->regs.srcmd_en[idx], SRCMD_EN0, L) == 0) {
1024
+ /* MD field is protected by mdlck */
1025
+ value32 = (value32 & ~s->regs.mdlck) |
1026
+ (s->regs.srcmd_en[idx] & s->regs.mdlck);
1027
+ iopmp_iommu_notify(s);
1028
+ switch (offset) {
1029
+ case SRCMD_EN_OFFSET:
1030
+ s->regs.srcmd_en[idx] =
1031
+ FIELD_DP32(s->regs.srcmd_en[idx], SRCMD_EN0, L,
1032
+ FIELD_EX32(value32, SRCMD_EN0, L));
1033
+ s->regs.srcmd_en[idx] =
1034
+ FIELD_DP32(s->regs.srcmd_en[idx], SRCMD_EN0, MD,
1035
+ FIELD_EX32(value32, SRCMD_EN0, MD));
1036
+ if (s->md_num <= 31) {
1037
+ s->regs.srcmd_en[idx] = extract32(s->regs.srcmd_en[idx],
1038
+ 0, s->md_num + 1);
1039
+ }
1040
+ break;
1041
+ case SRCMD_ENH_OFFSET:
1042
+ if (s->md_num > 31) {
1043
+ s->regs.srcmd_enh[idx] = value32;
1044
+ s->regs.srcmd_enh[idx] =
1045
+ extract32(s->regs.srcmd_enh[idx], 0,
1046
+ s->md_num - 31);
1047
+ } else {
1048
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad addr %x\n",
1049
+ __func__, (int)addr);
1050
+ }
1051
+ break;
1052
+ case SRCMD_R_OFFSET:
1053
+ s->regs.srcmd_r[idx] =
1054
+ FIELD_DP32(s->regs.srcmd_r[idx], SRCMD_R0, MD,
1055
+ FIELD_EX32(value32, SRCMD_R0, MD));
1056
+ if (s->md_num <= 31) {
1057
+ s->regs.srcmd_r[idx] = extract32(s->regs.srcmd_r[idx],
1058
+ 0, s->md_num + 1);
1059
+ }
1060
+ break;
1061
+ case SRCMD_RH_OFFSET:
1062
+ if (s->md_num > 31) {
1063
+ s->regs.srcmd_rh[idx] = value32;
1064
+ s->regs.srcmd_rh[idx] =
1065
+ extract32(s->regs.srcmd_rh[idx], 0,
1066
+ s->md_num - 31);
1067
+ } else {
1068
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad addr %x\n",
1069
+ __func__, (int)addr);
1070
+ }
1071
+ break;
1072
+ case SRCMD_W_OFFSET:
1073
+ s->regs.srcmd_w[idx] =
1074
+ FIELD_DP32(s->regs.srcmd_w[idx], SRCMD_W0, MD,
1075
+ FIELD_EX32(value32, SRCMD_W0, MD));
1076
+ if (s->md_num <= 31) {
1077
+ s->regs.srcmd_w[idx] = extract32(s->regs.srcmd_w[idx],
1078
+ 0, s->md_num + 1);
1079
+ }
1080
+ break;
1081
+ case SRCMD_WH_OFFSET:
1082
+ if (s->md_num > 31) {
1083
+ s->regs.srcmd_wh[idx] = value32;
1084
+ s->regs.srcmd_wh[idx] =
1085
+ extract32(s->regs.srcmd_wh[idx], 0,
1086
+ s->md_num - 31);
1087
+ } else {
1088
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad addr %x\n",
1089
+ __func__, (int)addr);
1090
+ }
1091
+ break;
1092
+ default:
1093
+ break;
1094
+ }
1095
+ }
1096
+ } else if (s->srcmd_fmt == 2 &&
1097
+ addr >= A_SRCMD_PERM0 &&
1098
+ addr <= A_SRCMD_PERMH0 + 32 * (s->md_num - 1)) {
1099
+ offset = addr - A_SRCMD_PERM0;
1100
+ idx = offset >> 5;
1101
+ offset &= 0x1f;
1102
+ /* mdlck lock bit is removed */
1103
+ mdlck = ((uint64_t)s->regs.mdlck |
1104
+ ((uint64_t)s->regs.mdlckh << 32)) >> 1;
1105
+ iopmp_iommu_notify(s);
1106
+ switch (offset) {
1107
+ case SRCMD_PERM_OFFSET:
1108
+ /* srcmd_perm[md] is protect by mdlck */
1109
+ if (((mdlck >> idx) & 0x1) == 0) {
1110
+ s->regs.srcmd_perm[idx] = value32;
1111
+ }
1112
+ if (s->rrid_num <= 16) {
1113
+ s->regs.srcmd_perm[idx] = extract32(s->regs.srcmd_perm[idx],
1114
+ 0, 2 * s->rrid_num);
1115
+ }
1116
+ break;
1117
+ case SRCMD_PERMH_OFFSET:
1118
+ if (s->rrid_num > 16) {
1119
+ if (((mdlck >> idx) & 0x1) == 0) {
1120
+ s->regs.srcmd_permh[idx] = value32;
1121
+ }
1122
+ s->regs.srcmd_permh[idx] =
1123
+ extract32(s->regs.srcmd_permh[idx], 0,
1124
+ 2 * (s->rrid_num - 16));
1125
+ } else {
1126
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad addr %x\n",
1127
+ __func__, (int)addr);
1128
+ }
1129
+ break;
1130
+ default:
1131
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad addr %x\n",
1132
+ __func__, (int)addr);
1133
+ break;
1134
+ }
1135
+ } else if (addr >= s->entry_offset &&
1136
+ addr <= s->entry_offset + ENTRY_USER_CFG_OFFSET
1137
+ + 16 * (s->entry_num - 1)) {
1138
+ offset = addr - s->entry_offset;
1139
+ idx = offset >> 4;
1140
+ offset &= 0xf;
1141
+
1142
+ /* index < ENTRYLCK_F is protected */
1143
+ if (idx >= FIELD_EX32(s->regs.entrylck, ENTRYLCK, F)) {
1144
+ switch (offset) {
1145
+ case ENTRY_ADDR_OFFSET:
1146
+ s->regs.entry[idx].addr_reg = value32;
1147
+ break;
1148
+ case ENTRY_ADDRH_OFFSET:
1149
+ s->regs.entry[idx].addrh_reg = value32;
1150
+ break;
1151
+ case ENTRY_CFG_OFFSET:
1152
+ s->regs.entry[idx].cfg_reg = value32;
1153
+ if (!s->tor_en &&
1154
+ FIELD_EX32(s->regs.entry[idx].cfg_reg,
1155
+ ENTRY_CFG, A) == IOPMP_AMATCH_TOR) {
1156
+ s->regs.entry[idx].cfg_reg =
1157
+ FIELD_DP32(s->regs.entry[idx].cfg_reg, ENTRY_CFG, A,
1158
+ IOPMP_AMATCH_OFF);
1159
+ }
1160
+ if (!s->peis) {
1161
+ s->regs.entry[idx].cfg_reg =
1162
+ FIELD_DP32(s->regs.entry[idx].cfg_reg, ENTRY_CFG,
1163
+ SIE, 0);
1164
+ }
1165
+ if (!s->pees) {
1166
+ s->regs.entry[idx].cfg_reg =
1167
+ FIELD_DP32(s->regs.entry[idx].cfg_reg, ENTRY_CFG,
1168
+ SEE, 0);
1169
+ }
1170
+ break;
1171
+ case ENTRY_USER_CFG_OFFSET:
1172
+ /* Does not support user customized permission */
1173
+ break;
1174
+ default:
1175
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad addr %x\n",
1176
+ __func__, (int)addr);
1177
+ break;
1178
+ }
1179
+ iopmp_update_rule(s, idx);
1180
+ if (idx + 1 < s->entry_num &&
1181
+ FIELD_EX32(s->regs.entry[idx + 1].cfg_reg, ENTRY_CFG, A) ==
1182
+ IOPMP_AMATCH_TOR) {
1183
+ iopmp_update_rule(s, idx + 1);
1184
+ }
1185
+ }
1186
+ } else {
1187
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad addr %x\n", __func__,
1188
+ (int)addr);
1189
+ }
1190
+ }
1191
+}
1192
+
1193
+static void apply_sps_permission(RISCVIOPMPState *s, int rrid, int md, int *cfg)
1194
+{
1195
+ uint64_t srcmd_r, srcmd_w;
1196
+ srcmd_r = ((uint64_t)s->regs.srcmd_rh[rrid]) << 32 | s->regs.srcmd_r[rrid];
1197
+ srcmd_w = ((uint64_t)s->regs.srcmd_wh[rrid]) << 32 | s->regs.srcmd_w[rrid];
1198
+ if (((srcmd_r >> (md + 1)) & 0x1) == 0) {
1199
+ /* remove r&x permission and error suppression */
1200
+ *cfg = FIELD_DP32(*cfg, ENTRY_CFG, R, 0);
1201
+ *cfg = FIELD_DP32(*cfg, ENTRY_CFG, X, 0);
1202
+ *cfg = FIELD_DP32(*cfg, ENTRY_CFG, SIRE, 0);
1203
+ *cfg = FIELD_DP32(*cfg, ENTRY_CFG, SERE, 0);
1204
+ *cfg = FIELD_DP32(*cfg, ENTRY_CFG, SIXE, 0);
1205
+ *cfg = FIELD_DP32(*cfg, ENTRY_CFG, SEXE, 0);
1206
+ }
1207
+ if (((srcmd_w >> (md + 1)) & 0x1) == 0) {
1208
+ /* remove w permission and error suppression */
1209
+ *cfg = FIELD_DP32(*cfg, ENTRY_CFG, W, 0);
1210
+ *cfg = FIELD_DP32(*cfg, ENTRY_CFG, SIWE, 0);
1211
+ *cfg = FIELD_DP32(*cfg, ENTRY_CFG, SEWE, 0);
1212
+ }
1213
+}
1214
+
1215
+static void apply_srcmdperm(RISCVIOPMPState *s, int rrid, int md, int *cfg)
1216
+{
1217
+ uint64_t srcmd_perm = ((uint64_t)s->regs.srcmd_permh[md]) << 32 |
1218
+ s->regs.srcmd_perm[md];
1219
+
1220
+ if (((srcmd_perm >> (2 * rrid)) & 0x1)) {
1221
+ /* add r&x permission */
1222
+ *cfg = FIELD_DP32(*cfg, ENTRY_CFG, R, 1);
1223
+ *cfg = FIELD_DP32(*cfg, ENTRY_CFG, X, 1);
1224
+ }
1225
+ if (((srcmd_perm >> (2 * rrid + 1)) & 0x1)) {
1226
+ /* add w permission */
1227
+ *cfg = FIELD_DP32(*cfg, ENTRY_CFG, W, 1);
1228
+ }
1229
+}
1230
+
1231
+static inline void apply_no_chk_x(int *cfg)
1232
+{
1233
+ /* Use read permission for fetch */
1234
+ *cfg = FIELD_DP32(*cfg, ENTRY_CFG, X, FIELD_EX32(*cfg, ENTRY_CFG, R));
1235
+}
1236
+
1237
+/*
1238
+ * entry_range_list: The entry ranges from SRCMD and MDCFG to match
1239
+ * entry_idx: matched priority entry index or first non-priority entry index
1240
+ * cfg: entry cfg for matched priority entry and overlap permission and
1241
+ * supression of matched on-priority entries
1242
+ * iopmp_tlb_size: If entire tlb has the same permission, the value is
1243
+ * TARGET_PAGE_SIZE, otherwise is 1.
1244
+ */
1245
+static iopmp_entry_hit match_entry_range(RISCVIOPMPState *s, int rrid,
1246
+ GSList *entry_range_list,
1247
+ hwaddr sa, hwaddr ea,
1248
+ int *entry_idx, int *cfg,
1249
+ hwaddr *iopmp_tlb_size)
1250
+{
1251
+ entry_range *range;
1252
+ iopmp_entry_hit result = IOPMP_ENTRY_NO_HIT;
1253
+ *iopmp_tlb_size = TARGET_PAGE_SIZE;
1254
+ *cfg = 0;
1255
+ int i = 0;
1256
+ int s_idx, e_idx;
1257
+ hwaddr tlb_sa = sa & ~(TARGET_PAGE_SIZE - 1);
1258
+ hwaddr tlb_ea = (ea & ~(TARGET_PAGE_SIZE - 1)) + TARGET_PAGE_SIZE - 1;
1259
+ int tlb_cfg = 0;
1260
+ int md;
1261
+ int curr_cfg;
1262
+
1263
+ while (entry_range_list) {
1264
+ range = (entry_range *)entry_range_list->data;
1265
+ s_idx = range->start_idx;
1266
+ e_idx = range->end_idx;
1267
+ md = range->md;
1268
+ if (e_idx > s->entry_num) {
1269
+ e_idx = s->entry_num;
1270
+ }
1271
+ for (i = s_idx; i < e_idx; i++) {
1272
+ if (FIELD_EX32(s->regs.entry[i].cfg_reg, ENTRY_CFG, A) ==
1273
+ IOPMP_AMATCH_OFF) {
1274
+ continue;
1275
+ }
1276
+
1277
+ if (i < s->prio_entry) {
1278
+ if (iopmp_tlb_size != NULL &&
1279
+ *iopmp_tlb_size == TARGET_PAGE_SIZE) {
1280
+ if ((s->entry_addr[i].sa >= tlb_sa &&
1281
+ s->entry_addr[i].sa <= tlb_ea) ||
1282
+ (s->entry_addr[i].ea >= tlb_sa &&
1283
+ s->entry_addr[i].ea <= tlb_ea)) {
1284
+ /*
1285
+ * A higher priority entry in the same TLB page,
1286
+ * but it does not occupy the entire page.
1287
+ */
1288
+ *iopmp_tlb_size = 1;
1289
+ }
1290
+ }
1291
+ if (sa >= s->entry_addr[i].sa &&
1292
+ sa <= s->entry_addr[i].ea) {
1293
+ if (ea >= s->entry_addr[i].sa &&
1294
+ ea <= s->entry_addr[i].ea) {
1295
+ *entry_idx = i;
1296
+ *cfg = s->regs.entry[i].cfg_reg;
1297
+ if (s->sps_en) {
1298
+ apply_sps_permission(s, rrid, md, cfg);
1299
+ }
1300
+ if (s->srcmd_fmt == 2) {
1301
+ apply_srcmdperm(s, rrid, md, cfg);
1302
+ }
1303
+ if (!s->chk_x) {
1304
+ apply_no_chk_x(cfg);
1305
+ }
1306
+ return IOPMP_ENTRY_HIT;
1307
+ } else {
1308
+ *entry_idx = i;
1309
+ return IOPMP_ENTRY_PAR_HIT;
1310
+ }
1311
+ } else if (ea >= s->entry_addr[i].sa &&
1312
+ ea <= s->entry_addr[i].ea) {
1313
+ *entry_idx = i;
1314
+ return IOPMP_ENTRY_PAR_HIT;
1315
+ } else if (sa < s->entry_addr[i].sa &&
1316
+ ea > s->entry_addr[i].ea) {
1317
+ *entry_idx = i;
1318
+ return IOPMP_ENTRY_PAR_HIT;
1319
+ }
1320
+ } else {
1321
+ /* Try to check entire tlb permission */
1322
+ if (*iopmp_tlb_size != 1 &&
1323
+ tlb_sa >= s->entry_addr[i].sa &&
1324
+ tlb_sa <= s->entry_addr[i].ea) {
1325
+ if (tlb_ea >= s->entry_addr[i].sa &&
1326
+ tlb_ea <= s->entry_addr[i].ea) {
1327
+ result = IOPMP_ENTRY_HIT;
1328
+ curr_cfg = s->regs.entry[i].cfg_reg;
1329
+ if (*entry_idx == -1) {
1330
+ /* record first matched non-priorty entry */
1331
+ *entry_idx = i;
1332
+ }
1333
+ if (s->sps_en) {
1334
+ apply_sps_permission(s, rrid, md, &curr_cfg);
1335
+ }
1336
+ if (s->srcmd_fmt == 2) {
1337
+ apply_srcmdperm(s, rrid, md, &curr_cfg);
1338
+ }
1339
+ if (!s->chk_x) {
1340
+ apply_no_chk_x(&curr_cfg);
1341
+ }
1342
+ tlb_cfg |= curr_cfg;
1343
+ if ((tlb_cfg & 0x7) == 0x7) {
1344
+ /* Already have RWX permission */
1345
+ *cfg = tlb_cfg;
1346
+ return result;
1347
+ }
1348
+ }
1349
+ }
1350
+ if (sa >= s->entry_addr[i].sa &&
1351
+ sa <= s->entry_addr[i].ea) {
1352
+ if (ea >= s->entry_addr[i].sa &&
1353
+ ea <= s->entry_addr[i].ea) {
1354
+ result = IOPMP_ENTRY_HIT;
1355
+ if (*entry_idx == -1) {
1356
+ /* record first matched non-priorty entry */
1357
+ *entry_idx = i;
1358
+ }
1359
+ curr_cfg = s->regs.entry[i].cfg_reg;
1360
+ if (s->sps_en) {
1361
+ apply_sps_permission(s, rrid, md, &curr_cfg);
1362
+ }
1363
+ if (s->srcmd_fmt == 2) {
1364
+ apply_srcmdperm(s, rrid, md, &curr_cfg);
1365
+ }
1366
+ if (!s->chk_x) {
1367
+ apply_no_chk_x(&curr_cfg);
1368
+ }
1369
+ *cfg |= curr_cfg;
1370
+ if ((*cfg & 0x7) == 0x7 && *iopmp_tlb_size == 1) {
1371
+ /*
1372
+ * Already have RWX permission and a higher priority
1373
+ * entry in the same TLB page, checking the
1374
+ * next non-priority entry is unnecessary
1375
+ */
1376
+ return result;
1377
+ }
1378
+ }
1379
+ }
1380
+ }
1381
+ }
1382
+ entry_range_list = entry_range_list->next;
1383
+ }
1384
+ if (result == IOPMP_ENTRY_HIT && (*cfg & 0x7) != (tlb_cfg & 0x7)) {
1385
+ /*
1386
+ * For non-priority entry hit, if the tlb permssion is different to
1387
+ * matched entries permssion, reduce iopmp_tlb_size
1388
+ */
1389
+ *iopmp_tlb_size = 1;
1390
+ }
1391
+ return result;
1392
+}
1393
+
1394
+static void entry_range_list_data_free(gpointer data)
1395
+{
1396
+ entry_range *range = (entry_range *)data;
1397
+ g_free(range);
1398
+}
1399
+
1400
+static iopmp_entry_hit match_entry_srcmd(RISCVIOPMPState *s, int rrid,
1401
+ hwaddr start_addr, hwaddr end_addr,
1402
+ int *match_entry_idx, int *cfg,
1403
+ hwaddr *iopmp_tlb_size)
1404
+{
1405
+ iopmp_entry_hit result = IOPMP_ENTRY_NO_HIT;
1406
+ GSList *entry_range_list = NULL;
1407
+ uint64_t srcmd_en;
1408
+ int k;
1409
+ entry_range *range;
1410
+ int md_idx;
1411
+ if (s->srcmd_fmt == 1) {
1412
+ range = g_malloc(sizeof(*range));
1413
+ md_idx = rrid;
1414
+ range->md = md_idx;
1415
+ if (s->mdcfg_fmt == 0) {
1416
+ if (md_idx > 0) {
1417
+ range->start_idx = FIELD_EX32(s->regs.mdcfg[md_idx - 1],
1418
+ MDCFG0, T);
1419
+ } else {
1420
+ range->start_idx = 0;
1421
+ }
1422
+ range->end_idx = FIELD_EX32(s->regs.mdcfg[md_idx], MDCFG0, T);
1423
+ } else {
1424
+ k = s->md_entry_num + 1;
1425
+ range->start_idx = md_idx * k;
1426
+ range->end_idx = (md_idx + 1) * k;
1427
+ }
1428
+ entry_range_list = g_slist_append(entry_range_list, range);
1429
+ } else {
1430
+ for (md_idx = 0; md_idx < s->md_num; md_idx++) {
1431
+ srcmd_en = ((uint64_t)s->regs.srcmd_en[rrid] |
1432
+ ((uint64_t)s->regs.srcmd_enh[rrid] << 32)) >> 1;
1433
+ range = NULL;
1434
+ if (s->srcmd_fmt == 2) {
1435
+ /* All entries are needed to be checked in srcmd_fmt2 */
1436
+ srcmd_en = -1;
1437
+ }
1438
+ if (srcmd_en & (1ULL << md_idx)) {
1439
+ range = g_malloc(sizeof(*range));
1440
+ range->md = md_idx;
1441
+ if (s->mdcfg_fmt == 0) {
1442
+ if (md_idx > 0) {
1443
+ range->start_idx = FIELD_EX32(s->regs.mdcfg[md_idx - 1],
1444
+ MDCFG0, T);
1445
+ } else {
1446
+ range->start_idx = 0;
1447
+ }
1448
+ range->end_idx = FIELD_EX32(s->regs.mdcfg[md_idx],
1449
+ MDCFG0, T);
1450
+ } else {
1451
+ k = s->md_entry_num + 1;
1452
+ range->start_idx = md_idx * k;
1453
+ range->end_idx = (md_idx + 1) * k;
1454
+ }
1455
+ }
1456
+ /*
1457
+ * There is no more memory domain after it enconter an invalid
1458
+ * mdcfg. Note that the behavior of mdcfg(t+1).f < mdcfg(t).f is
1459
+ * implementation-dependent.
1460
+ */
1461
+ if (range != NULL) {
1462
+ if (range->end_idx < range->start_idx) {
1463
+ break;
1464
+ }
1465
+ entry_range_list = g_slist_append(entry_range_list, range);
1466
+ }
1467
+ }
1468
+ }
1469
+ result = match_entry_range(s, rrid, entry_range_list, start_addr, end_addr,
1470
+ match_entry_idx, cfg, iopmp_tlb_size);
1471
+ g_slist_free_full(entry_range_list, entry_range_list_data_free);
1472
+ return result;
1473
+}
1474
+
1475
+static MemTxResult iopmp_error_reaction(RISCVIOPMPState *s, uint32_t rrid,
1476
+ uint32_t eid, hwaddr addr,
1477
+ uint32_t etype, uint32_t ttype,
1478
+ uint32_t cfg, uint64_t *data)
1479
+{
1480
+ uint32_t error_id = 0;
1481
+ uint32_t error_info = 0;
1482
+ int offset;
1483
+ /* interrupt enable regarding the access */
1484
+ int ie;
1485
+ /* bus error enable */
1486
+ int be;
1487
+ int error_record;
1488
+
1489
+ if (etype >= ERR_INFO_ETYPE_READ && etype <= ERR_INFO_ETYPE_WRITE) {
1490
+ offset = etype - ERR_INFO_ETYPE_READ;
1491
+ ie = (FIELD_EX32(s->regs.err_cfg, ERR_CFG, IE) &&
1492
+ !extract32(cfg, R_ENTRY_CFG_SIRE_SHIFT + offset, 1));
1493
+ be = (!FIELD_EX32(s->regs.err_cfg, ERR_CFG, RS) &&
1494
+ !extract32(cfg, R_ENTRY_CFG_SERE_SHIFT + offset, 1));
1495
+ } else {
1496
+ ie = extract32(s->regs.err_cfg, R_ERR_CFG_IE_SHIFT, 1);
1497
+ be = !extract32(s->regs.err_cfg, R_ERR_CFG_RS_SHIFT, 1);
1498
+ }
1499
+ error_record = (ie | be) && !(s->transaction_state[rrid].running &&
1500
+ s->transaction_state[rrid].error_reported);
1501
+ if (error_record) {
1502
+ if (s->transaction_state[rrid].running) {
1503
+ s->transaction_state[rrid].error_reported = true;
1504
+ }
1505
+ /* Update error information if the error is not suppressed */
1506
+ if (!FIELD_EX32(s->regs.err_info, ERR_INFO, V)) {
1507
+ error_id = FIELD_DP32(error_id, ERR_REQID, EID, eid);
1508
+ error_id = FIELD_DP32(error_id, ERR_REQID, RRID, rrid);
1509
+ error_info = FIELD_DP32(error_info, ERR_INFO, ETYPE, etype);
1510
+ error_info = FIELD_DP32(error_info, ERR_INFO, TTYPE, ttype);
1511
+ s->regs.err_info = error_info;
1512
+ s->regs.err_info = FIELD_DP32(s->regs.err_info, ERR_INFO, V, 1);
1513
+ s->regs.err_reqid = error_id;
1514
+ /* addr[LEN+2:2] */
1515
+ s->regs.err_reqaddr = addr >> 2;
1516
+ if (ie) {
1517
+ if (FIELD_EX32(s->regs.err_cfg, ERR_CFG, MSI_EN)) {
1518
+ iopmp_msi_send(s);
1519
+ } else {
1520
+ qemu_set_irq(s->irq, 1);
1521
+ }
1522
+ }
1523
+ } else if (s->mfr_en) {
1524
+ s->svw[rrid / 16] |= (1 << (rrid % 16));
1525
+ s->regs.err_info = FIELD_DP32(s->regs.err_info, ERR_INFO, SVC, 1);
1526
+ }
1527
+ }
1528
+ if (be) {
1529
+ return MEMTX_ERROR;
1530
+ } else {
1531
+ if (data) {
1532
+ *data = s->err_rdata;
1533
+ }
1534
+ return MEMTX_OK;
1535
+ }
1536
+}
1537
+
1538
+static IOMMUTLBEntry iopmp_translate(IOMMUMemoryRegion *iommu, hwaddr addr,
1539
+ IOMMUAccessFlags flags, int iommu_idx)
1540
+{
1541
+ int rrid = iommu_idx;
1542
+ RISCVIOPMPState *s = RISCV_IOPMP(container_of(iommu,
1543
+ RISCVIOPMPState, iommu));
1544
+ hwaddr start_addr, end_addr;
1545
+ int entry_idx = -1;
1546
+ hwaddr iopmp_tlb_size = TARGET_PAGE_SIZE;
1547
+ int match_cfg = 0;
1548
+ iopmp_entry_hit result;
1549
+ iopmp_permission iopmp_perm;
1550
+ bool lock = false;
1551
+ IOMMUTLBEntry entry = {
1552
+ .target_as = &s->downstream_as,
1553
+ .iova = addr,
1554
+ .translated_addr = addr,
1555
+ .addr_mask = 0,
1556
+ .perm = IOMMU_NONE,
1557
+ };
1558
+
1559
+ if (!s->enable) {
1560
+ /* Bypass IOPMP */
1561
+ entry.addr_mask = TARGET_PAGE_SIZE - 1,
1562
+ entry.perm = IOMMU_RW;
1563
+ return entry;
1564
+ }
1565
+
1566
+ /* unknown RRID */
1567
+ if (rrid >= s->rrid_num) {
1568
+ entry.target_as = &s->blocked_rwx_as;
1569
+ entry.perm = IOMMU_RW;
1570
+ return entry;
1571
+ }
1572
+
1573
+ if (s->is_stalled && s->rrid_stall[rrid]) {
1574
+ if (FIELD_EX32(s->regs.err_cfg, ERR_CFG, STALL_VIOLATION_EN)) {
1575
+ entry.target_as = &s->blocked_rwx_as;
1576
+ entry.perm = IOMMU_RW;
1577
+ return entry;
1578
+ } else {
1579
+ if (bql_locked()) {
1580
+ bql_unlock();
1581
+ lock = true;
1582
+ }
1583
+ while (s->is_stalled && s->rrid_stall[rrid]) {
1584
+ ;
1585
+ }
1586
+ if (lock) {
1587
+ bql_lock();
1588
+ }
1589
+ }
1590
+ }
1591
+
1592
+ if (s->transaction_state[rrid].running == true) {
1593
+ start_addr = s->transaction_state[rrid].start_addr;
1594
+ end_addr = s->transaction_state[rrid].end_addr;
1595
+ } else {
1596
+ /* No transaction information, use the same address */
1597
+ start_addr = addr;
1598
+ end_addr = addr;
1599
+ }
1600
+ result = match_entry_srcmd(s, rrid, start_addr, end_addr, &entry_idx,
1601
+ &match_cfg, &iopmp_tlb_size);
1602
+ entry.addr_mask = iopmp_tlb_size - 1;
1603
+ /* Remove permission for no_x, no_w*/
1604
+ if (s->chk_x && s->no_x) {
1605
+ match_cfg = FIELD_DP32(match_cfg, ENTRY_CFG, X, 0);
1606
+ }
1607
+ if (s->no_w) {
1608
+ match_cfg = FIELD_DP32(match_cfg, ENTRY_CFG, W, 0);
1609
+ }
1610
+ if (result == IOPMP_ENTRY_HIT) {
1611
+ iopmp_perm = match_cfg & IOPMP_RWX;
1612
+ if (flags) {
1613
+ if ((iopmp_perm & flags) == 0) {
1614
+ /* Permission denied */
1615
+ entry.target_as = &s->blocked_rwx_as;
1616
+ entry.perm = IOMMU_RW;
1617
+ } else {
1618
+ entry.target_as = &s->downstream_as;
1619
+ if (s->rrid_transl_en) {
1620
+ /* Indirectly access for rrid_transl */
1621
+ entry.target_as = &s->full_as;
1622
+ }
1623
+ entry.perm = iopmp_perm;
1624
+ }
1625
+ } else {
1626
+ /* CPU access with IOMMU_NONE flag */
1627
+ if (iopmp_perm & IOPMP_XO) {
1628
+ if ((iopmp_perm & IOPMP_RW) == IOPMP_RW) {
1629
+ entry.target_as = &s->downstream_as;
1630
+ if (s->rrid_transl_en) {
1631
+ entry.target_as = &s->full_as;
1632
+ }
1633
+ } else if ((iopmp_perm & IOPMP_RW) == IOPMP_RO) {
1634
+ entry.target_as = &s->blocked_w_as;
1635
+ } else if ((iopmp_perm & IOPMP_RW) == IOPMP_WO) {
1636
+ entry.target_as = &s->blocked_r_as;
1637
+ } else {
1638
+ entry.target_as = &s->blocked_rw_as;
1639
+ }
1640
+ } else {
1641
+ if ((iopmp_perm & IOPMP_RW) == IOMMU_RW) {
1642
+ entry.target_as = &s->blocked_x_as;
1643
+ } else if ((iopmp_perm & IOPMP_RW) == IOPMP_RO) {
1644
+ entry.target_as = &s->blocked_wx_as;
1645
+ } else if ((iopmp_perm & IOPMP_RW) == IOPMP_WO) {
1646
+ entry.target_as = &s->blocked_rx_as;
1647
+ } else {
1648
+ entry.target_as = &s->blocked_rwx_as;
1649
+ }
1650
+ }
1651
+ entry.perm = IOMMU_RW;
1652
+ }
1653
+ } else {
1654
+ /* CPU access with IOMMU_NONE flag no_hit or par_hit */
1655
+ entry.target_as = &s->blocked_rwx_as;
1656
+ entry.perm = IOMMU_RW;
1657
+ }
1658
+ return entry;
1659
+}
1660
+
1661
+static const MemoryRegionOps iopmp_ops = {
1662
+ .read = iopmp_read,
1663
+ .write = iopmp_write,
1664
+ .endianness = DEVICE_NATIVE_ENDIAN,
1665
+ .valid = {.min_access_size = 4, .max_access_size = 4}
1666
+};
1667
+
1668
+static MemTxResult iopmp_permssion_write(void *opaque, hwaddr addr,
1669
+ uint64_t value, unsigned size,
1670
+ MemTxAttrs attrs)
1671
+{
1672
+ MemTxResult result;
1673
+ int rrid = attrs.requester_id;
1674
+ bool sent_info = false;
1675
+ riscv_iopmp_txn_info signal;
1676
+ RISCVIOPMPState *s = RISCV_IOPMP(opaque);
1677
+ if (s->rrid_transl_en) {
1678
+ if (s->transaction_state[rrid].running && s->send_ss) {
1679
+ sent_info = true;
1680
+ signal.rrid = s->rrid_transl;
1681
+ signal.start_addr = s->transaction_state[rrid].start_addr;
1682
+ signal.end_addr = s->transaction_state[rrid].end_addr;
1683
+ signal.stage = s->transaction_state[rrid].stage + 1;
1684
+ /* Send transaction information to next stage iopmp. */
1685
+ stream_push(s->send_ss, (uint8_t *)&signal, sizeof(signal), 0);
1686
+ }
1687
+ attrs.requester_id = s->rrid_transl;
1688
+ }
1689
+ result = address_space_write(&s->downstream_as, addr, attrs, &value, size);
1690
+ if (sent_info) {
1691
+ stream_push(s->send_ss, (uint8_t *)&signal, sizeof(signal), 1);
1692
+ }
1693
+ return result;
1694
+}
1695
+
1696
+static MemTxResult iopmp_permssion_read(void *opaque, hwaddr addr,
1697
+ uint64_t *pdata, unsigned size,
1698
+ MemTxAttrs attrs)
1699
+{
1700
+ MemTxResult result;
1701
+ int rrid = attrs.requester_id;
1702
+ bool sent_info = false;
1703
+ riscv_iopmp_txn_info signal;
1704
+ RISCVIOPMPState *s = RISCV_IOPMP(opaque);
1705
+ if (s->rrid_transl_en) {
1706
+ if (s->transaction_state[rrid].running && s->send_ss) {
1707
+ sent_info = true;
1708
+ signal.rrid = s->rrid_transl;
1709
+ signal.start_addr = s->transaction_state[rrid].start_addr;
1710
+ signal.end_addr = s->transaction_state[rrid].end_addr;
1711
+ signal.stage = s->transaction_state[rrid].stage + 1;
1712
+ /* Send transaction information to next stage iopmp. */
1713
+ stream_push(s->send_ss, (uint8_t *)&signal, sizeof(signal), 0);
1714
+ }
1715
+ attrs.requester_id = s->rrid_transl;
1716
+ }
1717
+ result = address_space_read(&s->downstream_as, addr, attrs, pdata, size);
1718
+ if (sent_info) {
1719
+ stream_push(s->send_ss, (uint8_t *)&signal, sizeof(signal), 1);
1720
+ }
1721
+ return result;
1722
+}
1723
+
1724
+static MemTxResult iopmp_handle_block(void *opaque, hwaddr addr,
1725
+ uint64_t *data, unsigned size,
1726
+ MemTxAttrs attrs,
1727
+ iopmp_access_type access_type)
1728
+{
1729
+ RISCVIOPMPState *s = RISCV_IOPMP(opaque);
1730
+ int entry_idx;
1731
+ int rrid = attrs.requester_id;
1732
+ int result;
1733
+ hwaddr start_addr, end_addr;
1734
+ iopmp_err_info_etype etype;
1735
+ iopmp_err_info_ttype ttype;
1736
+ ttype = access_type;
1737
+ hwaddr iopmp_tlb_size = TARGET_PAGE_SIZE;
1738
+ int match_cfg = 0;
1739
+ /* unknown RRID */
1740
+ if (rrid >= s->rrid_num) {
1741
+ etype = ERR_INFO_ETYPE_RRID;
1742
+ return iopmp_error_reaction(s, rrid, 0, addr, etype, ttype, 0, data);
1743
+ }
1744
+
1745
+ if (s->is_stalled && s->rrid_stall[rrid]) {
1746
+ etype = ERR_INFO_ETYPE_STALL;
1747
+ return iopmp_error_reaction(s, rrid, 0, addr, etype, ttype, 0, data);
1748
+ }
1749
+
1750
+ if ((access_type == IOPMP_ACCESS_FETCH && s->no_x) ||
1751
+ (access_type == IOPMP_ACCESS_WRITE && s->no_w)) {
1752
+ etype = ERR_INFO_ETYPE_NOHIT;
1753
+ return iopmp_error_reaction(s, rrid, 0, addr, etype, ttype, 0, data);
1754
+ }
1755
+
1756
+ if (s->transaction_state[rrid].running == true) {
1757
+ start_addr = s->transaction_state[rrid].start_addr;
1758
+ end_addr = s->transaction_state[rrid].end_addr;
1759
+ } else {
1760
+ /* No transaction information, use the same address */
1761
+ start_addr = addr;
1762
+ end_addr = addr;
1763
+ }
1764
+
1765
+ /* matching again to get eid */
1766
+ result = match_entry_srcmd(s, rrid, start_addr, end_addr,
1767
+ &entry_idx, &match_cfg,
1768
+ &iopmp_tlb_size);
1769
+ if (result == IOPMP_ENTRY_HIT) {
1770
+ etype = access_type;
1771
+ } else if (result == IOPMP_ENTRY_PAR_HIT) {
1772
+ etype = ERR_INFO_ETYPE_PARHIT;
1773
+ /* error supperssion per entry is only for all-byte matched entry */
1774
+ } else {
1775
+ etype = ERR_INFO_ETYPE_NOHIT;
1776
+ entry_idx = 0;
1777
+ }
1778
+ return iopmp_error_reaction(s, rrid, entry_idx, start_addr, etype, ttype,
1779
+ match_cfg, data);
1780
+}
1781
+
1782
+static MemTxResult iopmp_block_write(void *opaque, hwaddr addr, uint64_t value,
1783
+ unsigned size, MemTxAttrs attrs)
1784
+{
1785
+ return iopmp_handle_block(opaque, addr, NULL, size, attrs,
1786
+ IOPMP_ACCESS_WRITE);
1787
+}
1788
+
1789
+static MemTxResult iopmp_block_read(void *opaque, hwaddr addr, uint64_t *pdata,
1790
+ unsigned size, MemTxAttrs attrs)
1791
+{
1792
+ return iopmp_handle_block(opaque, addr, pdata, size, attrs,
1793
+ IOPMP_ACCESS_READ);
1794
+}
1795
+
1796
+static MemTxResult iopmp_block_fetch(void *opaque, hwaddr addr, uint64_t *pdata,
1797
+ unsigned size, MemTxAttrs attrs)
1798
+{
1799
+ RISCVIOPMPState *s = RISCV_IOPMP(opaque);
1800
+ if (s->chk_x) {
1801
+ return iopmp_handle_block(opaque, addr, pdata, size, attrs,
1802
+ IOPMP_ACCESS_FETCH);
1803
+ }
1804
+ /* Using read reaction for no chk_x */
1805
+ return iopmp_handle_block(opaque, addr, pdata, size, attrs,
1806
+ IOPMP_ACCESS_READ);
1807
+}
1808
+
1809
+static const MemoryRegionOps iopmp_block_rw_ops = {
1810
+ .fetch_with_attrs = iopmp_permssion_read,
1811
+ .read_with_attrs = iopmp_block_read,
1812
+ .write_with_attrs = iopmp_block_write,
1813
+ .endianness = DEVICE_NATIVE_ENDIAN,
1814
+ .valid = {.min_access_size = 1, .max_access_size = 8},
1815
+};
1816
+
1817
+static const MemoryRegionOps iopmp_block_w_ops = {
1818
+ .fetch_with_attrs = iopmp_permssion_read,
1819
+ .read_with_attrs = iopmp_permssion_read,
1820
+ .write_with_attrs = iopmp_block_write,
1821
+ .endianness = DEVICE_NATIVE_ENDIAN,
1822
+ .valid = {.min_access_size = 1, .max_access_size = 8},
1823
+};
1824
+
1825
+static const MemoryRegionOps iopmp_block_r_ops = {
1826
+ .fetch_with_attrs = iopmp_permssion_read,
1827
+ .read_with_attrs = iopmp_block_read,
1828
+ .write_with_attrs = iopmp_permssion_write,
1829
+ .endianness = DEVICE_NATIVE_ENDIAN,
1830
+ .valid = {.min_access_size = 1, .max_access_size = 8},
1831
+};
1832
+
1833
+static const MemoryRegionOps iopmp_block_rwx_ops = {
1834
+ .fetch_with_attrs = iopmp_block_fetch,
1835
+ .read_with_attrs = iopmp_block_read,
1836
+ .write_with_attrs = iopmp_block_write,
1837
+ .endianness = DEVICE_NATIVE_ENDIAN,
1838
+ .valid = {.min_access_size = 1, .max_access_size = 8},
1839
+};
1840
+
1841
+static const MemoryRegionOps iopmp_block_wx_ops = {
1842
+ .fetch_with_attrs = iopmp_block_fetch,
1843
+ .read_with_attrs = iopmp_permssion_read,
1844
+ .write_with_attrs = iopmp_block_write,
1845
+ .endianness = DEVICE_NATIVE_ENDIAN,
1846
+ .valid = {.min_access_size = 1, .max_access_size = 8},
1847
+};
1848
+
1849
+static const MemoryRegionOps iopmp_block_rx_ops = {
1850
+ .fetch_with_attrs = iopmp_block_fetch,
1851
+ .read_with_attrs = iopmp_block_read,
1852
+ .write_with_attrs = iopmp_permssion_write,
1853
+ .endianness = DEVICE_NATIVE_ENDIAN,
1854
+ .valid = {.min_access_size = 1, .max_access_size = 8},
1855
+};
1856
+
1857
+static const MemoryRegionOps iopmp_block_x_ops = {
1858
+ .fetch_with_attrs = iopmp_block_fetch,
1859
+ .read_with_attrs = iopmp_permssion_read,
1860
+ .write_with_attrs = iopmp_permssion_write,
1861
+ .endianness = DEVICE_NATIVE_ENDIAN,
1862
+ .valid = {.min_access_size = 1, .max_access_size = 8},
1863
+};
1864
+
1865
+static const MemoryRegionOps iopmp_full_ops = {
1866
+ .fetch_with_attrs = iopmp_permssion_read,
1867
+ .read_with_attrs = iopmp_permssion_read,
1868
+ .write_with_attrs = iopmp_permssion_write,
1869
+ .endianness = DEVICE_NATIVE_ENDIAN,
1870
+ .valid = {.min_access_size = 1, .max_access_size = 8},
1871
+};
1872
+
1873
+static void iopmp_realize(DeviceState *dev, Error **errp)
1874
+{
1875
+ Object *obj = OBJECT(dev);
1876
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
1877
+ RISCVIOPMPState *s = RISCV_IOPMP(dev);
1878
+ uint64_t size;
1879
+
1880
+ size = -1ULL;
1881
+
1882
+ if (s->srcmd_fmt > 2) {
1883
+ error_setg(errp, "Invalid IOPMP srcmd_fmt");
1884
+ error_append_hint(errp, "Valid values are 0, 1, and 2.\n");
1885
+ return;
1886
+ }
1887
+
1888
+ if (s->mdcfg_fmt > 2) {
1889
+ error_setg(errp, "Invalid IOPMP mdcfg_fmt");
1890
+ error_append_hint(errp, "Valid values are 0, 1, and 2.\n");
1891
+ return;
1892
+ }
1893
+
1894
+ if (s->srcmd_fmt != 0) {
1895
+ /* SPS is only supported in srcmd_fmt0 */
1896
+ s->sps_en = false;
1897
+ }
1898
+
1899
+ s->md_num = MIN(s->md_num, IOPMP_MAX_MD_NUM);
1900
+ if (s->srcmd_fmt == 1) {
1901
+ /* Each RRID has one MD */
1902
+ s->md_num = MIN(s->md_num, s->rrid_num);
1903
+ }
1904
+ s->md_entry_num = s->default_md_entry_num;
1905
+ /* If md_entry_num is fixed, entry_num = md_num * (md_entry_num + 1)*/
1906
+ if (s->mdcfg_fmt == 1) {
1907
+ s->entry_num = s->md_num * (s->md_entry_num + 1);
1908
+ }
1909
+
1910
+ s->prient_prog = s->default_prient_prog;
1911
+ if (s->srcmd_fmt == 0) {
1912
+ s->rrid_num = MIN(s->rrid_num, IOPMP_SRCMDFMT0_MAX_RRID_NUM);
1913
+ } else if (s->srcmd_fmt == 1) {
1914
+ s->rrid_num = MIN(s->rrid_num, s->md_num);
1915
+ } else {
1916
+ s->rrid_num = MIN(s->rrid_num, IOPMP_SRCMDFMT2_MAX_RRID_NUM);
1917
+ }
1918
+ s->prio_entry = MIN(s->default_prio_entry, s->entry_num);
1919
+ s->rrid_transl_prog = s->default_rrid_transl_prog;
1920
+ s->rrid_transl = s->default_rrid_transl;
1921
+
1922
+ s->regs.err_cfg = FIELD_DP32(s->regs.err_cfg, ERR_CFG, MSI_EN,
1923
+ s->default_msi_en);
1924
+ s->regs.err_cfg = FIELD_DP32(s->regs.err_cfg, ERR_CFG, MSIDATA,
1925
+ s->default_msidata);
1926
+ s->regs.err_msiaddr = s->default_err_msiaddr;
1927
+ s->regs.err_msiaddrh = s->default_err_msiaddrh;
1928
+
1929
+ s->regs.mdcfg = g_malloc0(s->md_num * sizeof(uint32_t));
1930
+ if (s->srcmd_fmt != 2) {
1931
+ s->regs.srcmd_en = g_malloc0(s->rrid_num * sizeof(uint32_t));
1932
+ s->regs.srcmd_enh = g_malloc0(s->rrid_num * sizeof(uint32_t));
1933
+ } else {
1934
+ /* srcmd_perm */
1935
+ s->regs.srcmd_perm = g_malloc0(s->md_num * sizeof(uint32_t));
1936
+ s->regs.srcmd_permh = g_malloc0(s->md_num * sizeof(uint32_t));
1937
+ }
1938
+
1939
+ if (s->sps_en) {
1940
+ s->regs.srcmd_r = g_malloc0(s->rrid_num * sizeof(uint32_t));
1941
+ s->regs.srcmd_rh = g_malloc0(s->rrid_num * sizeof(uint32_t));
1942
+ s->regs.srcmd_w = g_malloc0(s->rrid_num * sizeof(uint32_t));
1943
+ s->regs.srcmd_wh = g_malloc0(s->rrid_num * sizeof(uint32_t));
1944
+ }
1945
+
1946
+ if (s->stall_en) {
1947
+ s->rrid_stall = g_malloc0(s->rrid_num * sizeof(bool));
1948
+ }
1949
+
1950
+ if (s->mfr_en) {
1951
+ s->svw = g_malloc0((s->rrid_num / 16 + 1) * sizeof(uint16_t));
1952
+ }
1953
+
1954
+ s->regs.entry = g_malloc0(s->entry_num * sizeof(riscv_iopmp_entry_t));
1955
+ s->entry_addr = g_malloc0(s->entry_num * sizeof(riscv_iopmp_addr_t));
1956
+ s->transaction_state = g_malloc0(s->rrid_num *
1957
+ sizeof(riscv_iopmp_transaction_state));
1958
+ qemu_mutex_init(&s->iopmp_transaction_mutex);
1959
+
1960
+ memory_region_init_iommu(&s->iommu, sizeof(s->iommu),
1961
+ TYPE_RISCV_IOPMP_IOMMU_MEMORY_REGION,
1962
+ obj, "riscv-iopmp-sysbus-iommu", UINT64_MAX);
1963
+ memory_region_init_io(&s->mmio, obj, &iopmp_ops,
1964
+ s, "riscv-iopmp-regs", 0x100000);
1965
+ sysbus_init_mmio(sbd, &s->mmio);
1966
+
1967
+ memory_region_init_io(&s->blocked_rw, NULL, &iopmp_block_rw_ops, s,
1968
+ "riscv-iopmp-blocked-rw", size);
1969
+ memory_region_init_io(&s->blocked_w, NULL, &iopmp_block_w_ops, s,
1970
+ "riscv-iopmp-blocked-w", size);
1971
+ memory_region_init_io(&s->blocked_r, NULL, &iopmp_block_r_ops, s,
1972
+ "riscv-iopmp-blocked-r", size);
1973
+ memory_region_init_io(&s->blocked_rwx, NULL, &iopmp_block_rwx_ops, s,
1974
+ "riscv-iopmp-blocked-rwx", size);
1975
+ memory_region_init_io(&s->blocked_wx, NULL, &iopmp_block_wx_ops, s,
1976
+ "riscv-iopmp-blocked-wx", size);
1977
+ memory_region_init_io(&s->blocked_rx, NULL, &iopmp_block_rx_ops, s,
1978
+ "riscv-iopmp-blocked-rx", size);
1979
+ memory_region_init_io(&s->blocked_x, NULL, &iopmp_block_x_ops, s,
1980
+ "riscv-iopmp-blocked-x", size);
1981
+ memory_region_init_io(&s->full_mr, NULL, &iopmp_full_ops, s,
1982
+ "riscv-iopmp-full", size);
1983
+
1984
+ address_space_init(&s->blocked_rw_as, &s->blocked_rw,
1985
+ "riscv-iopmp-blocked-rw-as");
1986
+ address_space_init(&s->blocked_w_as, &s->blocked_w,
1987
+ "riscv-iopmp-blocked-w-as");
1988
+ address_space_init(&s->blocked_r_as, &s->blocked_r,
1989
+ "riscv-iopmp-blocked-r-as");
1990
+ address_space_init(&s->blocked_rwx_as, &s->blocked_rwx,
1991
+ "riscv-iopmp-blocked-rwx-as");
1992
+ address_space_init(&s->blocked_wx_as, &s->blocked_wx,
1993
+ "riscv-iopmp-blocked-wx-as");
1994
+ address_space_init(&s->blocked_rx_as, &s->blocked_rx,
1995
+ "riscv-iopmp-blocked-rx-as");
1996
+ address_space_init(&s->blocked_x_as, &s->blocked_x,
1997
+ "riscv-iopmp-blocked-x-as");
1998
+ address_space_init(&s->full_as, &s->full_mr, "riscv-iopmp-full-as");
1999
+
2000
+ object_initialize_child(OBJECT(s), "riscv_iopmp_streamsink",
2001
+ &s->txn_info_sink,
2002
+ TYPE_RISCV_IOPMP_STREAMSINK);
2003
+}
2004
+
2005
+static void iopmp_reset_enter(Object *obj, ResetType type)
2006
+{
2007
+ RISCVIOPMPState *s = RISCV_IOPMP(obj);
2008
+
2009
+ qemu_set_irq(s->irq, 0);
2010
+ if (s->srcmd_fmt != 2) {
2011
+ memset(s->regs.srcmd_en, 0, s->rrid_num * sizeof(uint32_t));
2012
+ memset(s->regs.srcmd_enh, 0, s->rrid_num * sizeof(uint32_t));
2013
+ } else {
2014
+ memset(s->regs.srcmd_en, 0, s->md_num * sizeof(uint32_t));
2015
+ memset(s->regs.srcmd_enh, 0, s->md_num * sizeof(uint32_t));
2016
+ }
2017
+
2018
+ if (s->sps_en) {
2019
+ memset(s->regs.srcmd_r, 0, s->rrid_num * sizeof(uint32_t));
2020
+ memset(s->regs.srcmd_rh, 0, s->rrid_num * sizeof(uint32_t));
2021
+ memset(s->regs.srcmd_w, 0, s->rrid_num * sizeof(uint32_t));
2022
+ memset(s->regs.srcmd_wh, 0, s->rrid_num * sizeof(uint32_t));
2023
+ }
2024
+
2025
+ if (s->stall_en) {
2026
+ memset((void *)s->rrid_stall, 0, s->rrid_num * sizeof(bool));
2027
+ s->is_stalled = 0;
2028
+ }
2029
+
2030
+ if (s->mfr_en) {
2031
+ memset(s->svw, 0, (s->rrid_num / 16 + 1) * sizeof(uint16_t));
2032
+ }
2033
+
2034
+ memset(s->regs.entry, 0, s->entry_num * sizeof(riscv_iopmp_entry_t));
2035
+ memset(s->entry_addr, 0, s->entry_num * sizeof(riscv_iopmp_addr_t));
2036
+ memset(s->transaction_state, 0,
2037
+ s->rrid_num * sizeof(riscv_iopmp_transaction_state));
2038
+
2039
+ s->regs.mdlck = 0;
2040
+ s->regs.mdlckh = 0;
2041
+ s->regs.entrylck = 0;
2042
+ s->regs.mdcfglck = 0;
2043
+ s->regs.mdstall = 0;
2044
+ s->regs.mdstallh = 0;
2045
+ s->regs.rridscp = 0;
2046
+ s->regs.err_cfg = 0;
2047
+ s->regs.err_reqaddr = 0;
2048
+ s->regs.err_reqid = 0;
2049
+ s->regs.err_info = 0;
2050
+
2051
+ s->prient_prog = s->default_prient_prog;
2052
+ s->rrid_transl_prog = s->default_rrid_transl_prog;
2053
+ s->md_entry_num = s->default_md_entry_num;
2054
+ s->rrid_transl = s->default_rrid_transl;
2055
+ s->prio_entry = MIN(s->default_prio_entry, s->entry_num);
2056
+ s->regs.err_cfg = FIELD_DP32(s->regs.err_cfg, ERR_CFG, MSI_EN,
2057
+ s->default_msi_en);
2058
+ s->regs.err_cfg = FIELD_DP32(s->regs.err_cfg, ERR_CFG, STALL_VIOLATION_EN,
2059
+ s->default_stall_violation_en);
2060
+ s->regs.err_cfg = FIELD_DP32(s->regs.err_cfg, ERR_CFG, MSIDATA,
2061
+ s->default_msidata);
2062
+ s->regs.err_msiaddr = s->default_err_msiaddr;
2063
+ s->regs.err_msiaddrh = s->default_err_msiaddrh;
2064
+ s->enable = 0;
2065
+}
2066
+
2067
+static void iopmp_reset_hold(Object *obj, ResetType type)
2068
+{
2069
+ RISCVIOPMPState *s = RISCV_IOPMP(obj);
2070
+
2071
+ qemu_set_irq(s->irq, 0);
2072
+}
2073
+
2074
+static int iopmp_attrs_to_index(IOMMUMemoryRegion *iommu, MemTxAttrs attrs)
2075
+{
2076
+ return attrs.requester_id;
2077
+}
2078
+
2079
+static void iopmp_iommu_memory_region_class_init(ObjectClass *klass, void *data)
2080
+{
2081
+ IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass);
2082
+
2083
+ imrc->translate = iopmp_translate;
2084
+ imrc->attrs_to_index = iopmp_attrs_to_index;
2085
+}
2086
+
2087
+static const Property iopmp_property[] = {
2088
+ DEFINE_PROP_UINT32("mdcfg_fmt", RISCVIOPMPState, mdcfg_fmt, 1),
2089
+ DEFINE_PROP_UINT32("srcmd_fmt", RISCVIOPMPState, srcmd_fmt, 0),
2090
+ DEFINE_PROP_BOOL("tor_en", RISCVIOPMPState, tor_en, true),
2091
+ DEFINE_PROP_BOOL("sps_en", RISCVIOPMPState, sps_en, false),
2092
+ DEFINE_PROP_BOOL("prient_prog", RISCVIOPMPState, default_prient_prog, true),
2093
+ DEFINE_PROP_BOOL("rrid_transl_en", RISCVIOPMPState, rrid_transl_en, false),
2094
+ DEFINE_PROP_BOOL("rrid_transl_prog", RISCVIOPMPState,
2095
+ default_rrid_transl_prog, false),
2096
+ DEFINE_PROP_BOOL("chk_x", RISCVIOPMPState, chk_x, true),
2097
+ DEFINE_PROP_BOOL("no_x", RISCVIOPMPState, no_x, false),
2098
+ DEFINE_PROP_BOOL("no_w", RISCVIOPMPState, no_w, false),
2099
+ DEFINE_PROP_BOOL("stall_en", RISCVIOPMPState, stall_en, false),
2100
+ DEFINE_PROP_BOOL("peis", RISCVIOPMPState, peis, true),
2101
+ DEFINE_PROP_BOOL("pees", RISCVIOPMPState, pees, true),
2102
+ DEFINE_PROP_BOOL("mfr_en", RISCVIOPMPState, mfr_en, true),
2103
+ DEFINE_PROP_UINT32("md_entry_num", RISCVIOPMPState, default_md_entry_num,
2104
+ 5),
2105
+ DEFINE_PROP_UINT32("md_num", RISCVIOPMPState, md_num, 8),
2106
+ DEFINE_PROP_UINT32("rrid_num", RISCVIOPMPState, rrid_num, 16),
2107
+ DEFINE_PROP_UINT32("entry_num", RISCVIOPMPState, entry_num, 48),
2108
+ DEFINE_PROP_UINT32("prio_entry", RISCVIOPMPState, default_prio_entry,
2109
+ 65535),
2110
+ DEFINE_PROP_UINT32("rrid_transl", RISCVIOPMPState, default_rrid_transl,
2111
+ 0x0),
2112
+ DEFINE_PROP_INT32("entry_offset", RISCVIOPMPState, entry_offset, 0x4000),
2113
+ DEFINE_PROP_UINT32("err_rdata", RISCVIOPMPState, err_rdata, 0x0),
2114
+ DEFINE_PROP_BOOL("msi_en", RISCVIOPMPState, default_msi_en, false),
2115
+ DEFINE_PROP_UINT32("msidata", RISCVIOPMPState, default_msidata, 12),
2116
+ DEFINE_PROP_BOOL("stall_violation_en", RISCVIOPMPState,
2117
+ default_stall_violation_en, true),
2118
+ DEFINE_PROP_UINT32("err_msiaddr", RISCVIOPMPState, default_err_msiaddr,
2119
+ 0x24000000),
2120
+ DEFINE_PROP_UINT32("err_msiaddrh", RISCVIOPMPState, default_err_msiaddrh,
2121
+ 0x0),
2122
+ DEFINE_PROP_UINT32("msi_rrid", RISCVIOPMPState, msi_rrid, 0),
2123
+};
2124
+
2125
+static void iopmp_class_init(ObjectClass *klass, void *data)
2126
+{
2127
+ DeviceClass *dc = DEVICE_CLASS(klass);
2128
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
2129
+ device_class_set_props(dc, iopmp_property);
2130
+ dc->realize = iopmp_realize;
2131
+ rc->phases.enter = iopmp_reset_enter;
2132
+ rc->phases.hold = iopmp_reset_hold;
2133
+}
2134
+
2135
+static void iopmp_init(Object *obj)
2136
+{
2137
+ RISCVIOPMPState *s = RISCV_IOPMP(obj);
2138
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
2139
+
2140
+ sysbus_init_irq(sbd, &s->irq);
2141
+}
2142
+
2143
+static const TypeInfo iopmp_info = {
2144
+ .name = TYPE_RISCV_IOPMP,
2145
+ .parent = TYPE_SYS_BUS_DEVICE,
2146
+ .instance_size = sizeof(RISCVIOPMPState),
2147
+ .instance_init = iopmp_init,
2148
+ .class_init = iopmp_class_init,
2149
+};
2150
+
2151
+static const TypeInfo iopmp_iommu_memory_region_info = {
2152
+ .name = TYPE_RISCV_IOPMP_IOMMU_MEMORY_REGION,
2153
+ .parent = TYPE_IOMMU_MEMORY_REGION,
2154
+ .class_init = iopmp_iommu_memory_region_class_init,
2155
+};
2156
+
2157
+DeviceState *iopmp_create(hwaddr addr, qemu_irq irq)
2158
+{
2159
+ DeviceState *dev = qdev_new(TYPE_RISCV_IOPMP);
2160
+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq);
2161
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
2162
+ sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
2163
+ return dev;
2164
+}
2165
+
2166
+/*
2167
+ * Alias subregions from the source memory region to the destination memory
2168
+ * region
2169
+ */
2170
+static void alias_memory_subregions(MemoryRegion *src_mr, MemoryRegion *dst_mr)
2171
+{
2172
+ int32_t priority;
2173
+ hwaddr addr;
2174
+ MemoryRegion *alias, *subregion;
2175
+ QTAILQ_FOREACH(subregion, &src_mr->subregions, subregions_link) {
2176
+ priority = subregion->priority;
2177
+ addr = subregion->addr;
2178
+ alias = g_malloc0(sizeof(MemoryRegion));
2179
+ memory_region_init_alias(alias, NULL, subregion->name, subregion, 0,
2180
+ memory_region_size(subregion));
2181
+ memory_region_add_subregion_overlap(dst_mr, addr, alias, priority);
2182
+ }
2183
+}
2184
+
2185
+/*
2186
+ * Create downstream of system memory for IOPMP, and overlap memory region
2187
+ * specified in memmap with IOPMP translator. Make sure subregions are added to
2188
+ * system memory before call this function. It also add entry to
2189
+ * iopmp_protection_memmaps for recording the relationship between physical
2190
+ * address regions and IOPMP.
2191
+ */
2192
+void iopmp_setup_system_memory(DeviceState *dev, const MemMapEntry *memmap,
2193
+ uint32_t map_entry_num, uint32_t stage)
2194
+{
2195
+ RISCVIOPMPState *s = RISCV_IOPMP(dev);
2196
+ uint32_t i;
2197
+ MemoryRegion *iommu_alias;
2198
+ MemoryRegion *target_mr = get_system_memory();
2199
+ MemoryRegion *downstream = g_malloc0(sizeof(MemoryRegion));
2200
+ memory_region_init(downstream, NULL, "iopmp_downstream",
2201
+ memory_region_size(target_mr));
2202
+ /* Create a downstream which does not have iommu of iopmp */
2203
+ alias_memory_subregions(target_mr, downstream);
2204
+
2205
+ for (i = 0; i < map_entry_num; i++) {
2206
+ /* Memory access to protected regions of target are through IOPMP */
2207
+ iommu_alias = g_new(MemoryRegion, 1);
2208
+ memory_region_init_alias(iommu_alias, NULL, "iommu_alias",
2209
+ MEMORY_REGION(&s->iommu), memmap[i].base,
2210
+ memmap[i].size);
2211
+ memory_region_add_subregion_overlap(target_mr, memmap[i].base,
2212
+ iommu_alias, 1);
2213
+ }
2214
+ s->downstream = downstream;
2215
+ address_space_init(&s->downstream_as, s->downstream,
2216
+ "riscv-iopmp-downstream-as");
2217
+}
2218
+
2219
+static size_t txn_info_push(StreamSink *txn_info_sink, unsigned char *buf,
2220
+ size_t len, bool eop)
2221
+{
2222
+ riscv_iopmp_streamsink *ss = RISCV_IOPMP_STREAMSINK(txn_info_sink);
2223
+ RISCVIOPMPState *s = RISCV_IOPMP(container_of(ss, RISCVIOPMPState,
2224
+ txn_info_sink));
2225
+ riscv_iopmp_txn_info signal;
2226
+ uint32_t rrid;
2227
+
2228
+ memcpy(&signal, buf, len);
2229
+ rrid = signal.rrid;
2230
+
2231
+ if (s->transaction_state[rrid].running) {
2232
+ if (eop) {
2233
+ /* Finish the transaction */
2234
+ qemu_mutex_lock(&s->iopmp_transaction_mutex);
2235
+ s->transaction_state[rrid].running = 0;
2236
+ qemu_mutex_unlock(&s->iopmp_transaction_mutex);
2237
+ return 1;
2238
+ } else {
2239
+ /* Transaction is already running */
2240
+ return 0;
2241
+ }
2242
+ } else if (len == sizeof(riscv_iopmp_txn_info)) {
2243
+ /* Get the transaction info */
2244
+ s->transaction_state[rrid].supported = 1;
2245
+ qemu_mutex_lock(&s->iopmp_transaction_mutex);
2246
+ s->transaction_state[rrid].running = 1;
2247
+ qemu_mutex_unlock(&s->iopmp_transaction_mutex);
2248
+
2249
+ s->transaction_state[rrid].start_addr = signal.start_addr;
2250
+ s->transaction_state[rrid].end_addr = signal.end_addr;
2251
+ s->transaction_state[rrid].error_reported = 0;
2252
+ s->transaction_state[rrid].stage = signal.stage;
2253
+ return 1;
2254
+ }
2255
+ return 0;
2256
+}
2257
+
2258
+void iopmp_setup_sink(DeviceState *dev, StreamSink * ss)
2259
+{
2260
+ RISCVIOPMPState *s = RISCV_IOPMP(dev);
2261
+ s->send_ss = ss;
2262
+}
2263
+
2264
+static void riscv_iopmp_streamsink_class_init(ObjectClass *klass, void *data)
2265
+{
2266
+ StreamSinkClass *ssc = STREAM_SINK_CLASS(klass);
2267
+ ssc->push = txn_info_push;
2268
+}
2269
+
2270
+static const TypeInfo txn_info_sink = {
2271
+ .name = TYPE_RISCV_IOPMP_STREAMSINK,
2272
+ .parent = TYPE_OBJECT,
2273
+ .instance_size = sizeof(riscv_iopmp_streamsink),
2274
+ .class_init = riscv_iopmp_streamsink_class_init,
2275
+ .interfaces = (InterfaceInfo[]) {
2276
+ { TYPE_STREAM_SINK },
2277
+ { }
2278
+ },
2279
+};
2280
+
2281
+static void iopmp_register_types(void)
2282
+{
2283
+ type_register_static(&iopmp_info);
2284
+ type_register_static(&txn_info_sink);
2285
+ type_register_static(&iopmp_iommu_memory_region_info);
2286
+}
2287
+
2288
+type_init(iopmp_register_types);
2289
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
2290
index XXXXXXX..XXXXXXX 100644
2291
--- a/hw/misc/trace-events
2292
+++ b/hw/misc/trace-events
2293
@@ -XXX,XX +XXX,XX @@ ivshmem_flat_read_write_mmr_invalid(uint64_t addr_offset) "No ivshmem register m
2294
ivshmem_flat_interrupt_invalid_peer(uint16_t peer_id) "Can't interrupt non-existing peer %u"
2295
ivshmem_flat_write_mmr(uint64_t addr_offset) "Write access at offset %"PRIu64
2296
ivshmem_flat_interrupt_peer(uint16_t peer_id, uint16_t vector_id) "Interrupting peer ID %u, vector %u..."
2297
+
2298
+# riscv_iopmp.c
2299
+iopmp_read(uint64_t addr, uint32_t val) "addr 0x%"PRIx64" val 0x%x"
2300
+iopmp_write(uint64_t addr, uint32_t val) "addr 0x%"PRIx64" val 0x%x"
2301
diff --git a/include/hw/misc/riscv_iopmp.h b/include/hw/misc/riscv_iopmp.h
2302
new file mode 100644
2303
index XXXXXXX..XXXXXXX
2304
--- /dev/null
2305
+++ b/include/hw/misc/riscv_iopmp.h
2306
@@ -XXX,XX +XXX,XX @@
2307
+/*
2308
+ * QEMU RISC-V IOPMP (Input Output Physical Memory Protection)
2309
+ *
2310
+ * Copyright (c) 2023-2025 Andes Tech. Corp.
2311
+ *
2312
+ * SPDX-License-Identifier: GPL-2.0-or-later
2313
+ *
2314
+ * This program is free software; you can redistribute it and/or modify it
2315
+ * under the terms and conditions of the GNU General Public License,
2316
+ * version 2 or later, as published by the Free Software Foundation.
2317
+ *
2318
+ * This program is distributed in the hope it will be useful, but WITHOUT
2319
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
2320
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
2321
+ * more details.
2322
+ *
2323
+ * You should have received a copy of the GNU General Public License along with
2324
+ * this program. If not, see <http://www.gnu.org/licenses/>.
2325
+ */
2326
+
2327
+#ifndef RISCV_IOPMP_H
2328
+#define RISCV_IOPMP_H
2329
+
2330
+#include "hw/sysbus.h"
2331
+#include "qemu/typedefs.h"
2332
+#include "memory.h"
2333
+#include "exec/hwaddr.h"
2334
+#include "hw/stream.h"
2335
+
2336
+#define TYPE_RISCV_IOPMP "riscv-iopmp"
2337
+OBJECT_DECLARE_SIMPLE_TYPE(RISCVIOPMPState, RISCV_IOPMP)
2338
+
2339
+typedef struct riscv_iopmp_streamsink {
2340
+ Object parent;
2341
+} riscv_iopmp_streamsink;
2342
+#define TYPE_RISCV_IOPMP_STREAMSINK \
2343
+ "riscv-iopmp-streamsink"
2344
+DECLARE_INSTANCE_CHECKER(riscv_iopmp_streamsink, RISCV_IOPMP_STREAMSINK,
2345
+ TYPE_RISCV_IOPMP_STREAMSINK)
2346
+typedef struct {
2347
+ uint32_t addr_reg;
2348
+ uint32_t addrh_reg;
2349
+ uint32_t cfg_reg;
2350
+} riscv_iopmp_entry_t;
2351
+
2352
+typedef struct {
2353
+ uint64_t sa;
2354
+ uint64_t ea;
2355
+} riscv_iopmp_addr_t;
2356
+
2357
+typedef struct {
2358
+ union {
2359
+ uint32_t *srcmd_en;
2360
+ uint32_t *srcmd_perm;
2361
+ };
2362
+ union {
2363
+ uint32_t *srcmd_enh;
2364
+ uint32_t *srcmd_permh;
2365
+ };
2366
+ uint32_t *srcmd_r;
2367
+ uint32_t *srcmd_rh;
2368
+ uint32_t *srcmd_w;
2369
+ uint32_t *srcmd_wh;
2370
+ uint32_t *mdcfg;
2371
+ riscv_iopmp_entry_t *entry;
2372
+ uint32_t mdlck;
2373
+ uint32_t mdlckh;
2374
+ uint32_t entrylck;
2375
+ uint32_t mdcfglck;
2376
+ uint32_t mdstall;
2377
+ uint32_t mdstallh;
2378
+ uint32_t rridscp;
2379
+ uint32_t err_cfg;
2380
+ uint64_t err_reqaddr;
2381
+ uint32_t err_reqid;
2382
+ uint32_t err_info;
2383
+ uint32_t err_msiaddr;
2384
+ uint32_t err_msiaddrh;
2385
+} riscv_iopmp_regs;
2386
+
2387
+/* To detect partially hit */
2388
+typedef struct riscv_iopmp_transaction_state {
2389
+ bool running;
2390
+ bool error_reported;
2391
+ bool supported;
2392
+ uint32_t stage;
2393
+ hwaddr start_addr;
2394
+ hwaddr end_addr;
2395
+} riscv_iopmp_transaction_state;
2396
+
2397
+typedef struct RISCVIOPMPState {
2398
+ SysBusDevice parent_obj;
2399
+ riscv_iopmp_addr_t *entry_addr;
2400
+ MemoryRegion mmio;
2401
+ IOMMUMemoryRegion iommu;
2402
+ riscv_iopmp_regs regs;
2403
+ MemoryRegion *downstream;
2404
+ MemoryRegion blocked_r, blocked_w, blocked_x, blocked_rw, blocked_rx,
2405
+ blocked_wx, blocked_rwx;
2406
+ MemoryRegion full_mr;
2407
+
2408
+ AddressSpace downstream_as;
2409
+ AddressSpace blocked_r_as, blocked_w_as, blocked_x_as, blocked_rw_as,
2410
+ blocked_rx_as, blocked_wx_as, blocked_rwx_as;
2411
+ AddressSpace full_as;
2412
+ qemu_irq irq;
2413
+
2414
+ /* Transaction(txn) information to identify whole transaction length */
2415
+ /* Receive txn info */
2416
+ riscv_iopmp_streamsink txn_info_sink;
2417
+ /* Send txn info for next stage iopmp */
2418
+ StreamSink *send_ss;
2419
+ riscv_iopmp_transaction_state *transaction_state;
2420
+ QemuMutex iopmp_transaction_mutex;
2421
+
2422
+ /*
2423
+ * Stall:
2424
+ * a while loop to check stall flags if stall_violation is not enabled
2425
+ */
2426
+ volatile bool is_stalled;
2427
+ volatile bool *rrid_stall;
2428
+
2429
+ /* MFR extenstion */
2430
+ uint16_t *svw;
2431
+ uint16_t svi;
2432
+
2433
+ /* Properties */
2434
+ /*
2435
+ * MDCFG Format 0: MDCFG table is implemented
2436
+ * 1: HWCFG.md_entry_num is fixed
2437
+ * 2: HWCFG.md_entry_num is programmable
2438
+ */
2439
+ uint32_t mdcfg_fmt;
2440
+ /*
2441
+ * SRCMD Format 0: SRCMD_EN is implemented
2442
+ * 1: 1 to 1 SRCMD mapping
2443
+ * 2: SRCMD_PERM is implemented
2444
+ */
2445
+ uint32_t srcmd_fmt;
2446
+ bool tor_en;
2447
+ /* SPS is only supported srcmd_fmt0 */
2448
+ bool sps_en;
2449
+ /* Indicate prio_entry is programmable or not */
2450
+ bool default_prient_prog;
2451
+ bool rrid_transl_en;
2452
+ bool default_rrid_transl_prog;
2453
+ bool chk_x;
2454
+ bool no_x;
2455
+ bool no_w;
2456
+ bool stall_en;
2457
+ bool default_stall_violation_en;
2458
+ bool peis;
2459
+ bool pees;
2460
+ bool mfr_en;
2461
+ /* Indicate md_entry_num for mdcfg_fmt1/2 */
2462
+ uint32_t default_md_entry_num;
2463
+ uint32_t md_num;
2464
+ uint32_t rrid_num;
2465
+ uint32_t entry_num;
2466
+ /* Indicate number of priority entry */
2467
+ uint32_t default_prio_entry;
2468
+ uint32_t default_rrid_transl;
2469
+ /* MSI */
2470
+ bool default_msi_en;
2471
+ uint32_t default_msidata;
2472
+ uint32_t default_err_msiaddr;
2473
+ uint32_t default_err_msiaddrh;
2474
+ uint32_t msi_rrid;
2475
+ /* Note: entry_offset < 0 is not support in QEMU */
2476
+ int32_t entry_offset;
2477
+ /*
2478
+ * Data value to be returned for all read accesses that violate the security
2479
+ * check
2480
+ */
2481
+ uint32_t err_rdata;
2482
+
2483
+ /* Current status for programmable parameters */
2484
+ bool prient_prog;
2485
+ bool rrid_transl_prog;
2486
+ uint32_t md_entry_num;
2487
+ uint32_t prio_entry;
2488
+ uint32_t rrid_transl;
2489
+ bool enable;
2490
+} RISCVIOPMPState;
2491
+
2492
+DeviceState *iopmp_create(hwaddr addr, qemu_irq irq);
2493
+void iopmp_setup_system_memory(DeviceState *dev, const MemMapEntry *memmap,
2494
+ uint32_t mapentry_num, uint32_t stage);
2495
+void iopmp_setup_sink(DeviceState *dev, StreamSink * ss);
2496
+
2497
+#endif
2498
--
2499
2.34.1
2500
2501
diff view generated by jsdifflib
New patch
[PATCH v9 7/8] hw/misc/riscv_iopmp_dispatcher: Device for redirect IOPMP transaction infomation
1
This device determines the target IOPMP device for forwarding information
2
based on:
3
* Address: For parallel IOPMP devices
4
* Stage: For cascading IOPMP devices
1
5
6
Signed-off-by: Ethan Chen <ethan84@andestech.com>
7
---
8
hw/misc/meson.build | 1 +
9
hw/misc/riscv_iopmp_dispatcher.c | 136 +++++++++++++++++++++++
10
include/hw/misc/riscv_iopmp_dispatcher.h | 61 ++++++++++
11
3 files changed, 198 insertions(+)
12
create mode 100644 hw/misc/riscv_iopmp_dispatcher.c
13
create mode 100644 include/hw/misc/riscv_iopmp_dispatcher.h
14
15
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/misc/meson.build
18
+++ b/hw/misc/meson.build
19
@@ -XXX,XX +XXX,XX @@ system_ss.add(when: 'CONFIG_SIFIVE_E_AON', if_true: files('sifive_e_aon.c'))
20
system_ss.add(when: 'CONFIG_SIFIVE_U_OTP', if_true: files('sifive_u_otp.c'))
21
system_ss.add(when: 'CONFIG_SIFIVE_U_PRCI', if_true: files('sifive_u_prci.c'))
22
specific_ss.add(when: 'CONFIG_RISCV_IOPMP', if_true: files('riscv_iopmp.c'))
23
+specific_ss.add(when: 'CONFIG_RISCV_IOPMP', if_true: files('riscv_iopmp_dispatcher.c'))
24
25
subdir('macio')
26
27
diff --git a/hw/misc/riscv_iopmp_dispatcher.c b/hw/misc/riscv_iopmp_dispatcher.c
28
new file mode 100644
29
index XXXXXXX..XXXXXXX
30
--- /dev/null
31
+++ b/hw/misc/riscv_iopmp_dispatcher.c
32
@@ -XXX,XX +XXX,XX @@
33
+/*
34
+ * QEMU RISC-V IOPMP dispatcher
35
+ *
36
+ * Receives transaction information from the requestor and forwards it to the
37
+ * corresponding IOPMP device.
38
+ *
39
+ * Copyright (c) 2023-2025 Andes Tech. Corp.
40
+ *
41
+ * SPDX-License-Identifier: GPL-2.0-or-later
42
+ *
43
+ * This program is free software; you can redistribute it and/or modify it
44
+ * under the terms and conditions of the GNU General Public License,
45
+ * version 2 or later, as published by the Free Software Foundation.
46
+ *
47
+ * This program is distributed in the hope it will be useful, but WITHOUT
48
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
49
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
50
+ * more details.
51
+ *
52
+ * You should have received a copy of the GNU General Public License along with
53
+ * this program. If not, see <http://www.gnu.org/licenses/>.
54
+ */
55
+
56
+#include "qemu/osdep.h"
57
+#include "qemu/log.h"
58
+#include "qapi/error.h"
59
+#include "trace.h"
60
+#include "exec/exec-all.h"
61
+#include "exec/address-spaces.h"
62
+#include "hw/qdev-properties.h"
63
+#include "hw/sysbus.h"
64
+#include "hw/misc/riscv_iopmp_dispatcher.h"
65
+#include "memory.h"
66
+#include "hw/irq.h"
67
+#include "hw/misc/riscv_iopmp_txn_info.h"
68
+
69
+static void riscv_iopmp_dispatcher_realize(DeviceState *dev, Error **errp)
70
+{
71
+ int i;
72
+ RISCVIOPMPDispState *s = RISCV_IOPMP_DISP(dev);
73
+
74
+ s->SinkMemMap = g_new(SinkMemMapEntry *, s->stage_num);
75
+ for (i = 0; i < s->stage_num; i++) {
76
+ s->SinkMemMap[i] = g_new(SinkMemMapEntry, s->target_num);
77
+ }
78
+
79
+ object_initialize_child(OBJECT(s), "iopmp_dispatcher_txn_info",
80
+ &s->txn_info_sink,
81
+ TYPE_RISCV_IOPMP_DISP_SS);
82
+}
83
+
84
+static Property iopmp_dispatcher_properties[] = {
85
+ DEFINE_PROP_UINT32("stage-num", RISCVIOPMPDispState, stage_num, 2),
86
+ DEFINE_PROP_UINT32("target-num", RISCVIOPMPDispState, target_num, 10),
87
+};
88
+
89
+static void riscv_iopmp_dispatcher_class_init(ObjectClass *klass, void *data)
90
+{
91
+ DeviceClass *dc = DEVICE_CLASS(klass);
92
+ device_class_set_props(dc, iopmp_dispatcher_properties);
93
+ dc->realize = riscv_iopmp_dispatcher_realize;
94
+}
95
+
96
+static const TypeInfo riscv_iopmp_dispatcher_info = {
97
+ .name = TYPE_RISCV_IOPMP_DISP,
98
+ .parent = TYPE_DEVICE,
99
+ .instance_size = sizeof(RISCVIOPMPDispState),
100
+ .class_init = riscv_iopmp_dispatcher_class_init,
101
+};
102
+
103
+static size_t dispatcher_txn_info_push(StreamSink *txn_info_sink,
104
+ unsigned char *buf,
105
+ size_t len, bool eop)
106
+{
107
+ uint64_t addr;
108
+ uint32_t stage;
109
+ int i, j;
110
+ riscv_iopmp_disp_ss *ss =
111
+ RISCV_IOPMP_DISP_SS(txn_info_sink);
112
+ RISCVIOPMPDispState *s = RISCV_IOPMP_DISP(container_of(ss,
113
+ RISCVIOPMPDispState, txn_info_sink));
114
+ riscv_iopmp_txn_info signal;
115
+ memcpy(&signal, buf, len);
116
+ addr = signal.start_addr;
117
+ stage = signal.stage;
118
+ for (i = stage; i < s->stage_num; i++) {
119
+ for (j = 0; j < s->target_num; j++) {
120
+ if (s->SinkMemMap[i][j].map.base <= addr &&
121
+ addr < s->SinkMemMap[i][j].map.base
122
+ + s->SinkMemMap[i][j].map.size) {
123
+ return stream_push(s->SinkMemMap[i][j].sink, buf, len, eop);
124
+ }
125
+ }
126
+ }
127
+ /* Always pass if target is not protected by IOPMP*/
128
+ return 1;
129
+}
130
+
131
+static void riscv_iopmp_disp_ss_class_init(
132
+ ObjectClass *klass, void *data)
133
+{
134
+ StreamSinkClass *ssc = STREAM_SINK_CLASS(klass);
135
+ ssc->push = dispatcher_txn_info_push;
136
+}
137
+
138
+static const TypeInfo riscv_iopmp_disp_ss_info = {
139
+ .name = TYPE_RISCV_IOPMP_DISP_SS,
140
+ .parent = TYPE_OBJECT,
141
+ .instance_size = sizeof(riscv_iopmp_disp_ss),
142
+ .class_init = riscv_iopmp_disp_ss_class_init,
143
+ .interfaces = (InterfaceInfo[]) {
144
+ { TYPE_STREAM_SINK },
145
+ { }
146
+ },
147
+};
148
+
149
+void iopmp_dispatcher_add_target(DeviceState *dev, StreamSink *sink,
150
+ uint64_t base, uint64_t size, uint32_t stage, uint32_t id)
151
+{
152
+ RISCVIOPMPDispState *s = RISCV_IOPMP_DISP(dev);
153
+ if (stage < s->stage_num && id < s->target_num) {
154
+ s->SinkMemMap[stage][id].map.base = base;
155
+ s->SinkMemMap[stage][id].map.size = size;
156
+ s->SinkMemMap[stage][id].sink = sink;
157
+ }
158
+}
159
+
160
+static void
161
+iopmp_dispatcher_register_types(void)
162
+{
163
+ type_register_static(&riscv_iopmp_dispatcher_info);
164
+ type_register_static(&riscv_iopmp_disp_ss_info);
165
+}
166
+
167
+type_init(iopmp_dispatcher_register_types);
168
+
169
diff --git a/include/hw/misc/riscv_iopmp_dispatcher.h b/include/hw/misc/riscv_iopmp_dispatcher.h
170
new file mode 100644
171
index XXXXXXX..XXXXXXX
172
--- /dev/null
173
+++ b/include/hw/misc/riscv_iopmp_dispatcher.h
174
@@ -XXX,XX +XXX,XX @@
175
+/*
176
+ * QEMU RISC-V IOPMP dispatcher
177
+ *
178
+ * Receives transaction information from the requestor and forwards it to the
179
+ * corresponding IOPMP device.
180
+ *
181
+ * Copyright (c) 2023-2024 Andes Tech. Corp.
182
+ *
183
+ * SPDX-License-Identifier: GPL-2.0-or-later
184
+ *
185
+ * This program is free software; you can redistribute it and/or modify it
186
+ * under the terms and conditions of the GNU General Public License,
187
+ * version 2 or later, as published by the Free Software Foundation.
188
+ *
189
+ * This program is distributed in the hope it will be useful, but WITHOUT
190
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
191
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
192
+ * more details.
193
+ *
194
+ * You should have received a copy of the GNU General Public License along with
195
+ * this program. If not, see <http://www.gnu.org/licenses/>.
196
+ */
197
+
198
+#ifndef RISCV_IOPMP_DISPATCHER_H
199
+#define RISCV_IOPMP_DISPATCHER_H
200
+
201
+#include "hw/sysbus.h"
202
+#include "qemu/typedefs.h"
203
+#include "memory.h"
204
+#include "hw/stream.h"
205
+#include "hw/misc/riscv_iopmp_txn_info.h"
206
+#include "exec/hwaddr.h"
207
+
208
+#define TYPE_RISCV_IOPMP_DISP "riscv-iopmp-dispatcher"
209
+OBJECT_DECLARE_SIMPLE_TYPE(RISCVIOPMPDispState, RISCV_IOPMP_DISP)
210
+
211
+#define TYPE_RISCV_IOPMP_DISP_SS "riscv-iopmp-dispatcher-streamsink"
212
+OBJECT_DECLARE_SIMPLE_TYPE(riscv_iopmp_disp_ss, RISCV_IOPMP_DISP_SS)
213
+
214
+typedef struct riscv_iopmp_disp_ss {
215
+ Object parent;
216
+} riscv_iopmp_disp_ss;
217
+
218
+typedef struct SinkMemMapEntry {
219
+ StreamSink *sink;
220
+ MemMapEntry map;
221
+} SinkMemMapEntry;
222
+
223
+typedef struct RISCVIOPMPDispState {
224
+ SysBusDevice parent_obj;
225
+ riscv_iopmp_disp_ss txn_info_sink;
226
+ SinkMemMapEntry **SinkMemMap;
227
+ /* The maximum number of cascading stages of IOPMP */
228
+ uint32_t stage_num;
229
+ /* The maximum number of parallel IOPMP devices within a single stage. */
230
+ uint32_t target_num;
231
+} RISCVIOPMPDispState;
232
+
233
+void iopmp_dispatcher_add_target(DeviceState *dev, StreamSink *sink,
234
+ uint64_t base, uint64_t size, uint32_t stage, uint32_t id);
235
+#endif
236
--
237
2.34.1
diff view generated by jsdifflib
[PATCH v2 1/4] exec/memattrs: Add iopmp source id, start address, end address to MemTxAttrs
[PATCH v9 8/8] hw/riscv/virt: Add IOPMP support
1
- Add 'iopmp=on' option to enable IOPMP. It adds iopmp devices virt machine
2
to protect all regions of system memory.
3
1
Signed-off-by: Ethan Chen <ethan84@andestech.com>
4
Signed-off-by: Ethan Chen <ethan84@andestech.com>
2
---
5
---
3
include/exec/memattrs.h | 6 ++++++
6
docs/system/riscv/virt.rst | 7 ++++
4
1 file changed, 6 insertions(+)
7
hw/riscv/Kconfig | 1 +
8
hw/riscv/virt.c | 75 ++++++++++++++++++++++++++++++++++++++
9
include/hw/riscv/virt.h | 4 ++
10
4 files changed, 87 insertions(+)
5
11
6
diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h
12
diff --git a/docs/system/riscv/virt.rst b/docs/system/riscv/virt.rst
7
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
8
--- a/include/exec/memattrs.h
14
--- a/docs/system/riscv/virt.rst
9
+++ b/include/exec/memattrs.h
15
+++ b/docs/system/riscv/virt.rst
10
@@ -XXX,XX +XXX,XX @@ typedef struct MemTxAttrs {
16
@@ -XXX,XX +XXX,XX @@ The following machine-specific options are supported:
11
unsigned int target_tlb_bit0 : 1;
17
12
unsigned int target_tlb_bit1 : 1;
18
Enables the riscv-iommu-sys platform device. Defaults to 'off'.
13
unsigned int target_tlb_bit2 : 1;
19
14
+
20
+- iopmp=[on|off]
15
+ /* IOPMP support up to 65535 sources */
21
+
16
+ unsigned int iopmp_sid:16;
22
+ When this option is "on", IOPMP devices are added to machine. IOPMP checks
17
+ /* Transaction infomation for IOPMP */
23
+ memory transcations in system memory. This option is assumed to be "off". To
18
+ unsigned long long iopmp_start_addr;
24
+ enable the CPU to perform transactions with a specified RRID, use the CPU
19
+ unsigned long long iopmp_end_addr;
25
+ option "-cpu <cpu>,iopmp=true,iopmp_rrid=<rrid>"
20
} MemTxAttrs;
26
+
21
27
Running Linux kernel
22
/* Bus masters which don't specify any attributes will get this,
28
--------------------
29
30
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
31
index XXXXXXX..XXXXXXX 100644
32
--- a/hw/riscv/Kconfig
33
+++ b/hw/riscv/Kconfig
34
@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
35
select PLATFORM_BUS
36
select ACPI
37
select ACPI_PCI
38
+ select RISCV_IOPMP
39
40
config SHAKTI_C
41
bool
42
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
43
index XXXXXXX..XXXXXXX 100644
44
--- a/hw/riscv/virt.c
45
+++ b/hw/riscv/virt.c
46
@@ -XXX,XX +XXX,XX @@
47
#include "hw/acpi/aml-build.h"
48
#include "qapi/qapi-visit-common.h"
49
#include "hw/virtio/virtio-iommu.h"
50
+#include "hw/misc/riscv_iopmp.h"
51
+#include "hw/misc/riscv_iopmp_dispatcher.h"
52
53
/* KVM AIA only supports APLIC MSI. APLIC Wired is always emulated by QEMU. */
54
static bool virt_use_kvm_aia_aplic_imsic(RISCVVirtAIAType aia_type)
55
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry virt_memmap[] = {
56
[VIRT_UART0] = { 0x10000000, 0x100 },
57
[VIRT_VIRTIO] = { 0x10001000, 0x1000 },
58
[VIRT_FW_CFG] = { 0x10100000, 0x18 },
59
+ [VIRT_IOPMP] = { 0x10200000, 0x100000 },
60
[VIRT_FLASH] = { 0x20000000, 0x4000000 },
61
[VIRT_IMSIC_M] = { 0x24000000, VIRT_IMSIC_MAX_SIZE },
62
[VIRT_IMSIC_S] = { 0x28000000, VIRT_IMSIC_MAX_SIZE },
63
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry virt_memmap[] = {
64
[VIRT_DRAM] = { 0x80000000, 0x0 },
65
};
66
67
+static const MemMapEntry iopmp_protect_memmap[] = {
68
+ /* IOPMP protect all regions by default */
69
+ {0x0, 0xFFFFFFFF},
70
+};
71
+
72
/* PCIe high mmio is fixed for RV32 */
73
#define VIRT32_HIGH_PCIE_MMIO_BASE 0x300000000ULL
74
#define VIRT32_HIGH_PCIE_MMIO_SIZE (4 * GiB)
75
@@ -XXX,XX +XXX,XX @@ static void create_fdt_iommu(RISCVVirtState *s, uint16_t bdf)
76
bdf + 1, iommu_phandle, bdf + 1, 0xffff - bdf);
77
}
78
79
+static void create_fdt_iopmp(RISCVVirtState *s, const MemMapEntry *memmap,
80
+ uint32_t irq_mmio_phandle) {
81
+ g_autofree char *name = NULL;
82
+ MachineState *ms = MACHINE(s);
83
+
84
+ name = g_strdup_printf("/soc/iopmp@%lx", (long)memmap[VIRT_IOPMP].base);
85
+ qemu_fdt_add_subnode(ms->fdt, name);
86
+ qemu_fdt_setprop_string(ms->fdt, name, "compatible", "riscv_iopmp");
87
+ qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0x0, memmap[VIRT_IOPMP].base,
88
+ 0x0, memmap[VIRT_IOPMP].size);
89
+ qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", irq_mmio_phandle);
90
+ if (s->aia_type == VIRT_AIA_TYPE_NONE) {
91
+ qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", IOPMP_IRQ);
92
+ } else {
93
+ qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", IOPMP_IRQ, 0x4);
94
+ }
95
+}
96
+
97
static void finalize_fdt(RISCVVirtState *s)
98
{
99
uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1;
100
@@ -XXX,XX +XXX,XX @@ static void finalize_fdt(RISCVVirtState *s)
101
create_fdt_uart(s, virt_memmap, irq_mmio_phandle);
102
103
create_fdt_rtc(s, virt_memmap, irq_mmio_phandle);
104
+
105
+ if (s->have_iopmp) {
106
+ create_fdt_iopmp(s, virt_memmap, irq_mmio_phandle);
107
+ }
108
}
109
110
static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap)
111
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
112
DeviceState *mmio_irqchip, *virtio_irqchip, *pcie_irqchip;
113
int i, base_hartid, hart_count;
114
int socket_count = riscv_socket_count(machine);
115
+ DeviceState *iopmp_dev, *iopmp_disp_dev;
116
+ StreamSink *iopmp_ss, *iopmp_disp_ss;
117
118
/* Check socket count limit */
119
if (VIRT_SOCKETS_MAX < socket_count) {
120
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
121
}
122
virt_flash_map(s, system_memory);
123
124
+ if (s->have_iopmp) {
125
+ iopmp_dev = iopmp_create(memmap[VIRT_IOPMP].base,
126
+ qdev_get_gpio_in(DEVICE(mmio_irqchip), IOPMP_IRQ));
127
+
128
+ iopmp_setup_system_memory(iopmp_dev, &iopmp_protect_memmap[0], 1, 0);
129
+
130
+ iopmp_disp_dev = qdev_new(TYPE_RISCV_IOPMP_DISP);
131
+ qdev_prop_set_uint32(DEVICE(iopmp_disp_dev), "target-num", 1);
132
+ qdev_prop_set_uint32(DEVICE(iopmp_disp_dev), "stage-num", 1);
133
+ qdev_realize(DEVICE(iopmp_disp_dev), NULL, &error_fatal);
134
+
135
+ /* Add memmap inforamtion to dispatcher */
136
+ iopmp_ss = (StreamSink *)&(RISCV_IOPMP(iopmp_dev)->txn_info_sink);
137
+ iopmp_dispatcher_add_target(DEVICE(iopmp_disp_dev), iopmp_ss,
138
+ iopmp_protect_memmap[0].base,
139
+ iopmp_protect_memmap[0].size,
140
+ 0, 0);
141
+
142
+ iopmp_disp_ss =
143
+ (StreamSink *)&(RISCV_IOPMP_DISP(iopmp_disp_dev)->txn_info_sink);
144
+ iopmp_setup_sink(iopmp_dev, iopmp_disp_ss);
145
+ }
146
+
147
/* load/create device tree */
148
if (machine->dtb) {
149
machine->fdt = load_device_tree(machine->dtb, &s->fdt_size);
150
@@ -XXX,XX +XXX,XX @@ static void virt_set_iommu_sys(Object *obj, Visitor *v, const char *name,
151
visit_type_OnOffAuto(v, name, &s->iommu_sys, errp);
152
}
153
154
+static bool virt_get_iopmp(Object *obj, Error **errp)
155
+{
156
+ RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
157
+
158
+ return s->have_iopmp;
159
+}
160
+
161
+static void virt_set_iopmp(Object *obj, bool value, Error **errp)
162
+{
163
+ RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
164
+
165
+ s->have_iopmp = value;
166
+}
167
+
168
bool virt_is_acpi_enabled(RISCVVirtState *s)
169
{
170
return s->acpi != ON_OFF_AUTO_OFF;
171
@@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
172
NULL, NULL);
173
object_class_property_set_description(oc, "iommu-sys",
174
"Enable IOMMU platform device");
175
+
176
+ object_class_property_add_bool(oc, "iopmp", virt_get_iopmp,
177
+ virt_set_iopmp);
178
+ object_class_property_set_description(oc, "iopmp",
179
+ "Set on/off to enable/disable "
180
+ "iopmp device");
181
}
182
183
static const TypeInfo virt_machine_typeinfo = {
184
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
185
index XXXXXXX..XXXXXXX 100644
186
--- a/include/hw/riscv/virt.h
187
+++ b/include/hw/riscv/virt.h
188
@@ -XXX,XX +XXX,XX @@ struct RISCVVirtState {
189
190
int fdt_size;
191
bool have_aclint;
192
+ bool have_iopmp;
193
RISCVVirtAIAType aia_type;
194
int aia_guests;
195
char *oem_id;
196
@@ -XXX,XX +XXX,XX @@ enum {
197
VIRT_PLATFORM_BUS,
198
VIRT_PCIE_ECAM,
199
VIRT_IOMMU_SYS,
200
+ VIRT_IOPMP,
201
};
202
203
enum {
204
UART0_IRQ = 10,
205
RTC_IRQ = 11,
206
+ IOPMP_IRQ = 12,
207
+ DMA_IRQ = 13,
208
VIRTIO_IRQ = 1, /* 1 to 8 */
209
VIRTIO_COUNT = 8,
210
PCIE_IRQ = 0x20, /* 32 to 35 */
23
--
211
--
24
2.34.1
212
2.34.1
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

© 2016 - 2025 Red Hat, Inc.