This series implements IOPMP specification v1.0.0-draft4 rapid-k model.
When IOPMP is enabled, a DMA device ATCDMAC300 is added to RISC-V virt
platform. This DMA devce is connected to the IOPMP and has the functionalities
required by IOPMP, including:
- Support specify source-id (SID)
- Support asynchronous I/O to handle stall transcations
IOPMP takes a transaction which partially match an entry as a partially hit
error. The transaction size is depending on source device, destination device
and bus.
As v1 disccussion, new iommu translate_size() function is not suitable because
the size may be modified in previos stage.
In addtion to SID, start address and end address are also added to MemTxAttrs
in v2. IOPMP matches transaction to an entry with those attributes.
Changes for v2:
- Add iopmp_start_addr and iopmp_end_addr to MemTxAttrs.
- Remove translate_size().
- IOPMP: Get transaction info in attrs_to_index instead of using
translate_size().
- IOPMP: Fix some partially hit transactions are not detected.
- ATCDMAC300: Fix write stall is not resumed correctly.
- ATCDMAC300: Fix some partially hit errors are not detected.
Ethan Chen (4):
exec/memattrs: Add iopmp source id, start address, end address to
MemTxAttrs
Add RISC-V IOPMP support
hw/dma: Add Andes ATCDMAC300 support
hw/riscv/virt: Add IOPMP support
hw/dma/Kconfig | 3 +
hw/dma/atcdmac300.c | 460 +++++++++++++++++
hw/dma/meson.build | 1 +
hw/misc/Kconfig | 3 +
hw/misc/meson.build | 1 +
hw/misc/riscv_iopmp.c | 902 ++++++++++++++++++++++++++++++++++
hw/riscv/Kconfig | 2 +
hw/riscv/virt.c | 68 +++
include/exec/memattrs.h | 6 +
include/hw/dma/atcdmac300.h | 171 +++++++
include/hw/misc/riscv_iopmp.h | 330 +++++++++++++
include/hw/riscv/virt.h | 10 +-
12 files changed, 1956 insertions(+), 1 deletion(-)
create mode 100644 hw/dma/atcdmac300.c
create mode 100644 hw/misc/riscv_iopmp.c
create mode 100644 include/hw/dma/atcdmac300.h
create mode 100644 include/hw/misc/riscv_iopmp.h
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2.34.1