RISC-V: OpenTitan: Fixup ePMP and SPI interrupts

[PATCH 0/2] RISC-V: OpenTitan: Fixup ePMP and SPI interrupts

Alistair Francis posted 2 patches 1 year ago

Download series mbox

Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20231102003424.2003428-1-alistair.francis@wdc.com

Maintainers: Alistair Francis <alistair@alistair23.me>, Palmer Dabbelt <palmer@dabbelt.com>, Bin Meng <bin.meng@windriver.com>, Weiwei Li <liweiwei@iscas.ac.cn>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>

hw/ssi/ibex_spi_host.c | 6 ++++--
target/riscv/cpu.c     | 2 +-
2 files changed, 5 insertions(+), 3 deletions(-)

Expand all Fold all

[PATCH 0/2] RISC-V: OpenTitan: Fixup ePMP and SPI interrupts

Posted by Alistair Francis 1 year ago

Fixup the Ibex CPU priv version so that smepmp/epmp is correctly
enabled and make a small change to the SPI interrupt generation to
ensure we don't miss interrupts.

Alistair Francis (2):
  hw/ssi: ibex_spi_host: Clear the interrupt even if disabled
  target/riscv: cpu: Set the OpenTitan priv to 1.12.0

 hw/ssi/ibex_spi_host.c | 6 ++++--
 target/riscv/cpu.c     | 2 +-
 2 files changed, 5 insertions(+), 3 deletions(-)

-- 
2.41.0

Re: [PATCH 0/2] RISC-V: OpenTitan: Fixup ePMP and SPI interrupts

Posted by Alistair Francis 1 year ago

On Thu, Nov 2, 2023 at 10:34 AM Alistair Francis <alistair23@gmail.com> wrote:
>
> Fixup the Ibex CPU priv version so that smepmp/epmp is correctly
> enabled and make a small change to the SPI interrupt generation to
> ensure we don't miss interrupts.
>
> Alistair Francis (2):
>   hw/ssi: ibex_spi_host: Clear the interrupt even if disabled
>   target/riscv: cpu: Set the OpenTitan priv to 1.12.0

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>  hw/ssi/ibex_spi_host.c | 6 ++++--
>  target/riscv/cpu.c     | 2 +-
>  2 files changed, 5 insertions(+), 3 deletions(-)
>
> --
> 2.41.0
>