Add a small test to prevent regressions.

Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
---
 tests/tcg/s390x/Makefile.target |  1 +
 tests/tcg/s390x/clc.c           | 48 +++++++++++++++++++++++++++++++++
 2 files changed, 49 insertions(+)
 create mode 100644 tests/tcg/s390x/clc.c

diff --git a/tests/tcg/s390x/Makefile.target b/tests/tcg/s390x/Makefile.target
index 826f0a18e43..ccd4f4e68de 100644
--- a/tests/tcg/s390x/Makefile.target
+++ b/tests/tcg/s390x/Makefile.target
@@ -41,6 +41,7 @@ TESTS+=larl
 TESTS+=mdeb
 TESTS+=cgebra
 TESTS+=clgebr
+TESTS+=clc
 
 cdsg: CFLAGS+=-pthread
 cdsg: LDFLAGS+=-pthread
diff --git a/tests/tcg/s390x/clc.c b/tests/tcg/s390x/clc.c
new file mode 100644
index 00000000000..e14189bd75e
--- /dev/null
+++ b/tests/tcg/s390x/clc.c
@@ -0,0 +1,48 @@
+/*
+ * Test the CLC instruction.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+#include <assert.h>
+#include <signal.h>
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h>
+
+static void handle_sigsegv(int sig, siginfo_t *info, void *ucontext)
+{
+    mcontext_t *mcontext = &((ucontext_t *)ucontext)->uc_mcontext;
+    if (mcontext->gregs[0] != 600) {
+        write(STDERR_FILENO, "bad r0\n", 7);
+        _exit(EXIT_FAILURE);
+    }
+    if (((mcontext->psw.mask >> 44) & 3) != 1) {
+        write(STDERR_FILENO, "bad cc\n", 7);
+        _exit(EXIT_FAILURE);
+    }
+    _exit(EXIT_SUCCESS);
+}
+
+int main(void)
+{
+    register unsigned long r0 asm("r0");
+    unsigned long mem = 42, rhs = 500;
+    struct sigaction act;
+    int err;
+
+    memset(&act, 0, sizeof(act));
+    act.sa_sigaction = handle_sigsegv;
+    act.sa_flags = SA_SIGINFO;
+    err = sigaction(SIGSEGV, &act, NULL);
+    assert(err == 0);
+
+    r0 = 100;
+    asm("algr %[r0],%[rhs]\n"
+        "clc 0(8,%[mem]),0(0)\n"  /* The 2nd operand will cause a SEGV. */
+        : [r0] "+r" (r0)
+        : [mem] "r" (&mem)
+        , [rhs] "r" (rhs)
+        : "cc", "memory");
+
+    return EXIT_FAILURE;
+}
-- 
2.41.0

On 10/30/23 22:32, Ilya Leoshkevich wrote:
> +int main(void)
> +{
> +    register unsigned long r0 asm("r0");
> +    unsigned long mem = 42, rhs = 500;
> +    struct sigaction act;
> +    int err;
> +
> +    memset(&act, 0, sizeof(act));
> +    act.sa_sigaction = handle_sigsegv;
> +    act.sa_flags = SA_SIGINFO;
> +    err = sigaction(SIGSEGV, &act, NULL);
> +    assert(err == 0);
> +
> +    r0 = 100;
> +    asm("algr %[r0],%[rhs]\n"
> +        "clc 0(8,%[mem]),0(0)\n"  /* The 2nd operand will cause a SEGV. */
> +        : [r0] "+r" (r0)
> +        : [mem] "r" (&mem)
> +        , [rhs] "r" (rhs)
> +        : "cc", "memory");
> +

You could just as easily set cc based on CHI or something to avoid hard-coding r0, or even 
clobbering an output register at all.

But I guess there's little point bike shedding this too much...

r~

On Tue, 2023-10-31 at 15:53 -0700, Richard Henderson wrote:
> On 10/30/23 22:32, Ilya Leoshkevich wrote:
> > +int main(void)
> > +{
> > +    register unsigned long r0 asm("r0");
> > +    unsigned long mem = 42, rhs = 500;
> > +    struct sigaction act;
> > +    int err;
> > +
> > +    memset(&act, 0, sizeof(act));
> > +    act.sa_sigaction = handle_sigsegv;
> > +    act.sa_flags = SA_SIGINFO;
> > +    err = sigaction(SIGSEGV, &act, NULL);
> > +    assert(err == 0);
> > +
> > +    r0 = 100;
> > +    asm("algr %[r0],%[rhs]\n"
> > +        "clc 0(8,%[mem]),0(0)\n"  /* The 2nd operand will cause a
> > SEGV. */
> > +        : [r0] "+r" (r0)
> > +        : [mem] "r" (&mem)
> > +        , [rhs] "r" (rhs)
> > +        : "cc", "memory");
> > +
> 
> You could just as easily set cc based on CHI or something to avoid
> hard-coding r0, or even 
> clobbering an output register at all.

The point of hardcoding r0 is rather to be able to check its value in
handle_sigsegv(). While this was not buggy, I still wanted to make sure
that the updated value is "committed" despite SEGV.

> 
> But I guess there's little point bike shedding this too much...
> 
> r~