Based-on: <20231029145033.592566-1-alex.bennee@linaro.org>
("[PATCH v2 00/19] Maintainer updates for testing, gdb, semihosting and
plugins (pre-PR)")

This series extracts fixes and refactorings that can be applied
independently from "[PATCH v9 00/23] plugins: Allow to read registers".

The patch "target/riscv: Move MISA limits to class" was replaced with
patch "target/riscv: Move misa_mxl_max to class" since I found instances
may have different misa_ext_mask.

V5 -> V6:
  Added patch "default-configs: Add TARGET_XML_FILES definition".
  Rebased.

V4 -> V5:
  Added patch "hw/riscv: Use misa_mxl instead of misa_mxl_max".

V3 -> V4:
  Added patch "gdbstub: Check if gdb_regs is NULL".

V2 -> V3:
  Restored patch sets from the previous version.
  Rebased to commit 800485762e6564e04e2ab315132d477069562d91.

V1 -> V2:
  Added patch "target/riscv: Do not allow MXL_RV32 for TARGET_RISCV64".
  Added patch "target/riscv: Initialize gdb_core_xml_file only once".
  Dropped patch "target/riscv: Remove misa_mxl validation".
  Dropped patch "target/riscv: Move misa_mxl_max to class".
  Dropped patch "target/riscv: Validate misa_mxl_max only once".

Akihiko Odaki (5):
  hw/riscv: Use misa_mxl instead of misa_mxl_max
  target/riscv: Remove misa_mxl validation
  target/riscv: Move misa_mxl_max to class
  target/riscv: Validate misa_mxl_max only once
  default-configs: Add TARGET_XML_FILES definition

 configs/targets/loongarch64-linux-user.mak |   1 +
 target/riscv/cpu-qom.h                     |   1 +
 target/riscv/cpu.h                         |   3 +-
 hw/riscv/boot.c                            |   2 +-
 target/riscv/cpu.c                         | 139 ++++++++++++---------
 target/riscv/gdbstub.c                     |  12 +-
 target/riscv/kvm/kvm-cpu.c                 |  10 +-
 target/riscv/machine.c                     |   7 +-
 target/riscv/tcg/tcg-cpu.c                 |  42 +------
 target/riscv/translate.c                   |   3 +-
 10 files changed, 109 insertions(+), 111 deletions(-)

-- 
2.42.0

On Mon, Oct 30, 2023 at 3:49 PM Akihiko Odaki <akihiko.odaki@daynix.com> wrote:
>
> Based-on: <20231029145033.592566-1-alex.bennee@linaro.org>
> ("[PATCH v2 00/19] Maintainer updates for testing, gdb, semihosting and
> plugins (pre-PR)")
>
> This series extracts fixes and refactorings that can be applied
> independently from "[PATCH v9 00/23] plugins: Allow to read registers".
>
> The patch "target/riscv: Move MISA limits to class" was replaced with
> patch "target/riscv: Move misa_mxl_max to class" since I found instances
> may have different misa_ext_mask.

What instances? Couldn't MXL have the same differences?

Alistair

>
> V5 -> V6:
>   Added patch "default-configs: Add TARGET_XML_FILES definition".
>   Rebased.
>
> V4 -> V5:
>   Added patch "hw/riscv: Use misa_mxl instead of misa_mxl_max".
>
> V3 -> V4:
>   Added patch "gdbstub: Check if gdb_regs is NULL".
>
> V2 -> V3:
>   Restored patch sets from the previous version.
>   Rebased to commit 800485762e6564e04e2ab315132d477069562d91.
>
> V1 -> V2:
>   Added patch "target/riscv: Do not allow MXL_RV32 for TARGET_RISCV64".
>   Added patch "target/riscv: Initialize gdb_core_xml_file only once".
>   Dropped patch "target/riscv: Remove misa_mxl validation".
>   Dropped patch "target/riscv: Move misa_mxl_max to class".
>   Dropped patch "target/riscv: Validate misa_mxl_max only once".
>
> Akihiko Odaki (5):
>   hw/riscv: Use misa_mxl instead of misa_mxl_max
>   target/riscv: Remove misa_mxl validation
>   target/riscv: Move misa_mxl_max to class
>   target/riscv: Validate misa_mxl_max only once
>   default-configs: Add TARGET_XML_FILES definition
>
>  configs/targets/loongarch64-linux-user.mak |   1 +
>  target/riscv/cpu-qom.h                     |   1 +
>  target/riscv/cpu.h                         |   3 +-
>  hw/riscv/boot.c                            |   2 +-
>  target/riscv/cpu.c                         | 139 ++++++++++++---------
>  target/riscv/gdbstub.c                     |  12 +-
>  target/riscv/kvm/kvm-cpu.c                 |  10 +-
>  target/riscv/machine.c                     |   7 +-
>  target/riscv/tcg/tcg-cpu.c                 |  42 +------
>  target/riscv/translate.c                   |   3 +-
>  10 files changed, 109 insertions(+), 111 deletions(-)
>
> --
> 2.42.0
>
>

On 2023/11/23 12:10, Alistair Francis wrote:
> On Mon, Oct 30, 2023 at 3:49 PM Akihiko Odaki <akihiko.odaki@daynix.com> wrote:
>>
>> Based-on: <20231029145033.592566-1-alex.bennee@linaro.org>
>> ("[PATCH v2 00/19] Maintainer updates for testing, gdb, semihosting and
>> plugins (pre-PR)")
>>
>> This series extracts fixes and refactorings that can be applied
>> independently from "[PATCH v9 00/23] plugins: Allow to read registers".
>>
>> The patch "target/riscv: Move MISA limits to class" was replaced with
>> patch "target/riscv: Move misa_mxl_max to class" since I found instances
>> may have different misa_ext_mask.
> 
> What instances? Couldn't MXL have the same differences? >
> Alistair

Instances of subclasses of riscv-cpu. While misa_ext_mask are 
configurable for each instances with properties, the misa_mxl_max value 
is hardcoded for each classes and will not have such differences.

Regards,
Akihiko Odaki