From: Hao Wu <wuhaotsh@google.com>
This patch wires the PCI mailbox module to Nuvoton SoC.
Change-Id: I9421ff6bc7d365b0559c0a1f6b98cfd24b6f2d9f
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Signed-off-by: Nabih Estefan <nabihestefan@google.com>
---
docs/system/arm/nuvoton.rst | 2 ++
hw/arm/npcm7xx.c | 3 ++-
include/hw/arm/npcm7xx.h | 1 +
3 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
index 0424cae4b0..e611099545 100644
--- a/docs/system/arm/nuvoton.rst
+++ b/docs/system/arm/nuvoton.rst
@@ -50,6 +50,8 @@ Supported devices
* Ethernet controller (EMC)
* Tachometer
* Peripheral SPI controller (PSPI)
+ * BIOS POST code FIFO
+ * PCI Mailbox
Missing devices
---------------
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
index c69e936669..c9e87162cb 100644
--- a/hw/arm/npcm7xx.c
+++ b/hw/arm/npcm7xx.c
@@ -86,7 +86,6 @@ enum NPCM7xxInterrupt {
NPCM7XX_UART1_IRQ,
NPCM7XX_UART2_IRQ,
NPCM7XX_UART3_IRQ,
- NPCM7XX_PECI_IRQ = 6,
NPCM7XX_PCI_MBOX_IRQ = 8,
NPCM7XX_KCS_HIB_IRQ = 9,
NPCM7XX_GMAC1_IRQ = 14,
@@ -463,6 +462,8 @@ static void npcm7xx_init(Object *obj)
object_initialize_child(obj, "pspi[*]", &s->pspi[i], TYPE_NPCM_PSPI);
}
+ object_initialize_child(obj, "pci-mbox", &s->pci_mbox,
+ TYPE_NPCM7XX_PCI_MBOX);
object_initialize_child(obj, "mmc", &s->mmc, TYPE_NPCM7XX_SDHCI);
}
diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
index 273090ac60..cec3792a2e 100644
--- a/include/hw/arm/npcm7xx.h
+++ b/include/hw/arm/npcm7xx.h
@@ -105,6 +105,7 @@ struct NPCM7xxState {
OHCISysBusState ohci;
NPCM7xxFIUState fiu[2];
NPCM7xxEMCState emc[2];
+ NPCM7xxPCIMBoxState pci_mbox;
NPCM7xxSDHCIState mmc;
NPCMPSPIState pspi[2];
};
--
2.42.0.820.g83a721a137-goog
-----Original Message-----
From: Nabih Estefan <nabihestefan@google.com>
Sent: Saturday, October 28, 2023 1:55 AM
To: peter.maydell@linaro.org
Cc: qemu-arm@nongnu.org; qemu-devel@nongnu.org; CS20 KFTing <KFTING@nuvoton.com>; wuhaotsh@google.com; jasonwang@redhat.com; IS20 Avi Fishman <Avi.Fishman@nuvoton.com>; nabihestefan@google.com; CS20 KWLiu <KWLIU@nuvoton.com>; IS20 Tomer Maimon <tomer.maimon@nuvoton.com>; IN20 Hila Miranda-Kuzi <Hila.Miranda-Kuzi@nuvoton.com>
Subject: [PATCH v5 02/11] hw/arm: Add PCI mailbox module to Nuvoton SoC
CAUTION - External Email: Do not click links or open attachments unless you acknowledge the sender and content.
From: Hao Wu <wuhaotsh@google.com>
This patch wires the PCI mailbox module to Nuvoton SoC.
Change-Id: I9421ff6bc7d365b0559c0a1f6b98cfd24b6f2d9f
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Signed-off-by: Nabih Estefan <nabihestefan@google.com>
---
docs/system/arm/nuvoton.rst | 2 ++
hw/arm/npcm7xx.c | 3 ++-
include/hw/arm/npcm7xx.h | 1 +
3 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst index 0424cae4b0..e611099545 100644
--- a/docs/system/arm/nuvoton.rst
+++ b/docs/system/arm/nuvoton.rst
@@ -50,6 +50,8 @@ Supported devices
* Ethernet controller (EMC)
* Tachometer
* Peripheral SPI controller (PSPI)
+ * BIOS POST code FIFO
+ * PCI Mailbox
Missing devices
---------------
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c index c69e936669..c9e87162cb 100644
--- a/hw/arm/npcm7xx.c
+++ b/hw/arm/npcm7xx.c
@@ -86,7 +86,6 @@ enum NPCM7xxInterrupt {
NPCM7XX_UART1_IRQ,
NPCM7XX_UART2_IRQ,
NPCM7XX_UART3_IRQ,
- NPCM7XX_PECI_IRQ = 6,
NPCM7XX_PCI_MBOX_IRQ = 8,
NPCM7XX_KCS_HIB_IRQ = 9,
NPCM7XX_GMAC1_IRQ = 14,
@@ -463,6 +462,8 @@ static void npcm7xx_init(Object *obj)
object_initialize_child(obj, "pspi[*]", &s->pspi[i], TYPE_NPCM_PSPI);
}
+ object_initialize_child(obj, "pci-mbox", &s->pci_mbox,
+ TYPE_NPCM7XX_PCI_MBOX);
object_initialize_child(obj, "mmc", &s->mmc, TYPE_NPCM7XX_SDHCI); }
diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h index 273090ac60..cec3792a2e 100644
--- a/include/hw/arm/npcm7xx.h
+++ b/include/hw/arm/npcm7xx.h
@@ -105,6 +105,7 @@ struct NPCM7xxState {
OHCISysBusState ohci;
NPCM7xxFIUState fiu[2];
NPCM7xxEMCState emc[2];
+ NPCM7xxPCIMBoxState pci_mbox;
NPCM7xxSDHCIState mmc;
NPCMPSPIState pspi[2];
};
--
2.42.0.820.g83a721a137-goog
Signed-off-by: Tyrone Ting <kfting@nuvoton.com>
________________________________
________________________________
The privileged confidential information contained in this email is intended for use only by the addressees as indicated by the original sender of this email. If you are not the addressee indicated in this email or are not responsible for delivery of the email to such a person, please kindly reply to the sender indicating this fact and delete all copies of it from your computer and network server immediately. Your cooperation is highly appreciated. It is advised that any unauthorized use of confidential information of Nuvoton is strictly prohibited; and any information in this email irrelevant to the official business of Nuvoton shall be deemed as neither given nor endorsed by Nuvoton.
-----Original Message-----
From: CS20 KFTing
Sent: Monday, November 13, 2023 11:49 AM
To: Nabih Estefan <nabihestefan@google.com>; peter.maydell@linaro.org
Cc: qemu-arm@nongnu.org; qemu-devel@nongnu.org; wuhaotsh@google.com; jasonwang@redhat.com; IS20 Avi Fishman <Avi.Fishman@nuvoton.com>; CS20 KWLiu <KWLIU@nuvoton.com>; IS20 Tomer Maimon <tomer.maimon@nuvoton.com>; IN20 Hila Miranda-Kuzi <Hila.Miranda-Kuzi@nuvoton.com>
Subject: RE: [PATCH v5 02/11] hw/arm: Add PCI mailbox module to Nuvoton SoC
-----Original Message-----
From: Nabih Estefan <nabihestefan@google.com>
Sent: Saturday, October 28, 2023 1:55 AM
To: peter.maydell@linaro.org
Cc: qemu-arm@nongnu.org; qemu-devel@nongnu.org; CS20 KFTing <KFTING@nuvoton.com>; wuhaotsh@google.com; jasonwang@redhat.com; IS20 Avi Fishman <Avi.Fishman@nuvoton.com>; nabihestefan@google.com; CS20 KWLiu <KWLIU@nuvoton.com>; IS20 Tomer Maimon <tomer.maimon@nuvoton.com>; IN20 Hila Miranda-Kuzi <Hila.Miranda-Kuzi@nuvoton.com>
Subject: [PATCH v5 02/11] hw/arm: Add PCI mailbox module to Nuvoton SoC
CAUTION - External Email: Do not click links or open attachments unless you acknowledge the sender and content.
From: Hao Wu <wuhaotsh@google.com>
This patch wires the PCI mailbox module to Nuvoton SoC.
Change-Id: I9421ff6bc7d365b0559c0a1f6b98cfd24b6f2d9f
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Signed-off-by: Nabih Estefan <nabihestefan@google.com>
---
docs/system/arm/nuvoton.rst | 2 ++
hw/arm/npcm7xx.c | 3 ++-
include/hw/arm/npcm7xx.h | 1 +
3 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst index 0424cae4b0..e611099545 100644
--- a/docs/system/arm/nuvoton.rst
+++ b/docs/system/arm/nuvoton.rst
@@ -50,6 +50,8 @@ Supported devices
* Ethernet controller (EMC)
* Tachometer
* Peripheral SPI controller (PSPI)
+ * BIOS POST code FIFO
+ * PCI Mailbox
Missing devices
---------------
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c index c69e936669..c9e87162cb 100644
--- a/hw/arm/npcm7xx.c
+++ b/hw/arm/npcm7xx.c
@@ -86,7 +86,6 @@ enum NPCM7xxInterrupt {
NPCM7XX_UART1_IRQ,
NPCM7XX_UART2_IRQ,
NPCM7XX_UART3_IRQ,
- NPCM7XX_PECI_IRQ = 6,
NPCM7XX_PCI_MBOX_IRQ = 8,
NPCM7XX_KCS_HIB_IRQ = 9,
NPCM7XX_GMAC1_IRQ = 14,
@@ -463,6 +462,8 @@ static void npcm7xx_init(Object *obj)
object_initialize_child(obj, "pspi[*]", &s->pspi[i], TYPE_NPCM_PSPI);
}
+ object_initialize_child(obj, "pci-mbox", &s->pci_mbox,
+ TYPE_NPCM7XX_PCI_MBOX);
object_initialize_child(obj, "mmc", &s->mmc, TYPE_NPCM7XX_SDHCI); }
diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h index 273090ac60..cec3792a2e 100644
--- a/include/hw/arm/npcm7xx.h
+++ b/include/hw/arm/npcm7xx.h
@@ -105,6 +105,7 @@ struct NPCM7xxState {
OHCISysBusState ohci;
NPCM7xxFIUState fiu[2];
NPCM7xxEMCState emc[2];
+ NPCM7xxPCIMBoxState pci_mbox;
NPCM7xxSDHCIState mmc;
NPCMPSPIState pspi[2];
};
--
2.42.0.820.g83a721a137-goog
Signed-off-by: Tyrone Ting <kfting@nuvoton.com>
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
________________________________
________________________________
The privileged confidential information contained in this email is intended for use only by the addressees as indicated by the original sender of this email. If you are not the addressee indicated in this email or are not responsible for delivery of the email to such a person, please kindly reply to the sender indicating this fact and delete all copies of it from your computer and network server immediately. Your cooperation is highly appreciated. It is advised that any unauthorized use of confidential information of Nuvoton is strictly prohibited; and any information in this email irrelevant to the official business of Nuvoton shall be deemed as neither given nor endorsed by Nuvoton.
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