Having opcodes always present means that we can remove some tests.
NOT and MOVCOND were *almost* always present anyway.

A close candidate is NOT.  The hiccup is s390x: except for the most
recent hardware revision, there is no single insn which can implement
the operation.

I experimented with replacements:

    i32: xilf r,-1             (6 bytes, requires R=X)
         lcr r,x; ahi r,-1     (6 bytes)
    i64: lcgr r,x; aghi r,-1   (8 bytes)

But both don't compare well with the current

         lghi tmp,-1           (4 bytes, shared)
         xgrk r,x,tmp          (4 bytes)

With the constant -1 managed by register allocation, it gets loaded
once and then reused between operations.

An alternative might be to assume the presence of all opcodes during
initial expansion and lower them later, after optimization.  I'm close
to doing just that for the more complex opcodes like deposit anyway,
because the expansion is too complex for the optimizer to do anything
sensible after constant propagation.


r~


Richard Henderson (6):
  tcg/mips: Split out tcg_out_setcond_int
  tcg/mips: Always implement movcond
  tcg: Remove TCG_TARGET_HAS_movcond_{i32,i64}
  tcg/mips: Implement neg opcodes
  tcg/loongarch64: Implement neg opcodes
  tcg: Remove TCG_TARGET_HAS_neg_{i32,i64}

 include/tcg/tcg-op-common.h      |  12 +-
 include/tcg/tcg-opc.h            |   8 +-
 include/tcg/tcg.h                |   2 -
 tcg/aarch64/tcg-target.h         |   4 -
 tcg/arm/tcg-target.h             |   2 -
 tcg/i386/tcg-target.h            |   4 -
 tcg/loongarch64/tcg-target.h     |   4 -
 tcg/mips/tcg-target.h            |   4 -
 tcg/ppc/tcg-target.h             |   4 -
 tcg/riscv/tcg-target.h           |   4 -
 tcg/s390x/tcg-target.h           |   4 -
 tcg/sparc64/tcg-target.h         |   4 -
 tcg/tci/tcg-target.h             |   4 -
 tcg/optimize.c                   |  15 +-
 tcg/tcg-op.c                     |  60 ++---
 tcg/tcg.c                        |  12 +-
 tcg/tci.c                        |   2 -
 tcg/loongarch64/tcg-target.c.inc |   9 +
 tcg/mips/tcg-target.c.inc        | 383 +++++++++++++------------------
 19 files changed, 192 insertions(+), 349 deletions(-)

-- 
2.34.1

On 10/25/23 21:13, Richard Henderson wrote:
> Having opcodes always present means that we can remove some tests.
> NOT and MOVCOND were *almost* always present anyway.
> 
> A close candidate is NOT.  The hiccup is s390x: except for the most
> recent hardware revision, there is no single insn which can implement
> the operation.
> 
> I experimented with replacements:
> 
>      i32: xilf r,-1             (6 bytes, requires R=X)
>           lcr r,x; ahi r,-1     (6 bytes)
>      i64: lcgr r,x; aghi r,-1   (8 bytes)
> 
> But both don't compare well with the current
> 
>           lghi tmp,-1           (4 bytes, shared)
>           xgrk r,x,tmp          (4 bytes)
> 
> With the constant -1 managed by register allocation, it gets loaded
> once and then reused between operations.
> 
> An alternative might be to assume the presence of all opcodes during
> initial expansion and lower them later, after optimization.  I'm close
> to doing just that for the more complex opcodes like deposit anyway,
> because the expansion is too complex for the optimizer to do anything
> sensible after constant propagation.

Oh, for the record,

Based-on: 20231025072707.833943-1-richard.henderson@linaro.org
("tcg: Introduce TCG_COND_TST{EQ,NE}")


r~