Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sparc/insns.decode | 1 +
target/sparc/translate.c | 41 +++++++++++++++++++++------------------
2 files changed, 23 insertions(+), 19 deletions(-)
diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
index 0e29629b5c..42d740ad44 100644
--- a/target/sparc/insns.decode
+++ b/target/sparc/insns.decode
@@ -277,6 +277,7 @@ FABSd 10 ..... 110100 00000 0 0000 1010 ..... @r_r2
FMUL8ULx16 10 ..... 110110 ..... 0 0011 0111 ..... @r_r_r
FMULD8SUx16 10 ..... 110110 ..... 0 0011 1000 ..... @r_r_r
FMULD8ULx16 10 ..... 110110 ..... 0 0011 1001 ..... @r_r_r
+ PDIST 10 ..... 110110 ..... 0 0011 1110 ..... @r_r_r
FPMERGE 10 ..... 110110 ..... 0 0100 1011 ..... @r_r_r
FEXPAND 10 ..... 110110 ..... 0 0100 1101 ..... @r_r_r
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 35fdcfe4c1..40ef395d14 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -72,6 +72,7 @@
# define gen_helper_fmuld8sux16 ({ qemu_build_not_reached(); NULL; })
# define gen_helper_fmuld8ulx16 ({ qemu_build_not_reached(); NULL; })
# define gen_helper_fpmerge ({ qemu_build_not_reached(); NULL; })
+# define gen_helper_pdist ({ qemu_build_not_reached(); NULL; })
# define FSR_LDXFSR_MASK 0
# define FSR_LDXFSR_OLDMASK 0
# define MAXTL_MASK 0
@@ -1680,21 +1681,6 @@ static void gen_gsr_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2,
gen_store_fpr_D(dc, rd, dst);
}
-
-static void gen_ne_fop_DDDD(DisasContext *dc, int rd, int rs1, int rs2,
- void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64))
-{
- TCGv_i64 dst, src0, src1, src2;
-
- src1 = gen_load_fpr_D(dc, rs1);
- src2 = gen_load_fpr_D(dc, rs2);
- src0 = gen_load_fpr_D(dc, rd);
- dst = gen_dest_fpr_D(dc, rd);
-
- gen(dst, src0, src1, src2);
-
- gen_store_fpr_D(dc, rd, dst);
-}
#endif
static void gen_fop_QQ(DisasContext *dc, int rd, int rs,
@@ -4903,6 +4889,26 @@ TRANS(FXNORd, VIS1, do_ddd, a, tcg_gen_eqv_i64)
TRANS(FORNOTd, VIS1, do_ddd, a, tcg_gen_orc_i64)
TRANS(FORd, VIS1, do_ddd, a, tcg_gen_or_i64)
+static bool do_dddd(DisasContext *dc, arg_r_r_r *a,
+ void (*func)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64))
+{
+ TCGv_i64 dst, src0, src1, src2;
+
+ if (gen_trap_ifnofpu(dc)) {
+ return true;
+ }
+
+ dst = gen_dest_fpr_D(dc, a->rd);
+ src0 = gen_load_fpr_D(dc, a->rd);
+ src1 = gen_load_fpr_D(dc, a->rs1);
+ src2 = gen_load_fpr_D(dc, a->rs2);
+ func(dst, src0, src1, src2);
+ gen_store_fpr_D(dc, a->rd, dst);
+ return advance_pc(dc);
+}
+
+TRANS(PDIST, VIS1, do_dddd, a, gen_helper_pdist)
+
#define CHECK_IU_FEATURE(dc, FEATURE) \
if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
goto illegal_insn;
@@ -5312,6 +5318,7 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
case 0x039: /* VIS I fmuld8ulx16 */
case 0x04b: /* VIS I fpmerge */
case 0x04d: /* VIS I fexpand */
+ case 0x03e: /* VIS I pdist */
g_assert_not_reached(); /* in decodetree */
case 0x020: /* VIS I fcmple16 */
CHECK_FPU_FEATURE(dc, VIS1);
@@ -5387,10 +5394,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
gen_helper_fpackfix(cpu_dst_32, cpu_gsr, cpu_src1_64);
gen_store_fpr_F(dc, rd, cpu_dst_32);
break;
- case 0x03e: /* VIS I pdist */
- CHECK_FPU_FEATURE(dc, VIS1);
- gen_ne_fop_DDDD(dc, rd, rs1, rs2, gen_helper_pdist);
- break;
case 0x048: /* VIS I faligndata */
CHECK_FPU_FEATURE(dc, VIS1);
gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_faligndata);
--
2.34.1